Dac with common mode level and method for generating a common mode level

Abstract

The application provides a digital-to-analog conversion circuit with a common-mode level and a DAC, which comprises a common-mode sub-circuit, a first resistor, a second resistor, a common-mode module, N current modules and N first switch modules; control ends of the N first switch modules serve as input ends of the digital-to-analog conversion circuit, output ends of the N current modules are connected to first ends of the N first switch modules in correspondence, second ends of the N first switch modules are connected to a first end of the common-mode sub-circuit, a second end of the common-mode sub-circuit is connected to a first end of the common-mode module through the first resistor, a third end of the common-mode sub-circuit is connected to the first end of the common-mode module through the second resistor, a second end of the common-mode module is grounded, the second end of the common-mode sub-circuit serves as a first output end of the digital-to-analog conversion circuit, and the third end of the common-mode sub-circuit serves as a second output end of the digital-to-analog conversion circuit. The embodiment of the application can save power consumption and improve the linearity of the DAC.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a digital-to-analog conversion circuit with common-mode level and DAC. BACKGROUND

[0002] A digital-to-analog converter (DAC) can realize the function of converting discrete digital signals into continuous analog signals, and convert the input digital code value into analog signal output in proportion. The main application of DAC is to receive binary code generated by digital system, control DAC output analog quantity, and then input to analog system through amplifier; another main application field of DAC is calibration, which compensates parameters such as voltage and current bias; high-speed and high-precision DAC can also be directly used in the field of digital frequency synthesis. For DAC, no matter whether the decoding switch of DAC is opened or closed, the output of DAC usually needs a common-mode DC bias.

[0003] At present, a series of common-on common-mode current sources are usually added to drive the resistance load to generate a common-mode level as a common-mode DC bias. The addition of a series of common-mode current sources also increases the additional current power consumption. If the power consumption is to be reduced, the current size of the common-mode current source needs to be reduced, and the resistance value of the resistance load needs to be increased to achieve the same common-mode level.

[0004] However, reducing the current of the common-mode current source will make each current step of the DAC smaller, thereby reducing the signal-to-noise ratio of the DAC, resulting in low linearity of the DAC. SUMMARY

[0005] The present application provides a digital-to-analog conversion circuit with common-mode level and DAC to solve the problem of low linearity of DAC in the prior art.

[0006] The present application provides a digital-to-analog conversion circuit with common-mode level, comprising a common-mode sub-circuit, a first resistor, a second resistor, a common-mode module, N current modules and N first switch modules; wherein N = 2 n -1, n is the input bit number of the decoder connected to the input end of the digital-to-analog conversion circuit;

[0007] The control end of the N first switch modules is used as an input end of the digital-to-analog conversion circuit, the output end of the N current modules is connected to the first end of the N first switch modules correspondingly, the second end of the N first switch modules is connected to the first end of the common-mode sub-circuit, the second end of the common-mode sub-circuit is connected to the first end of the common-mode module through the first resistor, the third end of the common-mode sub-circuit is connected to the first end of the common-mode module through the second resistor, the second end of the common-mode module is grounded, the second end of the common-mode sub-circuit is used as a first output end of the digital-to-analog conversion circuit, and the third end of the common-mode sub-circuit is used as a second output end of the digital-to-analog conversion circuit.

[0008] The first switch module is used for turning on the first end and the second end of the first switch module when the first level from the decoder is received.

[0009] According to the application, a digital-to-analog conversion circuit with a common-mode level is provided.

[0010] The first end of the second switch module is used as the first end of the common-mode sub-circuit, the second end of the second switch module is used as the second end of the common-mode sub-circuit, the first end of the third switch module is connected to the first end of the second switch module, the second end of the third switch module is used as the third end of the common-mode sub-circuit, and the output end of the control module is connected to the control end of the second switch module and the control end of the third switch module respectively.

[0011] The control module is used for controlling the second switch module to turn on the first end and the second end of the second switch module and controlling the third switch module to turn on the first end and the second end of the third switch module.

[0012] According to the application, a digital-to-analog conversion circuit with a common-mode level is provided.

[0013] The source / drain of the first MOS tube is used as the first end of the second switch module, the drain / source of the first MOS tube is used as the second end of the second switch module, the gate of the first MOS tube is used as the control end of the second switch module, the source / drain of the second MOS tube is used as the first end of the third switch module, the drain / source of the second MOS tube is used as the second end of the third switch module, and the gate of the second MOS tube is used as the control end of the third switch module.

[0014] The control module is specifically used for controlling the first MOS tube and the second MOS tube to turn on.

[0015] The digital-to-analog conversion circuit with a common-mode level further comprises a differential-mode sub-circuit;

[0016] The third end of the N first switch modules is connected to the first end of the differential-mode sub-circuit, the second end of the differential-mode sub-circuit is connected to the first end of the common-mode module through the first resistor, the third end of the differential-mode sub-circuit is connected to the first end of the common-mode module through the second resistor, the second end of the differential-mode sub-circuit is further connected to the second end of the common-mode sub-circuit, and the third end of the differential-mode sub-circuit is further connected to the third end of the common-mode sub-circuit.

[0017] The first switch module is further configured to turn on the first end and the second end of the first switch module and turn off the first end and the third end of the first switch module when receiving a first level from the decoder, and turn off the first end and the second end of the first switch module and turn on the first end and the third end of the first switch module when receiving a second level from the decoder, wherein the first level is different from the second level.

[0018] The digital-to-analog conversion circuit with a common-mode level further comprises a differential-mode sub-circuit comprising a fourth switch module and a fifth switch module.

[0019] The first end of the fourth switch module serves as the first end of the differential-mode sub-circuit, the second end of the fourth switch module serves as the second end of the differential-mode sub-circuit, the first end of the fifth switch module is connected to the first end of the fourth switch module, the second end of the fifth switch module serves as the third end of the differential-mode sub-circuit, and the output end of the control module is connected to the control end of the fourth switch module and the control end of the fifth switch module, respectively.

[0020] The control module is further configured to control the fifth switch module to turn off the first end and the second end of the fifth switch module when controlling the fourth switch module to turn on the first end and the second end of the fourth switch module, and control the fifth switch module to turn on the first end and the second end of the fifth switch module when controlling the fourth switch module to turn off the first end and the second end of the fourth switch module.

[0021] The fourth switch module comprises a third MOS tube, and the fifth switch module comprises a fourth MOS tube.

[0022] The source / drain of the third MOS tube is the first end of the fourth switch module, the drain / source of the third MOS tube is the second end of the fourth switch module, the gate of the third MOS tube is the control end of the fourth switch module, the source / drain of the fourth MOS tube is the first end of the fifth switch module, the drain / source of the fourth MOS tube is the second end of the fifth switch module, and the gate of the fourth MOS tube is the control end of the fifth switch module.

[0023] The control module is also specifically used for controlling the fourth MOS tube to be turned off when the third MOS tube is controlled to be turned on, and controlling the fourth MOS tube to be turned on when the third MOS tube is controlled to be turned off.

[0024] According to the application, the digital-to-analog conversion circuit with common-mode level further comprises a normally-on current source, and the output end of the normally-on current source is connected to the first end of the common-mode sub-circuit and the first end of the differential-mode sub-circuit respectively.

[0025] According to the application, the digital-to-analog conversion circuit with common-mode level further comprises a normally-on current source, and the output end of the normally-on current source is connected to the first end of the common-mode sub-circuit and the first end of the differential-mode sub-circuit respectively.

[0026] According to the application, the digital-to-analog conversion circuit with common-mode level further comprises a normally-on current source, and the output end of the normally-on current source is connected to the first end of the common-mode sub-circuit and the first end of the differential-mode sub-circuit respectively.

[0027] The output end of the bias current source is connected to the drain / source of the first PMOS tube, the source / drain of the first PMOS tube is connected to the source / drain of the second PMOS tube, the drain / source of the second PMOS tube is the output end of the current module, the drain / source of the first PMOS tube is also connected to the gate of the first PMOS tube, the gate of the first PMOS tube is also connected to the gate of the second PMOS tube, and the output end of the voltage source is connected to the source / drain of the first PMOS tube.

[0028] The application further provides a digital-to-analog converter (DAC) comprising a decoder and the digital-to-analog conversion circuit with common-mode level.

[0029] The application provides a digital-to-analog conversion circuit with a common-mode level and a DAC. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0031] Figure 1 FIG. 1 is a structural schematic diagram of a digital-to-analog conversion circuit with a common-mode level provided by the application;

[0032] Figure 2 FIG. 2 is a schematic diagram of a DAC in the prior art;

[0033] Figure 3 FIG. 3 is a structural schematic diagram of a current steering DAC in the prior art;

[0034] Figure 4 FIG. 4 is a structural schematic diagram of a common-mode level DAC in the prior art;

[0035] Figure 5 FIG. 5 is a structural schematic diagram of a digital-to-analog conversion circuit with a common-mode level provided by the application;

[0036] Figure 6 FIG. 6 is a structural schematic diagram of a digital-to-analog conversion circuit with a common-mode level provided by the application.

[0037] Reference signs:

[0038] 100: digital-to-analog conversion circuit with a common-mode level; 200: decoder;

[0039] 101: common-mode sub-circuit;

[0040] 102: common-mode module;

[0041] 103: current module; I_bias: bias current source; Vdd: voltage source;

[0042] 104: first switch module;

[0043] 105: differential-mode sub-circuit;

[0044] 106: a constant current source;

[0045] R1: a first resistor; R2: a second resistor; R3: a common mode resistor; Q1: a first MOS transistor; Q2: a second MOS transistor; Q3: a third MOS transistor; Q4: a fourth MOS transistor; Q5: a first PMOS transistor; Q6: a second PMOS transistor. DETAILED DESCRIPTION

[0046] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0047] The digital-to-analog conversion circuit with a common mode level and the DAC of the present application will be described below with reference to the drawings.

[0048] Figure 1 is one of the structural schematic diagrams of the digital-to-analog conversion circuit with a common mode level provided by the present application, as shown in Figure 1 The digital-to-analog conversion circuit with a common mode level 100 comprises:

[0049] a common mode sub-circuit 101, a first resistor R1, a second resistor R2, a common mode module 102, N current modules 103 and N first switch modules 104; wherein N=2 n -1, n is the input bit number of a decoder (DECODE) 200 connected to the input end of the digital-to-analog conversion circuit.

[0050] For example, if the input bit number of the decoder 200 is 6 bits (sel<5:0>: sel<0> to sel<5>), N=2 6 -1=63, 63 current modules 103 and 63 first switch modules 104 need to be set, and the 63 current modules 103 correspond to one first switch module 104 respectively, and the decoder 200 can control the conduction state of the 63 first switch modules 104 to correspond to different thermal codes obtained by decoding the binary code sel<5:0>. Figure 1 The input of the decoder 200 is taken as an example of sel<0> to sel<5>.

[0051] The circuit connection structure of the digital-to-analog conversion circuit with a common mode level 100 is as follows:

[0052] The control end of the N first switch modules 104 is an input end in of the digital-to-analog conversion circuit 100, the output end of the N current modules 103 is connected to the first end of the N first switch modules 104 in correspondence, the second end of the N first switch modules 104 is connected to the first end of the common-mode sub-circuit 101, the second end of the common-mode sub-circuit 101 is connected to the first end of the common-mode module 102 through the first resistor R1, the third end of the common-mode sub-circuit 101 is connected to the first end of the common-mode module 102 through the second resistor R2, the second end of the common-mode module 102 is grounded, the second end of the common-mode sub-circuit 101 is a first output end outb of the digital-to-analog conversion circuit 100, and the third end of the common-mode sub-circuit 101 is a second output end out of the digital-to-analog conversion circuit 100.

[0053] The related art will be described below:

[0054] Figure 2 is a schematic diagram of a DAC in the related art, as shown in Figure 2 , the DAC can convert an input digital signal into an analog signal for output.

[0055] Figure 3 is a structure schematic diagram of a current steering DAC in the related art, as shown in Figure 3 , the main body is composed of a series of weighted current sources (powered by Vdd) and corresponding switches, after decoding the binary symbols (b_0 to b_n-1) input to the decoder, the decoder can control the current source to be turned on or turned off, and after the switch is turned on, the current source drives the load resistor R to make the output voltage V_out rise.

[0056] According to different decoding modes of the decoder, it can be divided into three different structures: binary decoding, thermometer decoding and segmented decoding structure.

[0057] Figure 4 is a structure schematic diagram of a common-mode level DAC in the related art, as shown in Figure 4 , the common-mode level DAC in the related art increases a series of common-mode current sources (I_extra) to drive the resistor R to generate a common-mode level as a common-mode DC bias of the DAC output. The specific decoder can control whether out and outb output a differential mode level or a common-mode level by controlling the on sel or selb.

[0058] It can be understood that increasing a series of normally open common mode current sources increases additional current power consumption. If the current size of the common mode current source needs to be reduced in order to reduce power consumption, but in order to achieve the same common mode level, the resistance value of the resistor R needs to be increased accordingly, and in order to output a current value of the same size step, the current value of each step will be reduced, which will affect the accuracy of a normal step. The smaller each step of the current is, the lower the signal-to-noise ratio is, which will result in poorer linearity of the DAC.

[0059] To solve the above problems, the embodiment of the present application provides a digital-to-analog conversion circuit with a common mode level, which can realize digital-to-analog conversion with low power consumption. Compared with the traditional method of generating a common mode level on a resistor by additionally increasing a common mode current source, the embodiment of the present application does not need to additionally increase the common mode current source, but can directly use the current source controlled by the existing code switch (i.e. the first switch module in the present application) to generate the common mode level, and adds a common mode sub-circuit and a common mode module. The present application can save power consumption while ensuring high linearity of the DAC.

[0060] Specifically, in the embodiment of the present application, the decoder can decode the control signal based on the input binary code after receiving the input binary code, to control the conduction state of the N first switch modules. Specifically, the decoder can output a first level to the control end of the first switch module, and the first switch module is turned on at the first end and the second end of the first switch module in the case of receiving the first level from the decoder. At this time, the first switch module connects the corresponding current module and the common mode sub-circuit, so as to supply power to the common mode module by the current module through the common mode sub-circuit, and finally generate the common mode level by the common mode module as the common mode direct current bias.

[0061] In the digital-to-analog conversion circuit with a common mode level provided by the embodiment of the present application, compared with the method of generating a common mode level on a resistor by using an additional common mode current source in the related art, the embodiment of the present application does not need to additionally increase the common mode current source, but directly uses the existing first switch module to control the current module to generate the common mode level on the common mode module through the common mode sub-circuit. The power consumption can be saved while ensuring that the current step of the DAC using the digital-to-analog conversion circuit with a common mode level is not too small, and the linearity of the DAC can be improved.

[0062] Optionally, the digital-to-analog conversion circuit 100 further includes a control module, which is not shown in the following figure and related connection structure, and the common mode sub-circuit 101 includes a second switch module and a third switch module.

[0063] The first end of the second switch module is the first end of the common mode sub-circuit 101, the second end of the second switch module is the second end of the common mode sub-circuit 101, the first end of the third switch module is connected to the first end of the second switch module, the second end of the third switch module is the third end of the common mode sub-circuit 101, and the output ends of the control module are connected to the control ends of the second switch module and the third switch module respectively.

[0064] The control module is configured to control the second switch module to turn on the first end and the second end of the second switch module, and control the third switch module to turn on the first end and the second end of the third switch module.

[0065] Specifically, the common mode sub-circuit can include the second switch module and the third switch module, and the control module can control the second switch module and the third switch module to always be in the on state (normally open state) in the normal state, so as to connect the current module with the common mode module and output the common mode level.

[0066] In one embodiment, the first end and the second end of the common mode sub-circuit, and the first end and the third end of the common mode sub-circuit are connected by wires.

[0067] In the embodiment of the application, by arranging the second switch module and the third switch module, the situation that the first switch module cannot work normally due to the direct connection of the first switch module to the first output end and the second output end of the digital-to-analog conversion circuit through wires can be avoided, and the stability of the working of the first switch module can be improved.

[0068] Optionally, Figure 5 is a structural diagram of a digital-to-analog conversion circuit with a common mode level provided by the application, as Figure 5 As shown in the figure, the second switch module includes a first MOS tube Q1, and the third switch module includes a second MOS tube Q2.

[0069] The source / drain of the first MOS tube Q1 is the first end of the second switch module, the drain / source of the first MOS tube Q1 is the second end of the second switch module, the gate of the first MOS tube Q1 is the control end of the second switch module, the source / drain of the second MOS tube Q2 is the first end of the third switch module, the drain / source of the second MOS tube Q2 is the second end of the third switch module, and the gate of the second MOS tube Q2 is the control end of the third switch module.

[0070] The control module is specifically configured to control the first MOS tube Q1 and the second MOS tube Q2 to turn on.

[0071] Specifically, the second switch module can be implemented by a first MOS tube, and the third switch module can be implemented by a second MOS tube. The control module outputs a control signal lo to the gate of the first MOS tube and the second MOS tube, so that the first MOS tube and the second MOS tube are always in an on state (always on state) in a normal state.

[0072] Optionally, the first MOS tube Q1 and the second MOS tube Q2 can be both NMOS tubes, or both PMOS tubes. Figure 5 For example, the first MOS tube Q1 and the second MOS tube Q2 are both PMOS tubes.

[0073] Optionally, as shown in Figure 5 The digital-to-analog conversion circuit 100 further includes a differential mode sub-circuit 105;

[0074] The third end of the N first switch modules 104 is connected to the first end of the differential mode sub-circuit 105. The second end of the differential mode sub-circuit 105 is connected to the first end of the common mode module 102 through the first resistor R1. The third end of the differential mode sub-circuit 105 is connected to the first end of the common mode module 102 through the second resistor R2. The second end of the differential mode sub-circuit 105 is also connected to the second end of the common mode sub-circuit 101. The third end of the differential mode sub-circuit 105 is also connected to the third end of the common mode sub-circuit 101.

[0075] The first switch module 104 is further configured to: in the case of receiving a first level from the decoder 200, turn on the first end and the second end of the first switch module 104, and turn off the first end and the third end of the first switch module 104; in the case of receiving a second level from the decoder 200, turn off the first end and the second end of the first switch module 104, and turn on the first end and the third end of the first switch module 104; wherein the first level is different from the second level.

[0076] Specifically, the digital-to-analog conversion circuit with a common mode level can further include a differential mode sub-circuit for generating a differential mode level.

[0077] The decoder can decode the control signal based on the input binary code after receiving the input binary code, so as to control the on state of the N first switch modules, and control whether each first switch module outputs a differential mode level or a common mode level. Specifically, the decoder can output a first level or a second level to the control end of each first switch module. It should be noted that the first level and the second level are different levels, for example, the first level is a high level, and the second level is a low level.

[0078] The first switch module, in a case of receiving the first level, turns on the first end and the second end of the first switch module and turns off the first end and the third end of the first switch module, at this time, the first switch module connects the corresponding current module and the common-mode sub-circuit and disconnects the corresponding current module and the differential-mode sub-circuit; the first switch module, in a case of receiving the second level, turns off the first end and the second end of the first switch module and turns on the first end and the third end of the first switch module, at this time, the first switch module disconnects the corresponding current module and the common-mode sub-circuit and connects the corresponding current module and the differential-mode sub-circuit.

[0079] Optionally, the first switch module can include two switch tubes, the two switch tubes are connected between the first end and the second end of the first switch module and between the first end and the third end of the first switch module, the switch tube is, for example, a controllable thyristor, a MOS tube or the like, and the two switch tubes are controlled by the decoder to only turn on one switch tube at the same time.

[0080] Optionally, as shown in Figure 5 the differential-mode sub-circuit 105 includes a fourth switch module and a fifth switch module;

[0081] The first end of the fourth switch module serves as the first end of the differential-mode sub-circuit 105, the second end of the fourth switch module serves as the second end of the differential-mode sub-circuit 105, the first end of the fifth switch module is connected to the first end of the fourth switch module, the second end of the fifth switch module serves as the third end of the differential-mode sub-circuit 105, and the output end of the control module is connected to the control end of the fourth switch module and the control end of the fifth switch module respectively;

[0082] The control module is further configured to control the fifth switch module to turn off the first end and the second end of the fifth switch module in a case of controlling the fourth switch module to turn on the first end and the second end of the fourth switch module, and control the fifth switch module to turn on the first end and the second end of the fifth switch module in a case of controlling the fourth switch module to turn off the first end and the second end of the fourth switch module.

[0083] Specifically, the differential-mode sub-circuit can include a fourth switch module and a fifth switch module, the control module can control the fifth switch module to turn off the first end and the second end of the fifth switch module in a case of controlling the fourth switch module to turn on the first end and the second end of the fourth switch module, at this time, the voltage of the first output end outb of the digital-to-analog conversion circuit will gradually be higher than the voltage of the second output end out of the digital-to-analog conversion circuit with the increase of the number of the first switch module turned on, resulting in that the voltage of out is lower than the voltage of outb, and further resulting in that the output level V_out-V_outb of the digital-to-analog conversion circuit is negative.

[0084] In a case that the fourth switch module is controlled to turn off the first end and the second end of the fourth switch module, the fifth switch module is controlled to turn on the first end and the second end of the fifth switch module, at this time, the voltage of the second output end out of the digital-to-analog conversion circuit will gradually be higher than the voltage of the first output end outb of the digital-to-analog conversion circuit with the increase of the number of the turned-on first switch modules, resulting in that the voltage of outb is lower than the voltage of out, and further resulting in that the output level V_out-V_outb of the digital-to-analog conversion circuit is positive.

[0085] Optionally, the highest bit sel<6> of the binary code and the result selb<6> of the inversion of sel<6> can be used as control signals for controlling the turned-on state of the fourth switch module and the fifth switch module respectively.

[0086] Optionally, as shown in Figure 5 the fourth switch module includes a third MOS tube Q3, and the fifth switch module includes a fourth MOS tube Q4;

[0087] the source / drain of the third MOS tube Q3 is used as the first end of the fourth switch module, the drain / source of the third MOS tube Q3 is used as the second end of the fourth switch module, the gate of the third MOS tube Q3 is used as the control end of the fourth switch module, the source / drain of the fourth MOS tube Q4 is used as the first end of the fifth switch module, the drain / source of the fourth MOS tube Q4 is used as the second end of the fifth switch module, and the gate of the fourth MOS tube Q4 is used as the control end of the fifth switch module.

[0088] The control module is further configured to: control the fourth MOS tube Q4 to turn off in a case that the third MOS tube Q3 is controlled to turn on; and control the fourth MOS tube Q4 to turn on in a case that the third MOS tube Q3 is controlled to turn off.

[0089] Specifically, the fourth switch module can be implemented by a third MOS tube, the fifth switch module can be implemented by a fourth MOS tube, and the control module controls the third MOS tube and the fourth MOS tube to turn on only one at the same time through the gates of the third MOS tube and the fourth MOS tube.

[0090] Optionally, the third MOS tube Q3 and the fourth MOS tube Q4 can be both NMOS tubes, or both PMOS tubes. Figure 5 For example, the third MOS tube Q3 and the fourth MOS tube Q4 are both PMOS tubes.

[0091] For example, sel<6> is used for controlling the third MOS tube Q3, and selb<6> is used for controlling the fourth MOS tube Q4.

[0092] When the third MOS Q3 and the fourth MOS Q4 are both PMOS, the third MOS Q3 is turned on when the control signal is 0, and the third MOS Q3 is turned off when the control signal is 1;

[0093] When sel<6>=1 and selb<6>=0, the third MOS Q3 is turned off, and the fourth MOS Q4 is turned on, at this time, V_out-V_outb is positive;

[0094] When sel<6>=0 and selb<6>=1, the third MOS Q3 is turned on, and the fourth MOS Q4 is turned off, at this time, V_out-V_outb is negative.

[0095] In the embodiment of the present application, the control module can control the positive and negative of the differential mode level output by the digital-to-analog conversion circuit by controlling the conduction state of the third MOS and the fourth MOS, for example, in the case that the third MOS is turned on and the fourth MOS is turned off, the differential mode level V_out-V_outb output by the digital-to-analog conversion circuit is negative, and in the case that the third MOS is turned off and the fourth MOS is turned on, the differential mode level V_out-V_outb output by the digital-to-analog conversion circuit is positive.

[0096] Optionally, as shown in Figure 5 the digital-to-analog conversion circuit 100 can further include a constant-on current source 106, and the output end of the constant-on current source 106 is connected to the first end of the common mode sub-circuit 101 and the first end of the differential mode sub-circuit 105.

[0097] Specifically, the digital-to-analog conversion circuit with a common mode level can further include a constant-on current source, which is directly connected to the first end of the common mode sub-circuit and the first end of the differential mode sub-circuit, so as to avoid the layout asymmetry caused by only setting N current modules, and the embodiment of the present application sets one more constant-on current source, which can ensure the layout symmetrical arrangement.

[0098] For example, when n=6, N=63, setting 63 current modules will cause layout asymmetry, therefore, the present application sets one more constant-on current source, and a total of 64 current modules or current sources are set, which can ensure the layout symmetrical arrangement.

[0099] Optionally, as shown in Figure 5 the common mode module 102 can include a common mode resistance R3, the first end of the common mode resistance R3 serves as the first end of the common mode module 102, and the second end of the common mode resistance R3 serves as the second end of the common mode module 102.

[0100] Specifically, the common mode module can be implemented by the common mode resistance R3, and the resistance value of the common mode resistance R3 can be set according to the needs of the digital-to-analog conversion circuit to the common mode level.

[0101] Optionally, as shown in Figure 6 the current module 103 includes a bias current source I_bias, a voltage source Vdd, a first PMOS tube Q5 and a second PMOS tube Q6;

[0102] The output end of the bias current source I_bias is connected to the drain / source of the first PMOS tube Q5, the source / drain of the first PMOS tube Q5 is connected to the source / drain of the second PMOS tube Q6, the drain / source of the second PMOS tube Q6 serves as the output end of the current module 103, the drain / source of the first PMOS tube Q5 is also connected to the gate of the first PMOS tube Q5, the gate of the first PMOS tube Q5 is also connected to the gate of the second PMOS tube Q6, and the output end of the voltage source Vdd is connected to the source / drain of the first PMOS tube Q5.

[0103] Specifically, the current module can include a bias current source, a voltage source, a first PMOS tube and a second PMOS tube, and the working principle of the specific current module can be the working principle of the current mirror in the related art, which will not be described here.

[0104] It should be noted that the voltage source is used to provide energy for the current module;

[0105] For example, if the bias current source outputs a current I_bias = 12.5uA, the width-length ratio of the first PMOS tube can be set to four times the width-length ratio of the second PMOS tube, so that the output current I1 of the current module is 1 / 4 of 12.5uA, which is approximately equal to 3uA.

[0106] The following illustrates the digital-to-analog conversion circuit with common-mode level provided by the embodiment of the present application.

[0107] Figure 6 is a structure schematic diagram of the digital-to-analog conversion circuit with common-mode level provided by the present application, as shown in Figure 6 the digital-to-analog conversion circuit with common-mode level includes a common-mode sub-circuit, a differential-mode sub-circuit, a first resistor R1, a second resistor R2, a common-mode module, 63 current modules, 63 first switch modules and one always-on current source (a total of 64 current modules or current sources).

[0108] Among them, the common-mode sub-circuit includes a first MOS tube Q1 and a second MOS tube Q2, the differential-mode sub-circuit includes a third MOS tube Q3 and a fourth MOS tube Q4, the first MOS tube Q1, the second MOS tube Q2, the third MOS tube Q3 and the fourth MOS tube Q4 are all PMOS tubes; the common-mode module includes a common-mode resistor R3; the current module includes a bias current source I_bias, a voltage source Vdd, a first PMOS tube Q5 and a second PMOS tube Q6.

[0109] As ​ shown, the output level of the digital-to-analog conversion circuit is V_out-V_outb, the control word is composed of seven binary codes, the highest bit sel<6> is used to control the positive and negative of the output level, and the low six binary codes sel<5:0> are decoded as 63 hot codes, which are used to control the on-off of the first switch module corresponding to the 63 current modules, in order to realize the layout symmetry, the application adds a normally open current source. A total of 64 current modules or current sources are controlled by switches to select the current flow direction to the common mode sub-circuit or the differential mode sub-circuit, and the current of each current source is I1=3uA, so the total current I is:

[0110] I=I1*64=192uA;

[0111] The application also adds: differential mode resistors R1=500Ω and R2=500Ω, and common mode resistor R3=750Ω. Regardless of the on-off of the switch, the common mode level generated by the common mode resistor R3 on V_out and V_outb is:

[0112] I1*64*R3=144mV;

[0113] If all the current controlled by the switch flows into the common mode sub-circuit, the common mode level generated on each differential mode resistor R1 and R2 is:

[0114] I1*0.5*64*R1=48.75mV;

[0115] Adding the above two common mode levels, the common mode level on V_out and V_outb when all the switches are in the common mode end is about 200mV.

[0116] When a switch is in the differential mode end, a differential step (absolute value) is:

[0117] |V_out-V_outb|=|I1*R1|=1.5mV;

[0118] When all the switches are in the differential mode end, the maximum differential mode level generated is:

[0119] 1.5mV*64=96mV;

[0120] Therefore, the DAC corresponding to the digital-to-analog conversion circuit of the application can output a differential mode level in the range of 0-96mV, and because sel<6> and selb<6> can control the positive and negative of the output level, the total output range is:

[0121] V_out-V_outb∈-96mV~96mV.

[0122] The total current size of the embodiment of the present application is 200uA, if the traditional method is used, 350uA is needed to achieve the same performance, wherein there is an additional 150uA common mode current (generated by the additional common mode current source), it can be seen that the embodiment of the present application reduces the power consumption by 42.8%.

[0123] In another aspect, the present application also provides a DAC, the DAC comprising the digital-to-analog conversion circuit 100 with common mode level and the decoder 200 in the above embodiments.

[0124] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A digital-to-analog conversion circuit with common mode level, characterized by The N first switch modules are connected to the input end of the digital-to-analog conversion circuit, the outputs of the N current modules are connected to the first ends of the N first switch modules, the second ends of the N first switch modules are connected to the first end of the common-mode sub-circuit, the second end of the common-mode sub-circuit is connected to the first end of the common-mode module through the first resistor, the third end of the common-mode sub-circuit is connected to the first end of the common-mode module through the second resistor, the second end of the common-mode module is grounded, the second end of the common-mode sub-circuit is the first output end of the digital-to-analog conversion circuit, and the third end of the common-mode sub-circuit is the second output end of the digital-to-analog conversion circuit. A common mode sub-circuit, a first resistor, a second resistor, a common mode module, N current modules and N first switch modules; wherein, N=2 n -1, n is the input bit number of a decoder connected to the input end of the digital-analog conversion circuit; The first switch module is configured to turn on the first end and the second end of the first switch module when receiving a first level from the decoder. The digital-to-analog conversion circuit further comprises a differential-mode sub-circuit, the third end of the N first switch modules is connected to the first end of the differential-mode sub-circuit, the second end of the differential-mode sub-circuit is connected to the first end of the common-mode module through the first resistor, the third end of the differential-mode sub-circuit is connected to the first end of the common-mode module through the second resistor, the second end of the differential-mode sub-circuit is further connected to the second end of the common-mode sub-circuit, and the third end of the differential-mode sub-circuit is further connected to the third end of the common-mode sub-circuit. The first switch module is further configured to turn on the first end and the second end of the first switch module when receiving a first level from the decoder, and turn off the first end and the third end of the first switch module; and turn off the first end and the second end of the first switch module when receiving a second level from the decoder, and turn on the first end and the third end of the first switch module; wherein the first level is different from the second level. The digital-to-analog conversion circuit further comprises a control module, and the common-mode sub-circuit comprises a second switch module and a third switch module.

2. The digital-to-analog conversion circuit with common mode level according to claim 1, characterized in that, The first end of the second switch module is the first end of the common-mode sub-circuit, the second end of the second switch module is the second end of the common-mode sub-circuit, the first end of the third switch module is connected to the first end of the second switch module, the second end of the third switch module is the third end of the common-mode sub-circuit, and the output end of the control module is connected to the control end of the second switch module and the control end of the third switch module. The control module is configured to control the second switch module to turn on the first end and the second end of the second switch module, and control the third switch module to turn on the first end and the second end of the third switch module. The second switch module comprises a first MOS tube, and the third switch module comprises a second MOS tube.

3. The digital-to-analog conversion circuit with common mode level according to claim 2, characterized in that, ​ The source / drain of the first MOS transistor is the first end of the second switch module, the drain / source of the first MOS transistor is the second end of the second switch module, the gate of the first MOS transistor is the control end of the second switch module, the source / drain of the second MOS transistor is the first end of the third switch module, the drain / source of the second MOS transistor is the second end of the third switch module, and the gate of the second MOS transistor is the control end of the third switch module. The control module is specifically configured to control the first MOS transistor and the second MOS transistor to be turned on.

4. The digital-to-analog conversion circuit with common mode level according to claim 3, characterized in that, The differential mode sub-circuit comprises a fourth switch module and a fifth switch module. The first end of the fourth switch module is the first end of the differential mode sub-circuit, the second end of the fourth switch module is the second end of the differential mode sub-circuit, the first end of the fifth switch module is connected to the first end of the fourth switch module, the second end of the fifth switch module is the third end of the differential mode sub-circuit, and the output end of the control module is connected to the control end of the fourth switch module and the control end of the fifth switch module. The control module is further configured to control the fifth switch module to turn off the first end and the second end of the fifth switch module when the control module controls the fourth switch module to turn on the first end and the second end of the fourth switch module, and control the fifth switch module to turn on the first end and the second end of the fifth switch module when the control module controls the fourth switch module to turn off the first end and the second end of the fourth switch module.

5. The digital-to-analog conversion circuit with common mode level according to claim 4, characterized in that, The fourth switch module comprises a third MOS transistor, and the fifth switch module comprises a fourth MOS transistor. The source / drain of the third MOS transistor is the first end of the fourth switch module, the drain / source of the third MOS transistor is the second end of the fourth switch module, the gate of the third MOS transistor is the control end of the fourth switch module, the source / drain of the fourth MOS transistor is the first end of the fifth switch module, the drain / source of the fourth MOS transistor is the second end of the fifth switch module, and the gate of the fourth MOS transistor is the control end of the fifth switch module. The control module is further specifically configured to control the fourth MOS transistor to turn off when the control module controls the third MOS transistor to turn on, and control the fourth MOS transistor to turn on when the control module controls the third MOS transistor to turn off.

6. The digital-to-analog conversion circuit with common mode level according to claim 5, characterized in that, The digital-to-analog conversion circuit further comprises a normally-on current source, and the output end of the normally-on current source is connected to the first end of the common mode sub-circuit and the first end of the differential mode sub-circuit.

7. The digital-to-analog conversion circuit with common mode level according to any one of claims 1 to 6, characterized in that, The common mode module comprises a common mode resistor, the first end of the common mode resistor is the first end of the common mode module, and the second end of the common mode resistor is the second end of the common mode module.

8. The digital-to-analog conversion circuit with common mode level according to claim 7, characterized in that, The current module comprises a bias current source, a voltage source, a first PMOS transistor, and a second PMOS transistor. The output terminal of the bias current source is connected to the drain / source of the first PMOS transistor, the source / drain of the first PMOS transistor is connected to the source / drain of the second PMOS transistor, the drain / source of the second PMOS transistor is the output terminal of the current module, the drain / source of the first PMOS transistor is also connected to the gate of the first PMOS transistor, the gate of the first PMOS transistor is also connected to the gate of the second PMOS transistor, and the output terminal of the voltage source is connected to the source / drain of the first PMOS transistor.

9. A digital-to-analog converter (DAC), comprising: The D / A conversion circuit with common mode level comprises a decoder and a D / A conversion circuit as claimed in any one of claims 1 to 8.

Images