Display panel and display device

Abstract

A display panel and a display device are provided. The display panel includes: a pixel unit located on a substrate, including a pixel circuit and a light-emitting element, the pixel circuit including a driving transistor, a first reset transistor, and a second reset transistor, a first initialization signal line connected to a first pole of the first reset transistor, a first reset control signal line connected to a gate of the first reset transistor; a second initialization signal line connected to a first pole of the second reset transistor, a second pole of the second reset transistor being connected to a first pole of the light-emitting element and configured to reset the first pole of the light-emitting element, the first initialization signal line and the second initialization signal line being on the same layer and being on a different layer from the first reset control signal line, a positive projection of the first reset control signal line on the substrate being located between a positive projection of the first initialization signal line on the substrate and a positive projection of the second initialization signal line on the substrate.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, Active-Matrix Organic Light-Emitting Diode (AMOLED) display technology has been increasingly applied to display devices such as mobile phones, tablet computers, digital cameras, etc. due to its advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, high response speed, etc.

[0003] Under-screen camera technology is a brand-new technology proposed to increase the screen-to-body ratio of display devices. Summary of the Invention

[0004] At least one embodiment of the present disclosure relates to a display panel and a display device.

[0005] On the one hand, at least one embodiment of the present disclosure provides a display panel, including: a substrate; a pixel unit located on the substrate, including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit including a driving transistor, a first reset transistor, and a second reset transistor, the first reset transistor being connected to the driving transistor and configured to reset the gate of the driving transistor, a first initialization signal line connected to a first pole of the first reset transistor and configured to provide a first initialization signal to the pixel unit, a first reset control signal line connected to the gate of the first reset transistor; a second initialization signal line, a first pole of the second reset transistor being connected to the second initialization signal line, a second pole of the second reset transistor being connected to a first pole of the light-emitting element and configured to reset the first pole of the light-emitting element, the first initialization signal line and the second initialization signal line being located on the same layer and being located on a different layer from the first reset control signal line, a positive projection of the first reset control signal line on the substrate being located between a positive projection of the first initialization signal line on the substrate and a positive projection of the second initialization signal line on the substrate.

[0006] In some embodiments of the present disclosure, the display panel further includes a first power supply line and a first connection electrode. The first power supply line is configured to provide a constant first voltage signal to the pixel unit. The pixel circuit further includes a first light-emitting control transistor and a storage capacitor. A first pole of the storage capacitor is connected to a gate of the driving transistor, and a second pole of the storage capacitor is connected to the first power supply line through the first connection electrode. The first connection electrode is connected to a first pole of the first light-emitting control transistor through a first via, and the first connection electrode is connected to the second pole of the storage capacitor through a second via.

[0007] In some embodiments of the present disclosure, the display panel further includes a second connection electrode and a third connection electrode. The first power supply line is connected to the first connection electrode through a third via. The pixel circuit further includes a second light-emitting control transistor. A first pole of the second light-emitting control transistor is connected to the driving transistor. The third connection electrode is connected to the second connection electrode through a fourth via. The second connection electrode is connected to a second pole of the second light-emitting control transistor through a fifth via. The fourth via and the third via are arranged along the first direction.

[0008] In some embodiments of the present disclosure, a distance from the fourth via to the first initialization signal line is equal to a distance from the third via to the first initialization signal line.

[0009] In some embodiments of the present disclosure, the display panel further includes a fourth connection electrode and a shielding electrode. A gate of the driving transistor is connected to a second pole of the first reset transistor through the fourth connection electrode. The shielding electrode and the first power supply line are of an integral structure. A positive projection of the shielding electrode on the substrate covers a positive projection of the fourth connection electrode on the substrate.

[0010] In some embodiments of the present disclosure, the fourth connection electrode is connected to the second pole of the first reset transistor through a sixth via. A positive projection of the shielding electrode on the substrate covers a positive projection of the sixth via on the substrate.

[0011] In some embodiments of the present disclosure, a positive projection of the shielding electrode on the substrate and a positive projection of the second pole of the first reset transistor on the substrate at least partially overlap.

[0012] In some embodiments of the present disclosure, the display panel further includes a data line. The data line is configured to provide a data signal to the pixel unit. The data line and the first power supply line are located on the same layer.

[0013] In some embodiments of the present disclosure, the display panel further includes a stopper and a fifth connection electrode. The pixel circuit further includes a threshold compensation transistor. The threshold compensation transistor includes a first channel, a second channel, and a conductive connection portion connecting the first channel and the second channel. The fifth connection electrode is connected to the first power supply line through a seventh via hole. The fifth connection electrode is connected to the stopper. At least a part of the orthographic projection of the stopper on the substrate overlaps with the orthographic projection of the conductive connection portion on the substrate. The stopper is configured to block the conductive connection portion of the pixel unit at its position.

[0014] In some embodiments of the present disclosure, the display panel further includes a sixth connection electrode. The pixel circuit further includes a data writing transistor. The data line is connected to the data writing transistor through the sixth connection electrode. The sixth connection electrode is connected to the data line through an eighth via hole. The seventh via hole and the eighth via hole are arranged along the first direction.

[0015] In some embodiments of the present disclosure, the distance from the seventh via hole to the first initialization signal line is equal to the distance from the eighth via hole to the first initialization signal line.

[0016] In some embodiments of the present disclosure, the data line includes a first data line and a second data line. The first data line extends along a second direction. The second data line includes a first part extending along the first direction. The first part of the second data line is located between the first initialization signal line and the sixth connection electrode.

[0017] In some embodiments of the present disclosure, the display panel further includes a seventh connection electrode. The first initialization signal line is connected to the first pole of the first reset transistor through the seventh connection electrode. The seventh connection electrode is connected to the first initialization signal line through a ninth via hole. The seventh connection electrode is connected to the first pole of the first reset transistor through a tenth via hole. The first initialization signal line extends along the first direction. The seventh connection electrode is inclined with respect to the first initialization signal line.

[0018] In some embodiments of the present disclosure, the included angle between the extending direction of the seventh connection electrode and the extending direction of the first initialization signal line is an acute angle.

[0019] In some embodiments of the present disclosure, the included angle is greater than or equal to 30 degrees and less than or equal to 60 degrees.

[0020] In some embodiments of the present disclosure, the first reset transistor includes a first channel and a second channel, and the central connection lines of the ninth via, the first channel, and the second channel form an acute triangle, and the central connection lines of the tenth via, the first channel, and the second channel form an obtuse triangle.

[0021] In some embodiments of the present disclosure, the first initialization signal line includes a first overlapping portion overlapping with the first pole of the first reset transistor and a second overlapping portion overlapping with the second pole of the first reset transistor, and the ninth via is located between the first overlapping portion and the second overlapping portion.

[0022] In some embodiments of the present disclosure, the orthographic projection of the ninth via on the substrate does not overlap with the orthographic projection of the first pole of the first reset transistor on the substrate, and does not overlap with the orthographic projection of the second pole of the first reset transistor on the substrate.

[0023] In some embodiments of the present disclosure, the ninth via and the tenth via are located on the same side of the first reset control signal line.

[0024] In some embodiments of the present disclosure, the first reset control signal line is located in the first conductive layer, the first initialization signal line and the second initialization signal line are located in the second conductive layer, the seventh connection electrode is located in the third conductive layer, the first conductive layer is closer to the substrate than the second conductive layer, and the second conductive layer is closer to the substrate than the third conductive layer.

[0025] In some embodiments of the present disclosure, the display panel further includes an eighth connection electrode, the eighth connection electrode is respectively connected to the second initialization signal line and the first pole of the second reset transistor, and the seventh connection electrode is inclined with respect to the eighth connection electrode.

[0026] In some embodiments of the present disclosure, the included angle between the extending direction of the seventh connection electrode and the extending direction of the eighth connection electrode is an acute angle.

[0027] In some embodiments of the present disclosure, the included angle between the extending direction of the seventh connection electrode and the extending direction of the eighth connection electrode is greater than or equal to 30 degrees and less than or equal to 60 degrees.

[0028] In some embodiments of the present disclosure, the ninth via and the eighth connection electrode are respectively disposed on opposite sides of the first pole of the first reset transistor.

[0029] In some embodiments of the present disclosure, the display panel includes a first display area and a second display area. The first display area is located on at least one side of the second display area. The pixel unit includes a first pixel unit and a second pixel unit. The pixel circuit and the light-emitting element of the first pixel unit are both located in the first display area. The pixel circuit of the second pixel unit is located in the first display area, and the light-emitting element of the second pixel unit is located in the second display area. The pixel circuit of the second pixel unit is connected to the light-emitting element of the second pixel unit through a conductive wire.

[0030] In some embodiments of the present disclosure, the orthographic projection of the conductive wire on the substrate overlaps partially with the orthographic projection of the pixel circuit of the first pixel unit on the substrate.

[0031] In some embodiments of the present disclosure, the orthographic projection of at least one of the eighth via hole, the seventh via hole, the fourth via hole, and the third via hole on the substrate does not overlap with the orthographic projection of the conductive wire on the substrate.

[0032] At least one embodiment of the present disclosure further provides a display device, including any of the above display panels.

[0033] On the other hand, at least one embodiment of the present disclosure provides a display panel, including: a substrate; a pixel unit located on the substrate, including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit including a driving transistor and a first reset transistor, the first reset transistor being connected to the driving transistor and being configured to reset the gate of the driving transistor; a first initialization signal line connected to a first pole of the first reset transistor and being configured to provide a first initialization signal to the pixel unit; a first connection electrode, the first initialization signal line being connected to the first pole of the first reset transistor through the first connection electrode, the first connection electrode being connected to the first initialization signal line through a first via hole, and the first connection electrode being connected to the first pole of the first reset transistor through a second via hole, the first initialization signal line extending in a first direction, and the first connection electrode being inclined with respect to the first initialization signal line.

[0034] In some embodiments, the included angle between the extending direction of the first connection electrode and the extending direction of the first initialization signal line is an acute angle.

[0035] In some embodiments, the included angle is greater than or equal to 30 degrees and less than or equal to 60 degrees.

[0036] In some embodiments, the first reset transistor includes a first channel and a second channel, and the central connection lines of the first via, the first channel, and the second channel form an acute triangle, and the central connection lines of the second via, the first channel, and the second channel form an obtuse triangle.

[0037] In some embodiments, the first initialization signal line includes a first overlapping portion overlapping with a first pole of the first reset transistor and a second overlapping portion overlapping with a second pole of the first reset transistor, and the first via is located between the first overlapping portion and the second overlapping portion.

[0038] In some embodiments, the orthographic projection of the first via on the substrate does not overlap with the orthographic projection of the first pole of the first reset transistor on the substrate, and does not overlap with the orthographic projection of the second pole of the first reset transistor on the substrate.

[0039] In some embodiments, the display panel further includes a first reset control signal line and a second initialization signal line, the pixel circuit further includes a second reset transistor, a first pole of the second reset transistor is connected to the second initialization signal line, a second pole of the second reset transistor is connected to a first pole of the light-emitting element and is configured to reset the first pole of the light-emitting element, the first reset control signal line is connected to a gate of the first reset transistor, the first initialization signal line and the second initialization signal line are located on the same layer and are located on different layers from the first reset control signal line, and the orthographic projection of the first reset control signal line on the substrate is located between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the second initialization signal line on the substrate.

[0040] In some embodiments, the first via and the second via are located on the same side of the first reset control signal line.

[0041] In some embodiments, the first reset control signal line is located in a first conductive layer, the first initialization signal line and the second initialization signal line are located in a second conductive layer, the first connection electrode is located in a third conductive layer, the first conductive layer is closer to the substrate than the second conductive layer, and the second conductive layer is closer to the substrate than the third conductive layer.

[0042] In some embodiments, the display panel further includes a second connection electrode, the second connection electrode is respectively connected to the second initialization signal line and the first pole of the second reset transistor, and the first connection electrode is inclined with respect to the second connection electrode.

[0043] In some embodiments, the included angle between the extending direction of the first connection electrode and the extending direction of the second connection electrode is an acute angle.

[0044] In some embodiments, the included angle between the extending direction of the first connection electrode and the extending direction of the second connection electrode is greater than or equal to 30 degrees and less than or equal to 60 degrees.

[0045] In some embodiments, the first via hole and the second connection electrode are respectively disposed on opposite sides of the first pole of the first reset transistor.

[0046] In some embodiments, the display panel further includes a third connection electrode, a first power supply line, and a shielding electrode. Wherein, the gate of the driving transistor is connected to the second pole of the first reset transistor through the third connection electrode. The first power supply line is configured to provide a constant first voltage signal to the pixel unit. The shielding electrode and the first power supply line are of an integral structure. The orthographic projection of the shielding electrode on the substrate covers the orthographic projection of the third connection electrode on the substrate.

[0047] In some embodiments, the third connection electrode and the second pole of the first reset transistor are connected through a third via hole. The orthographic projection of the shielding electrode on the substrate covers the orthographic projection of the third via hole on the substrate.

[0048] In some embodiments, the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the second pole of the first reset transistor on the substrate.

[0049] In some embodiments, the display panel further includes a fourth connection electrode. The pixel circuit further includes a first light-emitting control transistor and a storage capacitor. The first pole of the storage capacitor is connected to the gate of the driving transistor. The second pole of the storage capacitor is connected to the first power supply line through the fourth connection electrode. The fourth connection electrode is connected to the first pole of the first light-emitting control transistor through a fourth via hole. The fourth connection electrode is connected to the second pole of the storage capacitor through a fifth via hole.

[0050] In some embodiments, the display panel further includes a fifth connection electrode and a sixth connection electrode. Wherein, the first power supply line and the fourth connection electrode are connected through a sixth via hole. The pixel circuit further includes a second light-emitting control transistor. The first pole of the second light-emitting control transistor is connected to the driving transistor. The sixth connection electrode is connected to the fifth connection electrode through a seventh via hole. The fifth connection electrode is connected to the second pole of the second light-emitting control transistor through an eighth via hole. The seventh via hole and the sixth via hole are arranged along the first direction.

[0051] In some embodiments, the distance between the seventh via and the first initialization signal line is equal to the distance between the sixth via and the first initialization signal line.

[0052] In some embodiments, the display panel further includes a stopper and a seventh connection electrode, the pixel circuit further includes a threshold compensation transistor, the threshold compensation transistor includes a first channel, a second channel, and a conductive connection portion connecting the first channel and the second channel, the seventh connection electrode is connected to the first power supply line through a ninth via, the seventh connection electrode is connected to the stopper, and the orthographic projection of the stopper on the substrate at least partially overlaps with the orthographic projection of the conductive connection portion on the substrate, and the stopper is configured to block the conductive connection portion of the pixel unit at its position.

[0053] In some embodiments, the display panel further includes a data line and an eighth connection electrode, the pixel circuit further includes a data writing transistor, the data line is configured to provide a data signal to the pixel unit, the data line is connected to the data writing transistor through the eighth connection electrode, the eighth connection electrode is connected to the data line through a tenth via, and the ninth via and the tenth via are arranged along the first direction.

[0054] In some embodiments, the distance between the ninth via and the first initialization signal line is equal to the distance between the tenth via and the first initialization signal line.

[0055] In some embodiments, the data line includes a first data line and a second data line, the first data line extends along a second direction, the second data line includes a first portion extending along the first direction, and the first portion of the second data line is located between the first initialization signal line and the eighth connection electrode.

[0056] In some embodiments, the display panel includes a first display area and a second display area, the first display area is located on at least one side of the second display area, the pixel unit includes a first pixel unit and a second pixel unit, the pixel circuit and the light-emitting element of the first pixel unit are both located in the first display area, the pixel circuit of the second pixel unit is located in the first display area, the light-emitting element of the second pixel unit is located in the second display area, and the pixel circuit of the second pixel unit is connected to the light-emitting element of the second pixel unit through a conductive wire.

[0057] In some embodiments, the orthographic projection of the conductive wire on the substrate partially overlaps with the orthographic projection of the pixel circuit of the first pixel unit on the substrate.

[0058] In some embodiments, the positive projections of the tenth via, the ninth via, the seventh via, and the sixth via on the substrate do not overlap with the positive projection of the conductive line on the substrate.

[0059] At least one embodiment of the present disclosure further provides a display device, including any one of the above display panels.

[0060] For example, the display device further includes a sensor located on one side of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0062] Figure 1A is a schematic diagram of a display panel.

[0063] Figure 1B is a schematic diagram of a pixel unit in a display panel.

[0064] Figure 1C is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.

[0065] Figure 1D is a schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0066] Figure 1E is a schematic diagram of a display panel.

[0067] Figure 1F is a cross-sectional view of a display panel.

[0068] Figure 1G is a schematic diagram of forming a photoresist pattern.

[0069] Figure 1H is a schematic diagram of forming a conductive line.

[0070] Figure 2 is a schematic diagram of a pixel circuit in a display panel provided by some embodiments of the present disclosure.

[0071] Figure 3 is a layout diagram of a pixel circuit in a display panel provided by some embodiments of the present disclosure.

[0072] Figure 4A is Figure 3 a cross-sectional view along line A1-B1 of

[0073] Figure 4B is Figure 3Cross-sectional view along line A2 - B2 of

[0074] Figure 4C is Figure 3 Cross-sectional view along line A3 - B3 of

[0075] Figure 4D is Figure 3 Cross-sectional view along line A4 - B4 of

[0076] Figure 4E is Figure 3 Cross-sectional view along line A5 - B5 of

[0077] Figure 4F is Figure 3 Cross-sectional view along line A6 - B6 of

[0078] Figures 5 to 16 is Figure 3 Plan view of a single or multi-layer structure in the display panel shown

[0079] Figure 17 Schematic diagram of the first display area and the second display area in the display panel provided by an embodiment of the present disclosure

[0080] Figure 18 Schematic diagram of a conductive wire in a display panel provided by an embodiment of the present disclosure

[0081] Figure 19 Schematic diagram of a display panel

[0082] Figure 20 Schematic diagram of a conductive wire in a display panel provided by an embodiment of the present disclosure

[0083] Figure 21 is Figure 20 Partial enlarged view of

[0084] Figure 22 Schematic diagram of the first pixel unit in a display panel

[0085] Figure 23 is Figure 22 Cross-sectional view along line A8 - B8 of

[0086] Figure 24 and Figure 25 Schematic diagram of a display device provided by an embodiment of the present disclosure

[0087] Figure 26 is Figure 2 Timing diagram of the operation of the pixel circuit shown Detailed implementation manners

[0088] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0089] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0090] Figure 1A is a schematic diagram of a display panel. Figure 1A As shown, the display panel may include: a substrate BS. The display panel includes a display area R0 and a peripheral area R3. The peripheral area R3 may be located at least on one side of the display area R0. Figure 1A Take the peripheral area R3 surrounding the display area R0 as an example. For example, the display panel includes a plurality of pixel units 100, and the plurality of pixel units 100 are located in the display area R0. The plurality of pixel units 100 can be arranged in the display area R0 according to a certain rule. Figure 1A Only four pixel units 100 are shown for exemplary purposes. The number of pixel units 100 is not limited to that shown in the figure.

[0091] Figure 1B is a schematic diagram of a pixel unit in a display panel. Figure 1B As shown, the pixel unit 100 includes a pixel circuit 100a and a light emitting element 100b, and the pixel circuit 100a is configured to drive the light emitting element 100b. For example, the pixel circuit 100a is configured to provide a driving current to drive the light emitting element 100b to emit light. For example, the light emitting element 100b is an organic light emitting diode (OLED), and the light emitting element 100b emits red light, green light, blue light, or white light under the drive of its corresponding pixel circuit 100b. The color of the light emitted by the light emitting element 100b can be determined as required.

[0092] Figure 1C This is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. As Figure 1C shown, the display panel may include: a substrate substrate BS. The display panel includes a first display area R1 and a second display area R2, and the first display area R1 may be located on at least one side of the second display area R2. For example, in some embodiments, the first display area R1 surrounds the second display area R2. That is, the second display area R2 may be surrounded by the first display area R1. The second display area R2 may also be provided at other positions, and the setting position of the second display area R2 may be determined according to needs. For example, the second display area R2 may be located at the exact middle position on the top of the substrate substrate BS, or may be located at the upper left corner position or the upper right corner position of the substrate substrate BS. For example, hardware such as a photosensor (such as a camera) is provided in the second display area R2 of the display panel. For example, the second display area R2 is a light-transmissive display area, and the first display area R1 is a display area. For example, the first display area R1 is light-impermeable and only used for display.

[0093] In order to improve the light transmittance of the second display area R2, only light-emitting elements may be provided in the second display area R2, and the pixel circuits for driving the light-emitting elements in the second display area R2 are provided in the first display area R1. That is, the light transmittance of the second display area R2 is improved by separating the light-emitting elements and the pixel circuits.

[0094] Figure 1D This is a schematic diagram of a display panel provided by an embodiment of the present disclosure. As Figure 1D shown, the display panel includes: a plurality of first pixel circuits 10, a plurality of second pixel circuits 20, and a plurality of first light-emitting elements 30 located in the first display area R1, and a plurality of second light-emitting elements 40 located in the second display area R2. For example, the plurality of second pixel circuits 20 may be distributed at intervals between the plurality of first pixel circuits 10.

[0095] For example, as Figure 1D shown, at least one first pixel circuit 10 among the plurality of first pixel circuits 10 may be connected to at least one first light-emitting element 30 among the plurality of first light-emitting elements 30, and the orthographic projection of the at least one first pixel circuit 10 on the substrate substrate BS and the orthographic projection of the at least one first light-emitting element 30 on the substrate substrate BS may at least partially overlap. The at least one first pixel circuit 10 may be used to provide a driving signal for the connected first light-emitting element 30 to drive the first light-emitting element 30 to emit light.

[0096] For example, as Figure 1DAs shown, at least one of the multiple second pixel circuits 20 can be connected to at least one of the multiple second light-emitting elements 40 through a conductive line L1. The at least one second pixel circuit 20 can be used to provide a driving signal for the connected second light-emitting element 40 to drive the second light-emitting element 40 to emit light. As Figure 1D As shown, since the second light-emitting element 40 and the second pixel circuit 20 are located in different regions, the orthographic projection of at least one second pixel circuit 20 on the substrate substrate BS does not overlap with the orthographic projection of at least one second light-emitting element 40 on the substrate substrate BS.

[0097] For example, in the embodiments of the present disclosure, the first display area R1 can be set as a non-transmissive display area, and the second display area R2 can be set as a transmissive display area. For example, the first display area R1 is non-transmissive, and the second display area R2 is transmissive. In this way, for the display panel provided by the embodiments of the present disclosure, there is no need to perform a hole-drilling process on the display panel, and hardware structures such as photosensitive sensors can be directly disposed at the position corresponding to the second display area R2 on one side of the display panel, laying a solid foundation for the realization of a true full-screen display. Moreover, since the second display area R2 only includes light-emitting elements and does not include pixel circuits, it is beneficial to improve the light transmittance of the second display area R2, so that the display panel has a better display effect.

[0098] As Figure 1D As shown, the pixel unit 100 includes a first pixel unit 101 and a second pixel unit 102. The pixel circuit 100a and the light-emitting element 100b of the first pixel unit 101 are both located in the first display area R1. The pixel circuit 100a of the second pixel unit 102 is located in the first display area R1, and the light-emitting element 100b of the second pixel unit 102 is located in the second display area R2. In the embodiments of the present disclosure, the pixel circuit 100a of the first pixel unit 101 is the first pixel circuit 10, the light-emitting element 100b of the first pixel unit 101 is the first light-emitting element 30, the pixel circuit 100a of the second pixel unit 102 is the second pixel circuit 20, and the light-emitting element 100b of the second pixel unit 102 is the second light-emitting element 40. For example, the first pixel circuit 10 can be called an in-situ pixel circuit, and the second pixel circuit 20 can be called a non-in-situ pixel circuit.

[0099] For example, as Figure 1D As shown, the second light-emitting element 40 and the second pixel circuit 20 connected to the second light-emitting element 40 are located in the same row. That is, the light-emitting signal of the second light-emitting element 40 comes from the second pixel circuit in the same row. For example, the pixel circuits of the pixel units in the same row are connected to the same gate line.

[0100] As Figure 1DAs shown, the pixel circuit (second pixel circuit 20) of the second pixel unit 102 is connected to the light-emitting element (second light-emitting element 40) of the second pixel unit 102 through the conductive line L1. For example, the conductive line L1 is made of a transparent conductive material. For example, the conductive line L1 is made of a conductive oxide material. For example, the conductive oxide material includes indium tin oxide (ITO), but is not limited thereto.

[0101] As Figure 1D shown, one end of the conductive line L1 is connected to the second pixel circuit 20, and the other end of the conductive line L1 is connected to the second light-emitting element 40. As Figure 1D shown, the conductive line L1 extends from the first display area R1 to the second display area R2.

[0102] Figure 1E is a schematic diagram of a display panel. As Figure 1E shown, the display panel includes a plurality of data lines DT located on the substrate BS. In a display device with an under-screen camera, the arrangement of the plurality of data lines includes two methods: winding within the second display area R2 and winding outside the second display area. Due to the limitation of the space size of the second display area, Figure 1E The shown display panel is designed according to the full-compression pixel circuit scheme, and the data lines are arranged by winding the data lines outside the second display area R2. In this display panel, the first display area R1 includes a plurality of first pixel circuit columns and a plurality of second pixel circuit columns. In addition to the second pixel circuit, the second pixel circuit column where the second pixel circuit is located also includes dummy pixel circuits that are not connected to any light-emitting elements; the first display area R1 also includes a plurality of dummy pixel circuit columns, and at least one first pixel circuit column is arranged between two adjacent dummy pixel circuit columns. The above-mentioned full-compression pixel circuit means that without reducing the pixel density of the overall display area (including the first display area and the second display area), a plurality of pixel circuit columns in the overall display area are compressed in the first direction X (for example, reducing the size of each pixel circuit along the first direction X) to increase the number of pixel circuit columns arranged along the first direction X. The newly added pixel circuit columns include the second pixel circuit columns for connecting to the second light-emitting elements in the second display area and the dummy pixel circuit columns that are not connected to any light-emitting elements.

[0103] As Figure 1E shown, the plurality of data lines DT include a data line DT1 and a data line DT2. The data line DT1 is only connected to the first pixel circuit. The data line DT2 is at least connected to the second pixel circuit. The data line DT1 is a data line extending along the second direction Y. The data line DT2 includes a first part DT2a, a second part DT2b, a third part DT2c, a fourth part DT2d, and a fifth part DT2e. For example, as Figure 1EAs shown, the second part DT2b, the first part DT2a, the third part DT2c, the fourth part DT2d, and the fifth part DT2e are connected in sequence to form the second data line DT2. A gap 20 is provided between the third part DT2c and the dummy line 30 to achieve insulation between the two. The dummy line 30 is connected to the dummy pixel circuit. To avoid the floating of the dummy line 30, the dummy line 30 can be connected to a signal line with a fixed voltage, for example, the power supply voltage signal (VDD). For example, each data line DT can adopt single-path driving. It should be noted that the setting method of multiple data lines DT is not limited to Figure 1E as shown. Figure 1E Taking the fourth part DT2d located in the peripheral area R3 as an example for illustration. In other embodiments, the fourth part DT2d is located in the first display area R1.

[0104] Of course, in a display panel that does not adopt the full compression method, the second data line DT2 may not be provided either. The embodiments of the present disclosure are described by taking a display panel that adopts the full compression method as an example.

[0105] During the process of forming the conductive line L1, the conductive line may be broken or thinned, resulting in dark spot defects in the display. The following combines Figures 1F to 1H to illustrate the possible causes of dark spot defects.

[0106] Figure 1F is a cross-sectional view of a display panel. Figure 1F is a schematic diagram of an exposure process during the patterning of the transparent conductive film in the process of forming the conductive line L1. Figure 1G is a schematic diagram of forming a photoresist pattern. Figure 1H is a schematic diagram of forming a conductive line. As Figure 1F shown, the first conductive element 111 is located on the substrate BS; the first planarization layer 121 is located on the first conductive element 111; the second conductive element 112 is located on the first planarization layer 121 and is connected to the first conductive element 111 through a via V0 penetrating the first planarization layer 121; the second planarization layer 122 is located on the second conductive element 112. As Figure 1F shown, forming the conductive line L1 includes forming a transparent conductive film F1 on the second planarization layer 122, forming a photoresist film 201 on the transparent conductive film F1, and exposing the photoresist film 201 with the mask 202 as a mask, so that the photoresist film 201 forms a photoresist remaining portion 2011 and a photoresist to-be-removed portion 2012. As Figure 1G shown, after the exposure process, a development process is performed. In the development process, the photoresist to-be-removed portion 2012 is removed to form a photoresist pattern 201a. As Figure 1HAs shown, using the photoresist pattern 201a as a mask, the transparent conductive thin film F1 is etched to form a conductive line L1. For example, there are multiple conductive lines L1, and the multiple conductive lines L1 include multiple first conductive lines located in the first transparent conductive layer and multiple second conductive lines located in the second transparent conductive layer. An insulating layer may be provided between the first transparent conductive layer and the second transparent conductive layer. In other embodiments, three or more transparent conductive layers may be included to provide more conductive lines. An insulating layer is provided between adjacent transparent conductive layers.

[0107] After the exposure process, the photoresist on the transparent conductive thin film shows exposure breakage and thinning, resulting in broken or thinned conductive lines after development and etching, thereby causing dark spot defects in the display. An optical microscope confirmed that the positions of the broken and thinned conductive lines are at the vias V0 where the conductive lines cross the first planarization layer 121. Further, by performing focused ion beam (FIB) analysis on the cross-section of the via V0 in the first planarization layer 121, it was found that below the position where the conductive line crossing the via V0 is broken or thinned, there is a bowl-shaped portion of the second conductive element 112. Therefore, as Figure 1F shown, it is determined that the reasons for the broken and thinned conductive line defects are as follows: During the exposure process, the second conductive element 112 reflects light and converges it to the photoresist retention portion 2011 of the photoresist located above the bowl-shaped portion (corresponding to the position of the via V0) of the second conductive element 112, causing this part of the photoresist to be exposed or partially exposed and washed away after development. As a result, the conductive lines formed by etching the transparent conductive thin film using the photoresist pattern 201a as a mask show breakage and thinning. As Figures 1F to 1H shown, the photoresist retention portion 2011 of the photoresist at the middle position is irradiated by partial reflected light, causing the conductive line below it to become thinner.

[0108] Figure 2 is a schematic diagram of a pixel circuit in a display panel provided by some embodiments of the present disclosure. Figure 3 is a layout diagram of a pixel circuit in a display panel provided by some embodiments of the present disclosure. Figure 4A is Figure 3 a cross-sectional view along line A1 - B1 of Figure 4B is Figure 3 a cross-sectional view along line A2 - B2 of Figure 4C is Figure 3 a cross-sectional view along line A3 - B3 of ​ is ​ a cross-sectional view along line A4 - B4 of ​ is ​ a cross-sectional view along line A5 - B5 of ​ is ​ a cross-sectional view along line A6 - B6 of ​ is​ A plan view of a single-layer or multi-layer structure in the shown display panel. The following will describe a display panel provided by some embodiments of the present disclosure in conjunction with ​ a display panel provided by some embodiments of the present disclosure will be described.

[0109] ​ The shown pixel circuit may be a pixel circuit of a common Low Temperature Poly-silicon (LTPS) AMOLED in the related art. ​ The pixel circuit of a pixel unit of the display panel is shown. As ​ shown, the pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes six switching transistors (T2-T7), a driving transistor T1, and a storage capacitor Cst. For example, the six switching transistors are a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, and a second reset transistor T7. The light-emitting element 100b includes a first electrode Ea and a second electrode Eb, and a light-emitting functional layer located between the first electrode Ea and the second electrode Eb. It should be noted that ​ taking the 7T1C pixel circuit as an example for description, the embodiments of the present disclosure include but are not limited to this. In some embodiments, the pixel circuit 100a may not include at least one of the six switching transistors (T2-T7).

[0110] In some embodiments of the present disclosure, as ​ shown, the first electrode Ea is an anode, and the second electrode Eb is a cathode. Generally, the threshold compensation transistor T3 and the first reset transistor T6 adopt a dual-gate thin film transistor (TFT) method to reduce leakage.

[0111] In some embodiments of the present disclosure, referring to ​ , ​ , ​ , ​ , ​ , ​ and ​ shown, the display panel provided by some embodiments of the present disclosure includes: a substrate BS, a pixel unit 100, a first initialization signal line INT1, and a connection electrode E1.

[0112] In some embodiments of the present disclosure, referring to ​ , ​ , ​ , and ​, the pixel unit 100 is located on the substrate BS and includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a is configured to drive the light-emitting element 100b. The pixel circuit 100a includes a driving transistor T1 and a first reset transistor T6. The first reset transistor T6 is connected to the driving transistor T1 and is configured to reset the gate of the driving transistor T1.

[0113] In some embodiments of the present disclosure, referring to ​ and ​ , a first initialization signal line INT1 is connected to a first pole T61 of the first reset transistor T6 and is configured to provide a first initialization signal Vinit1 to the pixel unit 100.

[0114] In some embodiments of the present disclosure, referring to ​ , the first initialization signal line INT1 is connected to the first pole T61 of the first reset transistor T6 through a connection electrode E1. Referring to ​ and ​ , the connection electrode E1 is connected to the first initialization signal line INT1 through a via V1 and is connected to the first pole of the first reset transistor T6 through a via V2. The first initialization signal line INT1 extends along a first direction X, and the connection electrode E1 is inclined with respect to the first initialization signal line INT1.

[0115] The display panel provided by some embodiments of the present disclosure adopts a manner in which the connection electrode E1 is inclined with respect to the first initialization signal line INT1, so as to facilitate reducing the size of the pixel circuit in the first direction X. For example, reducing the lateral size of the pixel circuit. When the data lines in the display panel are arranged in a winding manner, the connection electrode E1 is inclined with respect to the first initialization signal line INT1, providing space for arranging a first part DT2a of a second data line DT2.

[0116] In some embodiments of the present disclosure, the connection electrode E1 being inclined with respect to the first initialization signal line INT1 includes that the connection electrode E1 is neither parallel nor perpendicular to the first initialization signal line INT1.

[0117] In some embodiments of the present disclosure, as ​ , ​ and ​ shown, the included angle θ1 between the extending direction of the connection electrode E1 and the extending direction of the first initialization signal line INT1 is an acute angle.

[0118] In some embodiments of the present disclosure, as ​ , ​ and ​ shown, for the convenience of layout design, the included angle θ1 is greater than or equal to 30 degrees and less than or equal to 60 degrees.

[0119] In some embodiments of the present disclosure, as ​ and ​ shown, the first reset transistor T6 includes a channel CN1 and a channel CN2. For example, as ​ and ​ shown, the center connection lines of the via V1, the channel CN1, and the channel CN2 form an acute triangle, and the center connection lines of the via V2, the channel CN1, and the channel CN2 form an obtuse triangle. For example, the acute triangle is an isosceles triangle, but is not limited thereto. ​ and ​ show the center C1 of the via V1, the center C4 of the via V2, the center C2 of the channel CN1 of the first reset transistor T6, and the center C3 of the channel CN2 of the first reset transistor T6. For example, in the embodiments of the present disclosure, the center of an element refers to the center of the geometric shape of the element.

[0120] In some embodiments of the present disclosure, as ​ , ​ and ​ shown, in order to facilitate reducing the size of the pixel circuit in the first direction, the first initialization signal line INT1 includes a first overlapping portion VP1 overlapping with the first pole T61 of the first reset transistor T6 and a second overlapping portion VP2 overlapping with the second pole of the first reset transistor T6. As ​ and ​ shown, in the plan view, the via V1 is located between the first overlapping portion VP1 and the second overlapping portion VP2. As ​ and ​ shown, the orthographic projection of the via V1 on the substrate is located between the orthographic projection of the first overlapping portion VP1 on the substrate and the orthographic projection of the second overlapping portion VP2 on the substrate.

[0121] In some embodiments of the present disclosure, as ​ and ​ shown, in order to avoid affecting the first pole T61 and the second pole T62 of the first reset transistor T6 during the formation of the via V1, the orthographic projection of the via V1 on the substrate BS does not overlap with the orthographic projection of the first pole T61 of the first reset transistor T6 on the substrate BS, and does not overlap with the orthographic projection of the second pole T62 of the first reset transistor T6 on the substrate BS.

[0122] In some embodiments of the present disclosure, as ​ , ​ , ​ and ​As shown, the display panel further includes a first reset control signal line RST1 and a second initialization signal line INT2. The first reset control signal line RST1 is configured to provide a first reset control signal RESET1 to the pixel unit 100. The second initialization signal line INT2 is configured to provide a second initialization signal Vinit2 to the pixel unit 100. The pixel circuit 100a further includes a second reset transistor T7. A first pole T71 of the second reset transistor T7 is connected to the second initialization signal line INT2. A second pole T72 of the second reset transistor T7 is connected to a first pole Ea of the light-emitting element 100b and is configured to reset the first pole Ea of the light-emitting element 100b. The first reset control signal line RST1 is connected to a gate T60 of the first reset transistor T6. The first initialization signal line INT1 and the second initialization signal line INT2 are on the same layer and are on different layers from the first reset control signal line RST1. A positive projection of the first reset control signal line RST1 on the substrate BS is located between a positive projection of the first initialization signal line INT1 on the substrate BS and a positive projection of the second initialization signal line INT2 on the substrate BS. That is, the first initialization signal line INT1 and the second initialization signal line INT2 are respectively disposed on opposite sides of the first reset control signal line RST1.

[0123] In some embodiments of the present disclosure, as ​ , ​ , ​ and ​ shown, the first reset control signal line RST1 is located in the first conductive layer LY1. As ​ , ​ and ​ shown, both the first initialization signal line INT1 and the second initialization signal line INT2 are located in the second conductive layer LY2.

[0124] In some embodiments of the present disclosure, the first initialization signal line INT1 and the second initialization signal line INT2 are located on the same layer and are located on different layers from the first reset control signal line RST1. The positive projection of the first reset control signal line RST1 on the substrate substrate BS is located between the positive projection of the first initialization signal line INT1 on the substrate substrate BS and the positive projection of the second initialization signal line INT2 on the substrate substrate BS, so that the first reset control signal line RST1 can be arranged in the gap between the first initialization signal line INT1 and the second initialization signal line INT2, thereby reducing the longitudinal space occupied by the first initialization signal line INT1, the second initialization signal line INT2, and the first reset control signal line RST1, which is beneficial to saving longitudinal space. When the display panel has data lines that are routed around the second display area, a setting space is provided for the portion of the data line that extends in the first direction X (the first portion DT2a of the second data line DT2). In the case where the first initialization signal line INT1 and the second initialization signal line INT2 are on the same side of the first reset control signal line RST1, since the distance between the first initialization signal line INT1 and the second initialization signal line INT2 on the same layer is relatively large, the longitudinal space occupied by the first initialization signal line INT1, the second initialization signal line INT2, and the first reset control signal line RST1 is relatively large.

[0125] In some embodiments of the present disclosure, as ​ , ​ and ​ shown, the via V1 and the via V2 are on the same side of the first reset control signal line RST1.

[0126] In some embodiments of the present disclosure, as ​ , ​ , ​ and ​ shown, the distance D1 from the via V1 to the first reset control signal line RST1 is less than the distance D2 from the via V2 to the first reset control signal line RST1. ​ Illustrates the distance D1 from the via V1 to the first reset control signal line RST1 and the distance D2 from the via V2 to the first reset control signal line RST1. For example, the distance D1 from the via V1 to the first reset control signal line RST1 may refer to the minimum distance from the center of the via V1 to the edge of the first reset control signal line RST1. For example, the distance D2 from the via V2 to the first reset control signal line RST1 may refer to the minimum distance from the center of the via V2 to the edge of the first reset control signal line RST1.

[0127] In some embodiments of the present disclosure, as ​ and ​As shown, the first reset control signal line RST1 is located in the first conductive layer LY1. For example, as ​ and ​ shown, the gate T10 of the driving transistor is located in the first conductive layer LY1. For example, as ​ shown, the first initialization signal line INT1 and the second initialization signal line INT2 are located in the second conductive layer LY2. For example, as ​ shown, the connection electrode E1 is located in the third conductive layer LY3. As ​ shown, the first conductive layer LY1 is closer to the substrate BS than the second conductive layer LY2, and the second conductive layer LY2 is closer to the substrate BS than the third conductive layer LY3. ​ It is shown that the second pole Cb of the storage capacitor Cst has an opening OPN1. By setting OPN1, the connection electrode E3 can be connected to the first pole Ca of the storage capacitor Cst.

[0128] In some embodiments of the present disclosure, as ​ shown, the display panel includes a first insulating layer ISL1, a second insulating layer ISL2, a third insulating layer ISL3, and a fourth insulating layer ISL4. ​ Taking the fourth insulating layer ISL4 including an insulator layer ISL41 and an insulator layer ISL42 as an example for illustration. In some embodiments of the present disclosure, the insulator layer ISL41 is a passivation layer, and the insulator layer ISL42 is a first planarization layer.

[0129] In some embodiments of the present disclosure, as ​ , ​ and ​ shown, the display panel further includes a connection electrode E2. The second initialization signal line INT2 and the first pole T71 of the second reset transistor T7 are connected through the connection electrode E2, that is, the connection electrode E2 is respectively connected to the second initialization signal line INT2 and the first pole T71 of the second reset transistor T7.

[0130] In some embodiments of the present disclosure, as ​ , ​ and ​ shown, the connection electrode E1 is disposed obliquely with respect to the connection electrode E2.

[0131] In some embodiments of the present disclosure, the included angle θ2 between the extending direction of the connection electrode E1 and the extending direction of the connection electrode E2 is an acute angle. For example, the included angle θ2 between the extending direction of the connection electrode E1 and the extending direction of the connection electrode E2 is greater than or equal to 30 degrees and less than or equal to 60 degrees.

[0132] In some embodiments of the present disclosure, the sum of the included angle θ1 and the included angle θ2 is 90°.

[0133] In some embodiments of the present disclosure, the first initialization signal line INT1 extends along the first direction X, the connection electrode E2 extends along the second direction Y, the connection electrode E1 is inclined with respect to the first direction X and inclined with respect to the second direction Y, and the first direction X is perpendicular to the second direction Y.

[0134] In some embodiments of the present disclosure, as ​ , ​ and ​ shown, the via V1 and the connection electrode E2 are respectively disposed on opposite sides of the first pole T61 of the first reset transistor T6.

[0135] In some embodiments of the present disclosure, as ​ , ​ , ​ , ​ and ​ shown, the display panel further includes a connection electrode E3, a first power line PL1, and a shielding electrode SE. The gate T10 of the driving transistor T1 is connected to the second pole T62 of the first reset transistor T6 through the connection electrode E3. The first power line PL1 is configured to provide a constant first voltage signal to the pixel unit 100. The shielding electrode SE and the first power line PL1 are of an integral structure. The orthographic projection of the shielding electrode SE on the substrate BS covers the orthographic projection of the connection electrode E3 on the substrate BS. For example, the shielding electrode SE and the first power line PL1 are both located in the same layer, that is, the fourth conductive layer LY4. The shielding electrode SE and the first power line PL1 are of an integral structure, avoiding connection through vias and avoiding the influence of the vias penetrating the fourth insulating layer on the conductive line.

[0136] For example, the gate T10 of the driving transistor T1, the connection electrode E3, and the second pole T62 of the first reset transistor T6 constitute a gate signal portion PT1. The potentials on the gate signal portion PT1 are the same.

[0137] To stabilize the potential on the gate signal portion PT1, the display panel provided by the embodiments of the present disclosure provides a shielding electrode SE. The shielding electrode SE is connected to the first power line PL1, so that the voltage on the shielding electrode SE is stable, playing a shielding role and avoiding the influence of other signal lines on the potential on the gate signal portion PT1. For example, by providing the shielding electrode SE, the influence of the conductive line L1 on the first node N1 is avoided, and the influence on the potential on the gate signal portion PT1 is avoided. The orthographic projection of the connection electrode E3 on the substrate BS falls within the orthographic projection of the shielding electrode SE on the substrate BS.

[0138] In some embodiments of the present disclosure, as ​ , ​ and ​As shown, the second pole of the connection electrode E3 and the first reset transistor T6 are connected through a via V3. As ​ shown, in order to stabilize the potential on the gate signal part PT1, the positive projection of the shielding electrode SE on the substrate BS covers the positive projection of the via V3 on the substrate BS.

[0139] In some embodiments of the present disclosure, as ​ shown, in order to stabilize the potential on the gate signal part PT1, the positive projection of the shielding electrode SE on the substrate BS and the positive projection of the second pole of the first reset transistor T6 on the substrate BS at least partially overlap.

[0140] In some embodiments of the present disclosure, as ​ and ​ shown, the display panel further includes a connection electrode E4, the pixel circuit 100a further includes a first light-emitting control transistor T4 and a storage capacitor Cst. The first pole Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1, the second pole Cb of the storage capacitor Cst is connected to the first power line PL1 through the connection electrode E4, the connection electrode E4 is connected to the first pole T41 of the first light-emitting control transistor T4 through a via V4, the connection electrode E4 is connected to the second pole Cb of the storage capacitor Cst through a via V5, and the first power line PL1 and the connection electrode E4 are connected through a via V6.

[0141] In some embodiments of the present disclosure, the first power line PL1 is respectively connected to the second pole Cb of the storage capacitor Cst and the first pole T41 of the first light-emitting control transistor T4 through the connection electrode E4, reducing the number of vias penetrating the fourth insulating layer ISL4 and avoiding problems such as thinning or disconnection of the conductive line L1.

[0142] In some embodiments of the present disclosure, as ​ and ​ shown, the display panel further includes a connection electrode E5 and a connection electrode E6, the pixel circuit 100a further includes a second light-emitting control transistor T5. The first pole T51 of the second light-emitting control transistor T5 is connected to the driving transistor T1, the connection electrode E6 is connected to the connection electrode E5 through a via V7, the connection electrode E5 is connected to the second pole T52 of the second light-emitting control transistor T5 through a via V8, and the vias V7 and V6 are arranged along the first direction X.

[0143] In some embodiments of the present disclosure, as ​ and ​As shown, the distance from via V7 to the first initialization signal line INT1 is equal to the distance from via V6 to the first initialization signal line INT1. For example, the distance from via V7 to the first initialization signal line INT1 may refer to the minimum distance from the center of via V7 to the edge of the first initialization signal line INT1, and the distance from via V6 to the first initialization signal line INT1 may refer to the minimum distance from the center of via V6 to the edge of the first initialization signal line INT1.

[0144] In some embodiments of the present disclosure, as ​ , ​ , ​ , ​ , ​ , ​ , ​ and ​ shown, the display panel further includes a stopper BK and a connection electrode E7, the pixel circuit 100a further includes a threshold compensation transistor T3, the threshold compensation transistor T3 includes a channel CN1, a channel CN2, and a conductive connection portion CP1 connecting the channel CN1 and the channel CN2. The connection electrode E7 is connected to the first power line PL1 through a via V9, the connection electrode E7 is connected to the stopper BK, and at least a part of the orthographic projection of the stopper BK on the substrate BS overlaps with the orthographic projection of the conductive connection portion CP1 on the substrate BS. The stopper BK is configured to block the conductive connection portion CP1 of the pixel unit 100 at its position. Compared with the stopper BK for blocking the conductive connection portions CP1 of the pixel units on the left and right sides of the pixel unit 100 at its position, the stopper BK is configured to block the conductive connection portion CP1 of the pixel unit 100 at its position, so that the structure of the pixel unit is more compact and more conducive to the stability of the voltage on the conductive connection portion CP1. As ​ and ​ shown, the connection electrode E7 and the stopper BK are connected through a via Vc. As ​ shown, the via Vc penetrates through the third insulating layer ISL3. As ​ shown, the via V9 penetrates through the fourth insulating layer ISL4.

[0145] In some embodiments of the present disclosure, as ​ , ​ shown, the first reset transistor T3 includes a channel CN10, a channel CN20, and a conductive connection portion CPa connecting the channel CN10 and the channel CN20. As ​ , ​ shown, in order to stabilize the voltage on the conductive connection portion CPa, the second initialization signal line INT2 overlaps with the conductive connection portion CPa. As ​ , ​As shown, in order to stabilize the voltage on the conductive connection portion CPa, the positive projection of the second initialization signal line INT2 on the substrate at least partially overlaps with the positive projection of the conductive connection portion CPa on the substrate.

[0146] In some embodiments of the present disclosure, as ​ , ​ , ​ , ​ , ​ , ​ As shown, the display panel further includes a data line DT and a connection electrode E8, and the pixel circuit 100a further includes a data writing transistor T2. The data line DT is configured to provide a data signal to the pixel unit 100. The data line DT is connected to the data writing transistor T2 through the connection electrode E8, and the connection electrode E8 is connected to the data line DT through a via V10. As ​ and ​ As shown, the vias V9 and V10 are arranged along the first direction X. Both the vias V9 and V10 are vias penetrating the fourth insulating layer ISL4, so that the arrangement of the vias V9 and V10 along the first direction X is beneficial to the setting of the conductive line L1.

[0147] As ​ and ​ As shown, as ​ and ​ As shown, the connection electrode E8 is connected to the first pole T21 of the data writing transistor T2. As ​ and ​ As shown, the connection electrode E8 is connected to the first pole T21 of the data writing transistor T2 through a via Vb. As ​ As shown, the via Vb penetrates the first insulating layer ISL1, the second insulating layer ISL2, and the third insulating layer ISL3.

[0148] In some embodiments of the present disclosure, in order to avoid the conductive line L1 from becoming thinner or broken, at the lateral position where the vias V9 and V10 are provided, the conductive line may not be provided, that is, the conductive line L1 is avoided from being disposed above the vias V9 and V10. In order to have more space for arranging the conductive line, the distance from the via V9 to the first initialization signal line INT1 is equal to the distance from the via V10 to the first initialization signal line INT1.

[0149] In some embodiments of the present disclosure, as ​ , ​ , ​ , ​ and ​As shown, the data line DT includes a first data line DT1 and a second data line DT2. The first data line DT1 extends along the second direction Y, and the second data line DT2 includes a first portion DT2a extending along the first direction X. The first portion DT2a of the second data line DT2 is located between the first initialization signal line INT1 and the connection electrode E8. As ​ and ​ shown, the first portion DT2a of the second data line DT2 is also located between the first initialization signal line INT1 and the connection electrode E7. Thus, the setting position of the first portion DT2a of the second data line DT2 is defined.

[0150] Refer to ​ , the second portion DT2b and the third portion DT2c of the second data line DT2 are connected by the first portion DT2a of the second data line DT2, and both the second portion DT2b and the third portion DT2c extend along the second direction Y.

[0151] In some embodiments of the present disclosure, in order to facilitate the formation of a high-frequency display panel, the data line DT and the first power line PL1 are located on the same layer, so as to facilitate the setting of the first portion DT2a of the second data line DT2 in the third conductive layer LY3, provide a setting position for the first portion DT2a of the second data line DT2, and provide a setting space for the data line that is arranged in the first display area and winds around the second display area.

[0152] In some embodiments of the present disclosure, as ​ shown, the display panel includes a first display area R1 and a second display area R2. The first display area R1 is located on at least one side of the second display area R2. The pixel unit 100 includes a first pixel unit 101 and a second pixel unit 102. The pixel circuit 100a and the light-emitting element 100b of the first pixel unit 101 are both located in the first display area R1. The pixel circuit 100a of the second pixel unit 102 is located in the first display area R1, and the light-emitting element 100b of the second pixel unit 102 is located in the second display area R2. The pixel circuit 100a of the second pixel unit 102 is connected to the light-emitting element 100b of the second pixel unit 102 through the conductive line L1.

[0153] For example, in some embodiments, the first reset control signal line can be connected to the gate line in this pixel unit. Thus, the first reset control signal line and the gate line in this pixel unit can be input with the same signal. For example, in some embodiments, the second reset control signal line can be connected to the gate line in the next pixel unit. Thus, the second reset control signal line and the gate line in the next pixel unit can be input with the same signal.

[0154] ​Schematic diagram of a first display area and a second display area in a display panel provided by an embodiment of the present disclosure. As ​ shown, in the second display area R2, a light-transmitting area R0 is provided between adjacent second light-emitting elements 40. For example, as ​ shown, a plurality of light-transmitting areas R0 are connected to each other to form a continuous light-transmitting area separated by a plurality of second light-emitting elements 40. The conductive wire L1 is made of a transparent conductive material to improve the light transmittance of the light-transmitting area R0 as much as possible. As ​ shown, the area of the second display area R2 except for the second light-emitting elements 40 provided may all be light-transmitting areas.

[0155] For example, in order to improve the display effect, the density of the second light-emitting elements 40 may be equal to the density of the first light-emitting elements 30. That is, the resolution of the second display area R2 is the same as the resolution of the first display area R1. Of course, in other embodiments, the density of the second light-emitting elements 40 may be greater than or less than the density of the first light-emitting elements 30. That is, the resolution of the second display area R2 may be greater than or less than the resolution of the first display area R1. For example, as ​ shown, the light-emitting area of the second light-emitting element 40 is smaller than the light-emitting area of the first light-emitting element 30. ​ The light-emitting areas of the second light-emitting element 40 and the first light-emitting element 30 are shown by dashed lines. For example, the light-emitting area of the light-emitting element may correspond to the area of the opening of the pixel definition layer.

[0156] ​ Schematic diagram of a conductive wire in a display panel provided by an embodiment of the present disclosure. ​ Schematic diagram of a display panel. ​ Schematic diagram of a conductive wire in a display panel provided by an embodiment of the present disclosure. ​ is ​ a partial enlarged view of. ​ 、 ​ and ​ show a plurality of conductive wires L1.

[0157] ​ and ​ show the first light-emitting element 30, the second light-emitting element 40, the first pixel circuit 10, the second pixel circuit 20, the connection element CE0, and the conductive wire L1. Each pixel circuit is connected to the light-emitting element through the connection element CE0. That is, each pixel unit has a connection element CE0. That is, the first pixel circuit 10 is connected to the first light-emitting element 30 through the connection element CE0, and the second pixel circuit 20 is connected to the second light-emitting element 40 through the connection element CE0. For example, one end of the conductive wire L1 is connected to the second pixel circuit 20 through the connection element CE0, and the other end of the conductive wire L1 is connected to the second light-emitting element 40.

[0158] As shown ​ in the figure, a conductive wire L1 passes through the area where the pixel circuit of the pixel unit is located to connect the second pixel circuit 20 and the second light-emitting element 40 on both sides of the pixel unit respectively. For example, the area where the pixel circuit of the pixel unit is located overlaps with multiple conductive wires L1 passing through this area, so that the pixel circuit and the conductive wire overlapping with the pixel circuit are coupled to form a parasitic capacitance, resulting in a difference in brightness and forming display defects such as stripes (Mura). Due to the coupling between the conductive wire and the pixel circuit, it is easy to cause a phenomenon that the brightness of some areas of the display panel is dim, and the dim pixel units are the pixel units (first pixel units) in the first display area R1, rather than the second light-emitting elements 40 in the second display area R2. For example, the situation of dim brightness is more obvious in high gray levels than in low gray levels. ​ Taking the example that a first pixel circuit 10 overlaps with at most two conductive wires L1, in other embodiments, a first pixel circuit 10 can also overlap with more conductive wires L1. For example, as ​ shown in the figure, in some embodiments, a first pixel circuit 10 can overlap with 10-15 conductive wires L1. The number of conductive wires L1 that a first pixel circuit 10 overlaps with can be determined according to needs.

[0159] Embodiments of the present disclosure are to solve the situation that the brightness of some areas of the display panel is dim, and a shielding electrode SE is provided. The shielding electrode SE is located between the conductive wire L1 and the gate signal part PT1. For example, in some embodiments, the shielding electrode SE is located between the conductive wire L1 and the gate T10 of the driving transistor. The shielding electrode SE is provided to play a better shielding role, which is beneficial to improving the brightness uniformity of the display panel and enhancing the display effect.

[0160] In some embodiments, the size of the first pixel circuit 10 can be compressed in the first direction X to obtain an area for setting the second pixel circuit 20. For example, as ​ shown in the figure, in the first display area, a second pixel circuit 20 is set every set column of the first pixel circuit 10. For example, the number of columns of the first pixel circuit 10 between two adjacent columns of the second pixel circuit 20 can be determined according to needs. In some embodiments of the present disclosure, as ​ and ​ shown in the figure, in order to avoid the situation that the conductive wire is broken or thinned, the orthographic projection of the conductive wire L1 on the substrate BS partially overlaps with the orthographic projection of the pixel circuit 100a of the first pixel unit 101 on the substrate BS.

[0161] In some embodiments of the present disclosure, as ​ and ​As shown, in order to avoid breakage or thinning of the conductive wire, the orthogonal projection of at least one of via V10, via V9, via V7, and via V6 on the substrate BS does not overlap with the orthogonal projection of the conductive wire L1 on the substrate BS. That is, the conductive wire L1 is arranged to avoid at least one of via V10, via V9, via V7, and via V6.

[0162] In some embodiments, the orthogonal projection of via V10, via V9, via V7, and via V6 on the substrate BS does not overlap with the orthogonal projection of the conductive wire L1 on the substrate BS.

[0163] In some embodiments, as ​ shown, a pixel unit only has four vias, namely via V10, via V9, via V7, and via V6, that penetrate the fourth insulating layer, so as to arrange as many conductive wires L1 as possible.

[0164] For example, as ​ shown, via V10, via V9, via V7, and via V6 are arranged in two rows. For example, as ​ shown, via V10, via V9, via V7, and via V6 are arranged in two rows in the horizontal direction. For example, as ​ shown, the connection lines of the two vias in each row extend along the first direction X. For example, as ​ shown, the connection line of via V10 and via V9 extends along the first direction X, and the connection line of via V7 and via V6 extends along the first direction X.

[0165] As ​ and ​As shown, the display panel includes gate lines GT, data lines DT, a first power supply line PL1, a second power supply line PL2, an emission control signal line EML, an initialization signal line INT, a reset control signal line RST, etc. For example, the reset control signal line RST includes a first reset control signal line RST1 and a second reset control signal line RST2. The first power supply line PL1 is configured to supply a constant first voltage signal VDD to the pixel unit 100, the second power supply line PL2 is configured to supply a constant second voltage signal VSS to the pixel unit 100, and the first voltage signal VDD is greater than the second voltage signal VSS. The gate line GT is configured to supply a scan signal SCAN to the pixel unit 100, the data line DT is configured to supply a data signal DATA (data voltage VDATA) to the pixel unit 100, the emission control signal line EML is configured to supply an emission control signal EM to the pixel unit 100, the first reset control signal line RST1 is configured to supply a first reset control signal RESET1 to the pixel unit 100, and the second reset control signal line RST2 is configured to supply a scan signal SCAN to the pixel unit 100. The first initialization signal line INT1 is configured to supply a first initialization signal Vinit1 to the pixel unit 100. The second initialization signal line INT2 is configured to supply a second initialization signal Vinit2 to the pixel unit 100. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 are constant voltage signals, and their magnitudes can, for example, be between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 can both be less than or equal to the second voltage signal VSS. For example, in some embodiments, the first initialization signal line INT1 and the second initialization signal line INT1 are connected and are both configured to supply an initialization signal Vinit to the pixel unit 100, that is, the first initialization signal line INT1 and the second initialization signal line INT2 are both referred to as the initialization signal line INT, and the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal and are both Vinit, but are not limited thereto. In other embodiments, the first initialization signal line INT1 and the second initialization signal line INT1 are insulated from each other to supply signals separately.

[0166] As ​ and ​ As shown, the driving transistor T1 is electrically connected to the light-emitting element 100b and outputs a driving current to drive the light-emitting element 100b to emit light under the control of signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, and the second voltage signal VSS.

[0167] For example, the light-emitting element 100b includes an organic light-emitting diode (OLED). The light-emitting element 100b emits red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit 100a. For example, one pixel includes a plurality of pixel units. One pixel may include a plurality of pixel units that emit different colors of light. For example, one pixel includes a pixel unit that emits red light, a pixel unit that emits green light, and a pixel unit that emits blue light, but is not limited thereto. The number of pixel units included in one pixel and the light-emitting situation of each pixel unit can be determined as needed.

[0168] For example, as ​ and ​ shown, the gate T20 of the data writing transistor T2 is connected to the gate line GT, the first pole T21 of the data writing transistor T2 is connected to the data line DT, and the second pole T22 of the data writing transistor T2 is connected to the first pole T11 of the driving transistor T1.

[0169] For example, as ​ and ​ shown, the pixel circuit 100a further includes a threshold compensation transistor T3. The gate T30 of the threshold compensation transistor T3 is connected to the gate line GT, the first pole T31 of the threshold compensation transistor T3 is connected to the second pole T12 of the driving transistor T1, and the second pole T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.

[0170] For example, as ​ and ​ shown, the display panel further includes a light-emitting control signal line EML. The pixel circuit 100a further includes a first light-emitting control transistor T4 and a second light-emitting control transistor T5. The gate T40 of the first light-emitting control transistor T4 is connected to the light-emitting control signal line EML, the first pole T41 of the first light-emitting control transistor T4 is connected to the first power line PL1, and the second pole T42 of the first light-emitting control transistor T4 is connected to the first pole T11 of the driving transistor T1; the gate T50 of the second light-emitting control transistor T5 is connected to the light-emitting control signal line EML, the first pole T51 of the second light-emitting control transistor T5 is connected to the second pole T12 of the driving transistor T1, and the second pole T52 of the second light-emitting control transistor T5 is connected to the first pole Ea of the light-emitting element 100b.

[0171] As ​ and ​As shown, the first reset transistor T6 is connected to the gate T10 of the driving transistor T1 and is configured to reset the gate of the driving transistor T1. The second reset transistor T7 is connected to the first pole Ea of the light-emitting element 100b and is configured to reset the first pole Ea of the light-emitting element 100b. The first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6. The second initialization signal line INT2 is connected to the first pole Ea of the light-emitting element 100b through the second reset transistor T7. For example, the first initialization signal line INT1 and the second initialization signal line INT2 are connected to be input with the same initialization signal, but not limited thereto. In some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 may also be insulated from each other and are configured to be input with signals respectively.

[0172] For example, as ​ and ​ shown, the first pole T61 of the first reset transistor T6 is connected to the first initialization signal line INT1, the second pole T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1, the first pole T71 of the second reset transistor T7 is connected to the second initialization signal line INT2, and the second pole T72 of the second reset transistor T7 is connected to the first pole Ea of the light-emitting element 100b. For example, as ​ and ​ shown, the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RST1, and the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RST2.

[0173] As ​ and ​ shown, the first power supply line PL1 is configured to provide a first voltage signal VDD to the pixel circuit 100a; the pixel circuit further includes a storage capacitor Cst. The first pole Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1, and the second pole Cb of the storage capacitor Cst is connected to the first power supply line PL1.

[0174] For example, as ​ and ​ shown, the display panel further includes a second power supply line PL2, and the second power supply line PL2 is connected to the second pole 201 of the light-emitting element 100b.

[0175] ​ The first node N1, the second node N2, the third node N3, and the fourth node N4 are shown. For example, in some embodiments, refer to ​ and ​, a capacitance is formed between the first node N1 and the conductive wire L1, a capacitance is formed between the conductive wire L1 and the fourth node N4, and the conductive wire L1 is coupled to the first node N1 and the fourth node N4 respectively, thereby causing a brightness difference and forming display defects such as Mura, which affects the display quality. Embodiments of the present disclosure reduce the brightness difference and improve the display quality by providing a shielding electrode SE.

[0176] ​ It is a schematic diagram of the first pixel unit in a display panel. ​ is ​ A cross-sectional view along line A8 - B8 of

[0177] Refer to ​ and ​ , a buffer layer BL is provided on the substrate substrate BS, an isolation layer BR is provided on the buffer layer BL, an active layer LY0 is provided on the isolation layer BR, a first insulating layer ISL1 is provided on the active layer LY0, a first conductive layer LY1 is provided on the first insulating layer ISL1, a second insulating layer ISL2 is provided on the first conductive layer LY1, a second conductive layer LY2 is provided on the second insulating layer ISL2, a third insulating layer ISL3 is provided on the second conductive layer LY2, a third conductive layer LY3 is provided on the third insulating layer ISL3. The third conductive layer LY3 includes a connection electrode CE01, and the connection electrode CE01 is connected to the second pole T52 of the second light-emitting control transistor T5 through a via H3 penetrating the first insulating layer ISL1, the second insulating layer ISL2, and the third insulating layer ISL3. A fourth insulating layer ISL4 and a fifth insulating layer ISL5 are provided on the third conductive layer LY3, a fourth conductive layer LY4 is provided on the fourth insulating layer ISL4 and the fifth insulating layer ISL5. The fourth conductive layer LY4 includes a connection electrode CE02, and the connection electrode CE02 is connected to the connection electrode CE01 through a via V32 penetrating the fourth insulating layer ISL4. A fifth insulating layer ISL5 is provided on the fourth conductive layer LY4. The light-emitting element 100b (the second light-emitting element 30) is connected to the connection electrode CE02 through a via Vf (such as ​ and ​ shown) connected to the connection electrode CE02. The light-emitting element 100b includes a first pole Ea, a second pole Eb, and a light-emitting functional layer FL located between the first pole Ea and the second pole Eb. For example, the connection element CE0 includes a connection electrode CE01 and a connection electrode CE02.

[0178] For example, the connection electrode CE01 is the connection electrode E5, and the connection electrode CE02 is the connection electrode E6.

[0179] Such as ​As shown, one end of the connection electrode E3 is connected to the gate T10 of the driving transistor T1 through the via Va, and the other end of the connection electrode E3 is connected to the second pole T62 of the first reset transistor T6 through the via V3. One end of the connection electrode E1 is connected to the first initialization signal line INL1 through the via V1, and the other end of the connection electrode E1 is connected to the first pole T61 of the first reset transistor T6 through the via V2. One end of the connection electrode E2 is connected to the second initialization signal line INL2 through the via Vd, and the other end of the connection electrode E2 is connected to the first pole T71 of the second reset transistor T7 through the via Ve. The first power line PL1 is connected to the connection electrode E4 through the via V6, and the connection electrode E4 is connected to the first pole T41 of the first light-emitting control transistor T4 through the via V4. The connection electrode E4 is connected to the second pole Cb of the storage capacitor Cst through the via V5. The first power line PL1 is connected to the second pole Cb of the storage capacitor Cst through the connection electrode E4. The first power line PL1 is connected to the stopper BK through the connection electrode E7. The first power line PL1 is connected to the connection electrode E7 through the via V9, and the connection electrode E7 is connected to the stopper BK through the via Vc. The data line DT is connected to the first pole T21 of the data writing transistor T2 through the connection electrode E8. The data line DT is connected to the connection electrode E8 through the via V10, and the connection electrode E8 is connected to the first pole T21 of the data writing transistor T2 through the via Vb.

[0180] For example, as ​ shown, in the manufacturing process of the display panel, using a self-alignment process, with the first conductive layer LY1 as a mask for the semiconductor pattern layer SC (such as ​Conductivization treatment is performed as shown. The semiconductor pattern layer can be formed by patterning a semiconductor thin film. For example, ion implantation is used to heavily dope the semiconductor pattern layer, so that the portions of the semiconductor pattern layer not covered by the first conductive layer LY1 are conductivized to form the source region (first pole T11) and drain region (second pole T12) of the driving transistor T1, the source region (first pole T21) and drain region (second pole T22) of the data writing transistor T2, the source region (first pole T31) and drain region (second pole T32) of the threshold compensation transistor T3, the source region (first pole T41) and drain region (second pole T42) of the first light emission control transistor T4, the source region (first pole T51) and drain region (second pole T52) of the second light emission control transistor T5, the source region (first pole T61) and drain region (second pole T62) of the first reset transistor T6, and the source region (first pole T71) and drain region (second pole T72) of the second reset transistor T7. The portions of the semiconductor pattern layer covered by the first conductive layer LY1 retain semiconductor characteristics to form the channel regions T13 of the driving transistor T1, the channel regions T23 of the data writing transistor T2, the channel regions T33 of the threshold compensation transistor T3, the channel regions T43 of the first light emission control transistor T4, the channel regions T53 of the second light emission control transistor T5, the channel regions T63 of the first reset transistor T6, and the channel regions T73 of the second reset transistor T7. For example, as ​ shown, the second pole T72 of the second reset transistor T7 and the second pole T52 of the second light emission control transistor T5 are integrally formed; the first pole T51 of the second light emission control transistor T5, the second pole T12 of the driving transistor T1, and the first pole T31 of the threshold compensation transistor T3 are integrally formed; the first pole T11 of the driving transistor T1, the second pole T22 of the data writing transistor T2, and the second pole T42 of the first light emission control transistor T4 are integrally formed; the second pole T32 of the threshold compensation transistor T3 and the second pole T62 of the first reset transistor T6 are integrally formed. In some embodiments, as ​ shown, the first pole T71 of the second reset transistor T7 and the first pole T61 of the first reset transistor T6 can be integrally formed.

[0181] For example, the channel region of the transistor adopted in the embodiments of the present disclosure may be single-crystalline silicon, polycrystalline silicon (such as low-temperature polycrystalline silicon), or metal oxide semiconductor material (such as IGZO, AZO, etc.). In one embodiment, the transistors are all P-type low-temperature polycrystalline silicon (LTPS) thin-film transistors. In another embodiment, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal oxide semiconductor thin-film transistors, that is, the channel material of the transistors is metal oxide semiconductor material (such as IGZO, AZO, etc.). The metal oxide semiconductor thin-film transistor has a low leakage current, which can help reduce the gate leakage current of the driving transistor T1.

[0182] For example, the transistors adopted in the embodiments of the present disclosure may include various structures, such as top-gate type, bottom-gate type, or double-gate structure. In one embodiment, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are double-gate thin-film transistors, which can help reduce the gate leakage current of the driving transistor T1.

[0183] For example, as ​ and ​ shown, the first electrode Ea of the light-emitting element is connected to the connection element CE0 through the via hole Ve.

[0184] For example, as ​ shown, the display panel further includes a pixel definition layer PDL and spacers PS. The pixel definition layer PDL has an opening OPN2, and the opening OPN2 is configured to define the light-emitting area (light-emitting region, effective light-emitting area) of the pixel unit. The spacers PS are configured to support the fine metal mask when forming the light-emitting functional layer FL.

[0185] For example, the opening OPN2 is the light-emitting region of the pixel unit. The light-emitting functional layer FL is located above the first electrode Ea of the light-emitting element 100b, and the second electrode Eb of the light-emitting element 100b is located on the light-emitting functional layer FL. As ​ shown, a packaging layer CPS is provided on the light-emitting element 100b. The packaging layer CPS includes a first packaging layer CPS1, a second packaging layer CPS2, and a third packaging layer CPS3. For example, the first packaging layer CPS1 and the third packaging layer CPS3 are inorganic material layers, and the second packaging layer CPS2 is an organic material layer. For example, the first electrode Ea is the anode of the light-emitting element 100b, and the second electrode Eb is the cathode of the light-emitting element 100b, but it is not limited thereto.

[0186] As ​ and ​As shown, the channels of the respective transistors and the first and second electrodes located on both sides of the channels are located in the active layer LY0; the first reset control signal line RST1, the gate line GT, the gate T10 of the driving transistor (the first electrode Ca of the storage capacitor Cst), the light emission control signal line EML, and the second reset control signal line RST2 are located in the first conductive layer LY1; the first initialization signal line INL1, the second electrode Cb of the storage capacitor Cst, the second initialization signal line INL2, and the stopper BK are located in the second conductive layer LY2; the first part DT2a of the second data line DT, the connection electrodes E1 to E5, the connection electrode E7, and the connection electrode E8 are located in the third conductive layer LY3; the first data line DT1, the first power supply line PL1, the connection electrode E6, and the shielding electrode SE are located in the fourth conductive layer LY4.

[0187] As ​ , and ​ shown, the first initialization signal line INL1, the first reset control signal line RST1, the gate line GT, the light emission control signal line EML, the second initialization signal line INL2, and the second reset control signal line RST2 all extend along the first direction X, and the first part DT2a of the second data line DT extends along the first direction X. As ​ , and ​ shown, shown, the first data line DT1 and the first power supply line PL1 both extend along the second direction Y.

[0188] In an embodiment of the present disclosure, the fact that the orthographic projection of component A on the substrate BS falls within the orthographic projection of component B on the substrate BS means that the orthographic projection of component A on the substrate BS completely falls within the orthographic projection of component B on the substrate BS, that is, the orthographic projection of component A on the substrate BS covers the orthographic projection of component B on the substrate BS, and the area of the orthographic projection of component A on the substrate BS is less than or equal to the area of the orthographic projection of component B on the substrate BS.

[0189] For example, the transistors in the pixel circuit of the embodiments of the present disclosure are all thin-film transistors. For example, the first conductive layer LY1, the second conductive layer LY2, the third conductive layer LY3, and the fourth conductive layer LY4 are all made of metal materials. For example, the first conductive layer LY1 and the second conductive layer LY2 are formed of metal materials such as nickel and aluminum, but are not limited thereto. For example, the third conductive layer LY3 and the fourth conductive layer LY4 are formed of materials such as titanium and aluminum, but are not limited thereto. For example, the third conductive layer LY3 and the fourth conductive layer LY4 are respectively structures formed by three sub-layers of Ti / AL / Ti, but are not limited thereto. For example, the substrate can be a glass substrate or a polyimide substrate, but is not limited thereto and can be selected according to needs. For example, the buffer layer BL, the isolation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, the fourth insulating layer IS4, and the fifth insulating layer ISL5 are all made of insulating materials. The materials of the first electrode Ea and the second electrode Eb of the light-emitting element can be selected according to needs. In some embodiments, the first electrode Ea can be at least one of a transparent conductive metal oxide and silver, but is not limited thereto. For example, the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto. For example, the first electrode Ea can have a structure in which three sub-layers of ITO-Ag-ITO are stacked. In some embodiments, the second electrode Eb can be a metal with a low work function and can be at least one of magnesium and silver, but is not limited thereto.

[0190] For example, referring to the layout diagram and cross-sectional view of the embodiments of the present disclosure, the display panel provided by at least one embodiment of the present disclosure can be fabricated by the following method.

[0191] (1) Form a buffer layer BL and an isolation layer BR on a substrate BS.

[0192] (2) Form a semiconductor thin film on the isolation layer BR.

[0193] (3) Pattern the semiconductor thin film to form a semiconductor pattern layer.

[0194] (4) Form a first insulating thin film on the semiconductor pattern layer.

[0195] (5) Form a first conductive thin film on the first insulating thin film, and pattern the first conductive thin film to form a first conductive layer LY1.

[0196] (6) Dope the semiconductor pattern layer using the first conductive layer LY1 as a mask to form an active layer LY0.

[0197] (7) Form a second insulating thin film on the first conductive layer LY1.

[0198] (8) Form a second conductive thin film on the second insulating layer ISL2, and pattern the second conductive thin film to form a second conductive layer LY2.

[0199] (9) Form a third insulating thin film on the second conductive layer LY2.

[0200] (10) Pattern at least one of the first insulating thin film, the second insulating thin film, and the third insulating thin film to form vias while forming a first insulating layer ISL1, a second insulating layer ISL2, and a third insulating layer ISL3.

[0201] (11) Form a third conductive thin film and pattern the third conductive thin film to form a third conductive layer LY3. Each component in the third conductive layer LY3 is connected to the element located below it through a via.

[0202] (12) Form a fourth insulating thin film and a fifth insulating thin film, and pattern the fourth insulating thin film and the fifth insulating thin film to form vias while forming a fourth insulating layer ISL4.

[0203] (13) Form a fourth conductive thin film and pattern the fourth conductive thin film to form a fourth conductive layer LY4.

[0204] (14) Form a sixth insulating thin film.

[0205] (15) Form at least one insulating material thin film and form at least one transparent conductive layer, and the transparent conductive layer includes a conductive wire L1.

[0206] (16) Form a first electrode Ea of the light-emitting element, and form a fifth insulating layer and at least one insulating material layer.

[0207] (17) Form a pixel definition layer PDL and a spacer layer PS.

[0208] (18) Form a light-emitting functional layer FL.

[0209] (19) Form a second electrode Eb of the light-emitting element.

[0210] (20) Form a packaging layer CPS.

[0211] At least one embodiment of the present disclosure provides a display device including any one of the above display panels.

[0212] ​ And ​ is a schematic diagram of a display device provided by an embodiment of the present disclosure. As ​ And ​ shown, the sensor SS is located on one side of the display panel DS and is located in the second display area R2. Ambient light can pass through the second display area R2 and be sensed by the sensor SS. As ​ shown, the side of the display panel without the sensor SS is the display side and can display an image.

[0213] For example, the display device is a full-screen display device with an under-screen camera. For example, the display device includes an OLED or a product including an OLED. For example, the display device includes any product or component with a display function, such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, etc., containing the above display panel.

[0214] For example, in the embodiments of the present disclosure, the first direction X and the second direction Y are directions parallel to the main surface of the substrate, and the third direction Z is a direction perpendicular to the main surface of the substrate. The main surface of the substrate is the surface for fabricating various components. The upper surface of the substrate in the sectional view is its main surface. For example, the first direction X and the second direction Y intersect. Further for example, the first direction X is perpendicular to the second direction Y. For example, the first direction X is the row direction of the pixel unit, and the second direction Y is the column direction of the pixel unit, but not limited thereto.

[0215] In the display panel provided by the embodiments of the present disclosure, each technical feature with an independent effect can exist independently without relying on other technical features. For example, some embodiments of the display panel may have at least one of the following situations. The following situations can exist independently or can be arbitrarily combined with other situations. The setting effects of each component can be referred to the corresponding parts.

[0216] (1) The first initialization signal line INT1 and the second initialization signal line INT2 are located on the same layer and are located on different layers from the first reset control signal line RST1. The positive projection of the first reset control signal line RST1 on the substrate BS is located between the positive projection of the first initialization signal line INT1 on the substrate BS and the positive projection of the second initialization signal line INT2 on the substrate BS.

[0217] (2) The vias V9 and V10 are arranged along the first direction X. For example, they are located at the same height or horizontally, in the same extension direction as a part of the conductive line L1.

[0218] (3) The vias V7 and V6 are arranged along the first direction X. For example, they are located at the same height or horizontally, in the same extension direction as a part of the conductive line L1.

[0219] (4) A connection electrode E4 is provided to reduce the number of vias penetrating the fourth insulating layer.

[0220] (5) The first power supply line PL1 is located in the fourth conductive layer. The shielding electrode SE and the first power supply line PL1 are of an integral structure, reducing the number of vias penetrating the fourth insulating layer.

[0221] (6) The stopper BK is configured to block the conductive connection portion CP1 of the pixel unit 100 at its position.

[0222] (7) The connecting electrode E1 is disposed obliquely.

[0223] ​ is ​ the operating timing diagram of the pixel circuit shown in the figure. As ​ shown, in a frame display period, the driving method of the pixel unit includes a first reset stage t1, data writing and threshold compensation, a second reset stage t2, and a light emitting stage t3. When the reset control signal RESET is at a low level, the gate of the driving transistor T1 is reset. When the scan signal SCAN is at a low level, the first electrode Ea (for example, the anode) of the light emitting element 100b is reset. For example, as ​ shown, when the scan signal SCAN is at a low level, the data voltage VDATA is written, and at the same time, the threshold voltage Vth of the driving transistor T1 is obtained, and the data voltage VDADA containing the data information on the data line is stored in the capacitor Cst; when the light emission control signal line EML is at a low level, the light emitting element 100b emits light, and the voltage of the first node N1 (gate point) is maintained (the light emission stability of the light emitting element 100b) by the storage capacitor Cst. During the driving process of the pixel circuit 10, in the light emitting stage, the storage capacitor is used to hold the voltage signal so that the potential of its signal holding end is kept constant, and a voltage is formed between the gate and the source of the driving transistor, thereby controlling the driving transistor to form a driving current, and further driving the light emitting element 100b to emit light.

[0224] As ​ shown, in the reset stage t1, the light emission control signal EM is set to the off voltage, the reset control signal RESET is set to the on voltage, and the scan signal SCAN is set to the off voltage.

[0225] As ​ shown, in the data writing and threshold compensation stage and the second reset stage t2, the light emission control signal EM is set to the off voltage, the reset control signal RESET is set to the off voltage, and the scan signal SCAN is set to the on voltage.

[0226] As ​ shown, in the light emitting stage t3, the light emission control signal EM is set to the on voltage, the reset control signal RESET is set to the off voltage, and the scan signal SCAN is set to the off voltage.

[0227] As ​ shown, both the first voltage signal ELVDD and the second voltage signal ELVSS are constant voltage signals. For example, the initialization signal Vinit is between the first voltage signal ELVDD and the second voltage signal ELVSS.

[0228] For example, in the embodiments of the present disclosure, the turn-on voltage refers to the voltage that can turn on the first and second poles of the corresponding transistor, and the turn-off voltage refers to the voltage that can turn off the first and second poles of the corresponding transistor. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (for example, 0V), and the turn-off voltage is a high voltage (for example, 5V); when the transistor is an N-type transistor, the turn-on voltage is a high voltage (for example, 5V), and the turn-off voltage is a low voltage (for example, 0V). ​ The driving waveforms shown are all described by taking the P-type first reset transistor as an example. For example, the turn-on voltage is a low voltage (for example, 0V), and the turn-off voltage is a high voltage (for example, 5V), but it is not limited thereto.

[0229] Please refer to ​ and ​ simultaneously. In the first reset stage t1, the emission control signal EM is at the turn-off voltage, the reset control signal RESET is at the turn-on voltage, and the scan signal SCAN is at the turn-off voltage. At this time, the first reset transistor T6 is in the on state, while the second reset transistor T7, the data writing transistor T2, the threshold compensation transistor T3, the first emission control transistor T4, and the second emission control transistor T5 are in the off state. The first reset transistor T6 transfers the first initialization signal (for example, the initialization voltage Vinit) Vinit1 to the gate of the driving transistor T1 and stores it in the storage capacitor Cst, resets the driving transistor T1, and erases the data stored during the previous (previous frame) emission.

[0230] In the data writing, threshold compensation, and second reset phase t2, the emission control signal EM is at the off voltage, the reset control signal RESET is at the off voltage, and the scan signal SCAN is at the on voltage. At this time, the data writing transistor T2 and the threshold compensation transistor T3 are in the conducting state, the second reset transistor T7 is in the conducting state, and the second reset transistor T7 transmits the second initialization signal (for example, the initialization voltage Vinit) Vinit2 to the first electrode Ea of the light-emitting element 100b to reset the light-emitting element 100b. The first emission control transistor T4, the second emission control transistor T5, and the first reset transistor T6 are in the off state. At this time, the data writing transistor T2 transmits the data voltage VDATA to the first electrode of the driving transistor T1, that is, the data writing transistor T2 receives the scan signal SCAN and the data voltage VDATA and writes the data voltage VDATA to the first electrode of the driving transistor T1 according to the scan signal SCAN. The threshold compensation transistor T3 conducts to connect the driving transistor T1 into a diode structure, whereby the gate of the driving transistor T1 can be charged. After the charging is completed, the gate voltage of the driving transistor T1 is VDATA + Vth, where VDATA is the data voltage and Vth is the threshold voltage of the driving transistor T1, that is, the threshold compensation transistor T3 receives the scan signal SCAN and compensates the threshold voltage for the gate voltage of the driving transistor T1 according to the scan signal SCAN. In this stage, the voltage difference across the storage capacitor Cst is ELVDD - VDATA - Vth.

[0231] In the light-emitting phase t3, the emission control signal EM is at the on voltage, the reset control signal RESET is at the off voltage, and the scan signal SCAN is at the off voltage. The first emission control transistor T4 and the second emission control transistor T5 are in the conducting state, while the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6, and the second reset transistor T7 are in the off state. The first voltage signal ELVDD is transmitted to the first electrode of the driving transistor T1 through the first emission control transistor T4. The gate voltage of the driving transistor T1 remains at VDATA + Vth. The light-emitting current I flows into the light-emitting element 100b through the first emission control transistor T4, the driving transistor T1, and the second emission control transistor T5, and the light-emitting element 100b emits light. That is, the first emission control transistor T4 and the second emission control transistor T5 receive the emission control signal EM and control the light-emitting element 100b to emit light according to the emission control signal EM. The light-emitting current I satisfies the following saturation current formula:

[0232] K(Vgs - Vth) 2 = K(VDATA + Vth - ELVDD - Vth) 2 = K(VDATA - ELVDD) 2

[0233] Among them, μ n is the channel mobility of the driving transistor, Cox is the channel capacitance per unit area of the driving transistor T1, W and L are the channel width and channel length of the driving transistor T1 respectively, and Vgs is the voltage difference between the gate and the source of the driving transistor T1 (i.e., the first pole of the driving transistor T1 in this embodiment).

[0234] It can be seen from the above formula that the current flowing through the light-emitting element 100b is independent of the threshold voltage of the driving transistor T1. Therefore, this pixel circuit compensates well for the threshold voltage of the driving transistor T1.

[0235] ​ Only the initialization voltage Vinit is shown, and the second initialization signal Vinit2 and the first initialization signal Vinit1 can be different signals. That is, the first initialization signal line INT1 and the second initialization signal line INT2 can be insulated from each other to be input with different signals.

[0236] For example, the ratio of the duration of the light-emitting stage t3 to the duration of one frame display period can be adjusted. In this way, the light-emitting brightness can be controlled by adjusting the ratio of the duration of the light-emitting stage t3 to the duration of one frame display period. For example, the ratio of the duration of the light-emitting stage t3 to the duration of one frame display period is adjusted by controlling the scan driving circuit in the display panel or an additionally provided driving circuit.

[0237] For example, the embodiments of the present disclosure are not limited to ​ the specific pixel circuit shown. Pixel circuits that can achieve compensation for the driving transistor can be adopted. Based on the description and teaching of the present disclosure for this implementation manner, other setting manners that can be easily thought of by those of ordinary skill in the art without creative efforts all fall within the protection scope of the present disclosure.

[0238] The above is described by taking the 7T1C pixel circuit as an example. The embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin-film transistors and the number of capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel can also be a structure including other numbers of transistors, such as 7T2C structure, 6T1C structure, 6T2C structure or 9T2C structure. The embodiments of the present disclosure do not limit this. Of course, the display panel can also include pixel circuits with less than 7 transistors.

[0239] In the embodiments of the present disclosure, the elements located on the same layer can be formed by the same film layer through the same patterning process. For example, the elements located on the same layer can be located on the surface of the same element away from the substrate.

[0240] It should be noted that, for clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is enlarged. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there can be intermediate elements.

[0241] In the embodiments of the present disclosure, the patterning or patterning process may only include a lithography process, or include a lithography process and an etching step, or may include other processes such as printing and inkjet for forming a predetermined pattern. The lithography process refers to a process including film formation, exposure, development, etc., and uses photoresist, mask, exposure machine, etc. to form a pattern. The corresponding patterning process can be selected according to the structure formed in the embodiments of the present disclosure.

[0242] It should be noted that in the embodiments of the present disclosure, each type of component may not be numbered in sequence according to the order of appearance. In the claims, each type of component can be numbered in sequence according to the order of appearance.

[0243] The following lists two cases of sequential numbering. In other embodiments, each type of component may have other numbering orders according to different orders of appearance.

[0244] For example, in one case, the via holes V1 - V10 are numbered in sequence and the connection electrodes E1 - E8 are numbered in sequence as shown in Table 1 and Table 2.

[0245] Table 1. Via holes V1 - V10 are numbered in sequence

[0246]

[0247] Table 2. Connection electrodes E1 - E8 are numbered in sequence

[0248]

[0249] For example, in another case, the via holes V1 - V10 are numbered in sequence and the connection electrodes E1 - E8 are numbered in sequence as shown in Table 3 and Table 4.

[0250] Table 3. Via holes V1 - V10 are numbered in sequence

[0251]

[0252] Table 4. Connection electrodes E1 - E8 are numbered in sequence

[0253]

[0254] In the case of no conflict, the features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0255] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A display panel, comprising: A substrate substrate; A pixel unit located on the substrate substrate, including a pixel circuit and a light-emitting element, the pixel circuit being configured to drive the light-emitting element, the pixel circuit including a driving transistor, a first reset transistor, and a second reset transistor, the first reset transistor being connected to the driving transistor and configured to reset the gate of the driving transistor, A first initialization signal line connected to a first pole of the first reset transistor and configured to provide a first initialization signal to the pixel unit, A first reset control signal line, the first reset control signal line being connected to the gate of the first reset transistor; A second initialization signal line, a first pole of the second reset transistor being connected to the second initialization signal line, a second pole of the second reset transistor being connected to a first pole of the light-emitting element, the second reset transistor being configured to reset the first pole of the light-emitting element, Wherein, the first initialization signal line and the second initialization signal line are located on the same layer and are located on different layers from the first reset control signal line, A positive projection of the first reset control signal line on the substrate substrate is located between a positive projection of the first initialization signal line on the substrate substrate and a positive projection of the second initialization signal line on the substrate substrate, The display panel further includes a first power supply line and a first connection electrode, wherein, the first power supply line is configured to provide a constant first voltage signal to the pixel unit, the pixel circuit further includes a first light-emitting control transistor and a storage capacitor, a first pole of the storage capacitor is connected to the gate of the driving transistor, and a second pole of the storage capacitor is connected to the first power supply line through the first connection electrode, The first connection electrode is connected to a first pole of the first light-emitting control transistor through a first via, and the first connection electrode is connected to a second pole of the storage capacitor through a second via, The display panel further includes a fourth connection electrode and a shielding electrode, wherein, the gate of the driving transistor is connected to a second pole of the first reset transistor through the fourth connection electrode, The shielding electrode and the first power supply line are of an integral structure, A positive projection of the shielding electrode on the substrate substrate covers a positive projection of the fourth connection electrode on the substrate substrate.

2. The display panel according to claim 1, wherein, The second initialization signal line is configured to provide a second initialization signal to the pixel unit.

3. The display panel according to claim 1 further includes a second connection electrode and a third connection electrode, wherein, The first power supply line and the first connection electrode are connected through a third via, The pixel circuit further includes a second light-emitting control transistor, a first pole of the second light-emitting control transistor being connected to the driving transistor, The third connection electrode is connected to the second connection electrode through a fourth via, The second connection electrode is connected to a second pole of the second light-emitting control transistor through a fifth via, The fourth via and the third via are arranged along a first direction.

4. The display panel according to claim 3, wherein, A distance from the fourth via to the first initialization signal line is equal to a distance from the third via to the first initialization signal line.

5. The display panel according to any one of claims 1-4, wherein, The first reset control signal line and the first initialization signal line are adjacent to each other, and the first reset control signal line and the second initialization signal line are adjacent to each other.

6. The display panel according to any one of claims 1-4, wherein, The fourth connection electrode is connected to the second pole of the first reset transistor through a sixth via hole. The positive projection of the shielding electrode on the substrate covers the positive projection of the sixth via hole on the substrate.

7. The display panel according to claim 5, wherein, The positive projection of the shielding electrode on the substrate at least partially overlaps with the positive projection of the second pole of the first reset transistor on the substrate.

8. The display panel according to any one of claims 1-4, further comprising a data line, wherein the data line is configured to provide a data signal to the pixel unit, and the data line and the first power supply line are on the same layer.

9. The display panel according to claim 8 further includes a stopper and a fifth connection electrode, wherein, The pixel circuit further includes a threshold compensation transistor. The threshold compensation transistor includes a first channel, a second channel, and a conductive connection portion connecting the first channel and the second channel. The fifth connection electrode is connected to the first power supply line through a seventh via hole, and the fifth connection electrode is connected to the stopper. The positive projection of the stopper on the substrate at least partially overlaps with the positive projection of the conductive connection portion on the substrate. The stopper is configured to block the conductive connection portion of the pixel unit at its position.

10. The display panel according to claim 9 further includes a sixth connection electrode, wherein, The pixel circuit further includes a data writing transistor. The data line is connected to the data writing transistor through the sixth connection electrode. The sixth connection electrode is connected to the data line through an eighth via hole. The seventh via hole and the eighth via hole are arranged along a first direction.

11. The display panel according to claim 10, wherein, The distance from the seventh via hole to the first initialization signal line is equal to the distance from the eighth via hole to the first initialization signal line.

12. The display panel according to claim 8, wherein, The data line includes a first data line and a second data line. The first data line extends along a second direction, and the second data line includes a first portion extending along the first direction. The first portion of the second data line is located between the first initialization signal line and the sixth connection electrode.

13. The display panel according to any one of claims 1-4 further includes a seventh connection electrode, wherein, The first initialization signal line is connected to the first pole of the first reset transistor through the seventh connection electrode. The seventh connection electrode is connected to the first initialization signal line through a ninth via hole, and the seventh connection electrode is connected to the first pole of the first reset transistor through a tenth via hole. Wherein, the first initialization signal line extends along the first direction, and the seventh connection electrode is inclined with respect to the first initialization signal line.

14. The display panel according to claim 13, wherein, The included angle between the extending direction of the seventh connection electrode and the extending direction of the first initialization signal line is an acute angle.

15. The display panel according to claim 14, wherein, The included angle is greater than or equal to 30 degrees and less than or equal to 60 degrees.

16. The display panel according to claim 13, wherein, The first reset transistor includes a first channel and a second channel. The central connection lines of the ninth via hole, the first channel, and the second channel form an acute triangle, and the central connection lines of the tenth via hole, the first channel, and the second channel form an obtuse triangle.

17. The display panel according to claim 13, wherein, The first initialization signal line includes a first overlapping portion overlapping with a first pole of the first reset transistor and a second overlapping portion overlapping with a second pole of the first reset transistor, and the ninth via hole is located between the first overlapping portion and the second overlapping portion.

18. The display panel according to claim 13, wherein, A positive projection of the ninth via hole on the substrate does not overlap with a positive projection of the first pole of the first reset transistor on the substrate, and does not overlap with a positive projection of the second pole of the first reset transistor on the substrate.

19. The display panel according to claim 13, wherein, The ninth via hole and the tenth via hole are located on the same side of the first reset control signal line.

20. The display panel according to claim 13, wherein, The first reset control signal line is located in a first conductive layer, the first initialization signal line and the second initialization signal line are located in a second conductive layer, the seventh connection electrode is located in a third conductive layer, the first conductive layer is closer to the substrate than the second conductive layer, and the second conductive layer is closer to the substrate than the third conductive layer.

21. The display panel according to claim 13 further includes an eighth connection electrode, wherein, The eighth connection electrode is respectively connected to the second initialization signal line and a first pole of the second reset transistor, and the seventh connection electrode is inclined with respect to the eighth connection electrode.

22. The display panel according to claim 21, wherein, An included angle between an extending direction of the seventh connection electrode and an extending direction of the eighth connection electrode is an acute angle.

23. The display panel according to claim 22, wherein, The included angle between the extending direction of the seventh connection electrode and the extending direction of the eighth connection electrode is greater than or equal to 30 degrees and less than or equal to 60 degrees.

24. The display panel according to claim 21, wherein, The ninth via hole and the eighth connection electrode are respectively disposed on opposite sides of a first pole of the first reset transistor.

25. The display panel according to any one of claims 1-4, wherein, The display panel includes a first display area and a second display area, and the first display area is located on at least one side of the second display area. The pixel unit includes a first pixel unit and a second pixel unit. The pixel circuit and the light-emitting element of the first pixel unit are both located in the first display area. The pixel circuit of the second pixel unit is located in the first display area, and the light-emitting element of the second pixel unit is located in the second display area. The pixel circuit of the second pixel unit is connected to the light-emitting element of the second pixel unit through a conductive wire.

26. The display panel according to claim 25, wherein, A positive projection of the conductive wire on the substrate partially overlaps with a positive projection of the pixel circuit of the first pixel unit on the substrate.

27. The display panel according to claim 3 or 4, wherein The display panel further includes a data line, wherein the data line is configured to provide a data signal to the pixel unit, and the data line is located in the same layer as the first power supply line. The display panel further includes a stopper and a fifth connection electrode, wherein the pixel circuit further includes a threshold compensation transistor. The threshold compensation transistor includes a first channel, a second channel, and a conductive connection portion connecting the first channel and the second channel. The fifth connection electrode is connected to the first power supply line through a seventh via hole, and the fifth connection electrode is connected to the stopper. A positive projection of the stopper on the substrate at least partially overlaps with a positive projection of the conductive connection portion on the substrate. The stopper is configured to block the conductive connection portion of the pixel unit at its location. The display panel further includes a sixth connection electrode. Wherein, the pixel circuit further includes a data writing transistor. The data line is connected to the data writing transistor through the sixth connection electrode. The sixth connection electrode is connected to the data line through an eighth via hole. The seventh via hole and the eighth via hole are arranged along the first direction. The display panel includes a first display area and a second display area, and the first display area is located on at least one side of the second display area. The pixel unit includes a first pixel unit and a second pixel unit. The pixel circuit and the light-emitting element of the first pixel unit are both located in the first display area. The pixel circuit of the second pixel unit is located in the first display area, and the light-emitting element of the second pixel unit is located in the second display area. The pixel circuit of the second pixel unit is connected to the light-emitting element of the second pixel unit through a conductive wire. The positive projection of at least one of the eighth via hole, the seventh via hole, the fourth via hole, and the third via hole on the substrate does not overlap with the positive projection of the conductive wire on the substrate.

28. A display device, comprising the display panel according to any one of claims 1-27.

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