Semiconductor memory stack connected to a processing unit and associated methods

Abstract

A semiconductor memory stack connected to a processing unit and associated methods and systems are disclosed. In some embodiments, the semiconductor memory stack can include one or more memory dies attached to and carried by a memory controller die (e.g., high bandwidth memory). Further, a processing unit (e.g., a processor) can be attached to the memory controller die without an intermediary to provide the shortest possible route for signals traveling between the semiconductor memory stack and the processing unit. Additionally, the semiconductor memory stack and the processing unit can be attached to a package substrate without an intermediary.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor device assemblies, and more specifically, to semiconductor memory stacks connected to processing units and associated systems and methods. Background Technology

[0002] Semiconductor packages typically include one or more semiconductor dies (e.g., memory chips, microprocessor chips, imager chips) mounted on a substrate and enclosed within a protective cap. The semiconductor die may contain functional features, such as memory cells, processor circuitry, or imager devices, and bonding pads electrically connected to these functional features. The bonding pads may be electrically connected to corresponding conductive structures on the substrate, which may couple to terminals outside the protective cap, allowing the semiconductor die to be connected to higher-level circuitry. Attached Figure Description

[0003] The following figures provide a better understanding of many aspects of the invention. The components in the figures are not necessarily to scale. Instead, emphasis is placed on clearly illustrating the overall features and principles of the invention.

[0004] Figure 1A A schematic diagram illustrating an example of a semiconductor memory stack according to an embodiment of the present invention.

[0005] Figure 1B The illustration shows an example diagram of an embodiment of the present invention comprising one or more semiconductor memory stacks and a substrate.

[0006] Figure 1C This is an example schematic diagram illustrating a semiconductor die assembly comprising one or more semiconductor memory stacks, processing units, and a substrate, according to an embodiment of the present invention.

[0007] Figure 2 A block diagram illustrating a system comprising a semiconductor die assembly configured according to an embodiment of the present invention.

[0008] Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor die assembly according to an embodiment of the present invention. Detailed Implementation

[0009] The following describes specific details of several embodiments of one or more semiconductor memory stacks connected to processing units and associated systems and methods. The term "semiconductor device or die" generally refers to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include logic devices or dies, memory devices or dies, controllers or microprocessors (e.g., central processing unit (CPU), graphics processing unit (GPU)), etc. Such semiconductor devices may include integrated circuits or components, data storage elements, processing components, and / or other features fabricated on a semiconductor substrate. Furthermore, the term "semiconductor device or die" may refer to a finished device or an assembly or other structure at various processing stages prior to becoming a finished functional device. Depending on the context in which it is used, the term "substrate" may include a semiconductor wafer, a package support substrate, a semiconductor device or die, etc. Those skilled in the art will recognize that appropriate steps of the methods described herein can be performed by processing steps associated with the fabrication of semiconductor devices (wafer level and / or die level) and / or the fabrication of semiconductor packages.

[0010] Some computing systems, such as high-performance computing (HPC) systems, include a processor coupled to a high-bandwidth memory (HBM) comprising one or more memory dies (e.g., DRAM dies) stacked above a controller. In some embodiments, the processor and HBM may be attached side-by-side to an intermediary containing conductive traces, which provides a communication path for signals between the processor and the HBM. In some cases, the intermediary can become a bottleneck in designing computing systems to operate in HPC environments because maintaining the fidelity of signals transmitted and / or received via the intermediary becomes increasingly challenging, for example, due to the distance the signals travel between the HBM and the processor. Furthermore, given the various semiconductor process technologies used to fabricate intermediaries on silicon substrates (e.g., Si intermediaries), the intermediaries increase the assembly cost of the computing system.

[0011] This invention eliminates the need for an intermediary (e.g., a Si intermediary) and provides the shortest possible path for connecting a semiconductor memory stack and a processing unit. The semiconductor memory stack may include one or more memory dies (or a stack of memory dies) attached to and carried by a controller die (e.g., an HBM). As described in more detail herein, the controller die of the semiconductor memory stack may be attached to a package substrate, with its front surface or front side facing away from the package substrate (i.e., the back side of the controller die faces the package substrate) without an intermediary. Additionally, the processing unit may be arranged above the controller die (and the package substrate), with its front surface or front side facing the controller die (and the package substrate). Furthermore, a first region of the processing unit may be directly attached to an uncovered portion of the controller die (i.e., unobstructed by the memory die), allowing an electrical connection to be established between the controller die and the processing unit, e.g., a direct chip-to-chip connection without an intermediary.

[0012] Furthermore, the processing unit can establish an electrical connection with the package substrate without using an intermediary. That is, the second region of the processing unit, which is not directly attached to the controller die, can be coupled to the conductive components (e.g., bonding pads) of the package substrate via conductive pillars and / or solder balls. In this way, the present invention provides the shortest possible path without an intermediary between the semiconductor memory stack (i.e., the controller die carrying the memory die) and the processing unit of the conductive trace, while directly connecting both the semiconductor memory stack (i.e., the controller die carrying the memory die) and the processing unit to the package substrate without an intermediary.

[0013] As used herein, the terms “front,” “back,” “vertical,” “lateral,” “downward,” “upward,” “upper,” and “lower” can refer to the relative orientation or position of features in an assembly of oriented semiconductor devices as shown in the figures. For example, “upper” or “topmost” can refer to a feature positioned closer to the top of the page than another feature. However, these terms should be broadly interpreted to include semiconductor devices with other orientations. Unless otherwise stated, words such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these words are not necessarily intended to indicate a temporal or other priority order of these elements.

[0014] Figure 1A This diagram illustrates an example of a semiconductor memory stack according to an embodiment of the present invention. The semiconductor memory stack may be an example of HBM or an aspect incorporating HBM. Figure 1A A three-dimensional (3D) diagram 100a containing a semiconductor memory stack and a schematic cross-sectional diagram 101a generally corresponding to the 3D diagram 100a.

[0015] Figure 101a illustrates a semiconductor memory stack including a controller die 105 (which may be referred to differently as a controller, interface (IF) die, logic die, HBM controller die, or memory controller die) and a memory die stack 125 attached to the controller die 105. The controller die 105 includes a front side 106 and a back side 107 opposite to the front side 106. The memory die stack 125 is attached to the front side 106 of the controller die 105. The controller die 105 includes active components (e.g., various control circuitry systems, such as interface circuitry, channel control circuitry, etc.) near the front side 106. The controller die 105 may also include a layer 108 having conductive traces (such as multilayer metal layers and vias (which may also be referred to as interconnects)) embedded in a dielectric layer, such that the active components of the controller die 105 can be coupled to the memory die stack 125 and the conductive components 115 of the controller die 105. In some embodiments, the conductive component 115 may include a connection pad comprising copper (Cu), a thin film metal layer stack configured for conductive pillars and / or under-bump metallization, etc.

[0016] like Figure 1A As depicted, the edge of the controller die 105 extends beyond the corresponding edge of the memory die stack 125, such that a portion 110 of the front side 106 of the controller die 105 is not covered by the memory die stack 125. Thus, portion 110 may be referred to as exposed portion 110 and / or uncovered portion 110. In this regard, the controller die 105 can be considered to have an increased die size to include the exposed portion 110 for housing conductive components 115. The exposed portion 110 (containing at least a portion of the conductive components 115) may be placed below a processor die (e.g., a processing unit, microprocessor (e.g., GPU, CPU)) such that the conductive components 115 are directly electrically connected to the corresponding conductive components of the processor die (e.g., direct chip-to-chip connection) without any intermediaries. Furthermore, the controller die 105 may include a through-substrate via (TSV) 120. The TSV 120 is configured to forward electrical signals between the front side 106 and the back side 107 of the controller die 105. For example, the TSV120 can be coupled to the active components of the controller die 105.

[0017] In some embodiments, the semiconductor memory stack of FIG101a can be formed by attaching a memory die stack to the front side of a memory controller die, such that a portion of the front side is exposed (i.e., not covered by the memory die stack). The exposed portion of the memory controller may include a plurality of first conductive components (e.g., conductive component 115). In this regard, the present invention includes increasing the size of the memory controller die such that the memory controller die may have unobstructed portions (e.g., exposed portions, uncovered portions) to place the conductive components therein. The conductive components (e.g., conductive component 115) placed in the exposed portions can be identified for exchanging signals with the processor die, as referenced Figure 1C As described. In this manner, the exposed portion of the memory controller die can be positioned below the area of ​​the processor die facing the memory controller die, so that the front sides of the memory controller die and the processor die can be directly attached to each other.

[0018] Although the foregoing example embodiments have described and illustrated a semiconductor memory stack comprising four (4) memory dies, in other embodiments, semiconductor memory stacks may be provided with different numbers of memory dies. For example, a semiconductor memory stack may contain more than Figure 1A The semiconductor memory depicted in the text stacks smaller (e.g., one, two, three) or larger (e.g., six, eight, twelve, or even larger) numbers of memory dies.

[0019] Figure 1B The illustration shows an example diagram of an embodiment of the present invention comprising one or more semiconductor memory stacks and a substrate. Figure 1B A 3D diagram 100b includes four (4) semiconductor memory stacks mounted on a substrate 130 and a schematic cross-sectional diagram 101b that generally corresponds to the 3D diagram 100b.

[0020] Figure 101a illustrates one of a semiconductor memory stack attached to a substrate 130. The substrate 130 may include a first segment 135 for attaching the semiconductor memory stack and a second segment 145 for directly attaching a processor die. Furthermore, the substrate 130 may include an assembly of conductive components 140 in the first segment 135 and another assembly of conductive components 150 in the second segment 145. The substrate 130 also includes components for attaching to a controller die 105 (and / or a processor die 160, such as...) Figure 3 Substrate terminals 131 for external communication between the conductive components 140 (as depicted in C) and higher-level circuit systems. In some embodiments, the assembly of conductive components 140 may be compatible with forming and / or attaching to a solder ball array (e.g., a ball grid array (BGA)). Furthermore, the assembly of conductive components 150 may be compatible with forming and / or attaching to conductive pillars or solder balls.

[0021] like Figure 1B As depicted, the back side 107 of the controller die 105 can be attached to the substrate 130 via an array of solder balls 155. In this regard, each of the TSVs 120 of the controller die 105 can be connected to a corresponding conductive component 140 in a first segment 135 of the substrate 130 via solder balls 155 in the array. Therefore, the controller die 105 and the substrate 130 can transmit and / or receive signals via at least one of the TSVs 120, which is connected to a corresponding conductive component 140 without including an intermediate layer containing conductive traces.

[0022] As depicted in Figure 101b, a semiconductor memory stack attached to a substrate can be formed by attaching the back side of a memory controller die carrying the memory die stack to the substrate, as described herein. For example, an array of solder balls (e.g., solder ball 155) can be formed on the back side of the memory controller die, with each solder ball coupled to a corresponding TSV (e.g., TSV 120) of the memory controller die. Alternatively, an array of solder balls can be formed on the substrate, with each solder ball coupled to a corresponding conductive component (e.g., conductive component 140) of the substrate. The memory controller die can then be disposed over the substrate such that each of the TSVs is aligned with a corresponding one of the conductive components (e.g., conductive component 140). Furthermore, the memory controller die can be brought to the substrate (or the substrate can be brought to the memory controller) such that each of the TSVs is connected to a corresponding one of the conductive components via solder balls in the array.

[0023] Figure 1C This is an example schematic diagram illustrating a semiconductor die assembly comprising one or more semiconductor memory stacks, processing units, and a substrate, according to an embodiment of the present invention. Figure 1C A 3D view 100c includes a semiconductor die assembly comprising four (4) semiconductor memory stacks and a processor die 160 mounted on a substrate 130, and a schematic cross-sectional view 101c generally corresponding to the 3D view 100c.

[0024] Figure 101c illustrates a semiconductor memory stack attached to a first segment 135 of substrate 130 and a processor die 160 attached to a controller die 105 and a second segment 145 of substrate 130. The processor die 160 includes a first side 161 and a second side 162 opposite to the first side 161. Similar to the controller die 105, the processor die 160 includes various active components (e.g., graphics and computing arrays and peripheral circuitry of a GPU, cache memory, and arithmetic logic circuitry of a CPU) near the first side 161.

[0025] Furthermore, the processor die 160 may include a first group of conductive components 170 disposed in a first region 165 of the first side 161 and a second group of conductive components 180 disposed in a second region 175 of the first side 161. The first group of conductive components 170 and the second group of conductive components 180 are coupled to active components of the processor die 160. In some embodiments, each of the conductive components 170 and / or 180 may be surrounded by a dielectric material such as oxide, nitride, oxynitride, etc. In some embodiments, the conductive component 170 may include a connection pad comprising copper (Cu), a thin film metal layer stack configured for conductive pillars and / or under-bump metallization, etc. Furthermore, the conductive component 180 may be compatible with forming and / or attaching to conductive pillars or solder balls.

[0026] like Figure 1C As depicted, the front side 161 of the processor die 160 faces the front side 106 of the controller die 105 and the substrate 130. For example, the processor die 160 is flipped so that its front side 161 faces downward toward the controller die 105 and the substrate 130. Furthermore, the processor die 160 may be positioned above the controller die 105 such that a first region 165 of the processor die 160 faces and overlaps with the exposed portion 110 of the controller die 105. Additionally, a second region 175 of the processor die 160 faces a second segment 145 of the substrate 130. In this manner, each of the conductive components 115 in the exposed portion 110 can be aligned and coupled to a corresponding conductive component 170 in the first region 165. Similarly, each of the conductive components 150 in the second segment 145 of the substrate 130 can be aligned and coupled to a corresponding conductive component 180 in the second region 175 of the processor die 160.

[0027] In some embodiments, each of the conductive components 115 is aligned with and directly bonded to a corresponding one of the conductive components 170 in the first region 165, and the dielectric material surrounding each of the conductive components 115 (e.g., the dielectric material of layer 108 of the controller die 105) is directly bonded to another dielectric material surrounding each of the conductive components 170. In this regard, since two or more dissimilar materials (e.g., dielectric and conductive materials) are directly bonded together to form interconnects and surround the dielectric layer, such a configuration may be referred to as combined bonding, hybrid bonding, direct bonding, etc. In some embodiments, both conductive components 115 and 170 contain copper as a common primary component, and each of the conductive components 115 is in direct contact with a corresponding one of the conductive components 170. In some embodiments, each of the conductive components 115 or each of the conductive components 170 includes a conductive post (not shown) such that each of the conductive components 115 can be connected to a corresponding one of the conductive components 170 via the conductive post.

[0028] In this manner, the processor die 160 and the controller die 105 can transmit and / or receive signals via at least one of the conductive components 115, which is coupled to a corresponding one of the conductive components 170 without including an intermediary layer containing conductive traces. Therefore, the present invention provides the shortest possible path for connecting a semiconductor memory stack (i.e., the memory die stack 125 carried by the controller die 105) to a processing unit (e.g., a processor die, GPU, CPU).

[0029] Furthermore, conductive components 180 of the processor die 160 may be coupled to corresponding conductive components 150 of the substrate 130. In some embodiments, each of the conductive components 180 includes a conductive post 185, such that the conductive component 180 can be connected to a corresponding one of the conductive components 150 via the conductive post 185. Alternatively, each of the conductive components 150 may include a conductive post 185, such that the conductive component 180 can be connected to a corresponding one of the conductive components 150 via the conductive post 185. In some embodiments, an array of solder balls (not shown) may be disposed between the processor die 160 and the substrate 130, such that each of the conductive components 180 can be connected to a corresponding one of the conductive components 150 via solder balls in the array. In some embodiments, the conductive posts and / or solder balls disposed between the processor die 160 and the substrate 130 may have a certain height and / or distribution to prevent the processor die 160 from tilting and / or sagging, for example, to provide mechanical support for the processor die 160.

[0030] In this manner, the processor die 160 and substrate 130 can transmit and / or receive signals via at least one of the conductive components 180, which is coupled to a corresponding one of the conductive components 150 without including an intermediate layer containing conductive traces. Furthermore, as referenced... Figure 1B As described, the controller die 105 and substrate 130 can also transmit and / or receive signals via at least one of the TSVs 120, which are connected to a corresponding one of the conductive components 140 without including an interposer layer.

[0031] In some embodiments, the two end regions of the processor die 160 may be directly attached to the controller die as depicted in FIG100c. In these embodiments, the central region of the processor die may contain a collection of active components (e.g., various circuit systems) for communicating (or otherwise interfaced) with higher-level circuit systems (e.g., host devices) via connections (e.g., conductive pillars 185 and / or solder balls) established between the processor die 160 and the substrate 130. Thus, the end regions of the processor die may contain another collection of active components for communicating (or otherwise interfaced) with semiconductor memory stacks (e.g., peripheral circuitry of a GPU).

[0032] Although the processor die coupled to four (4) semiconductor memory stacks has been described and illustrated in the foregoing example embodiments, in other embodiments, the processor die may be provided to couple to a different number of semiconductor memory stacks. For example, the processor die may be coupled to a different number of semiconductor memory stacks. Figure 1C The processor die depicted in the text is coupled with a smaller (e.g., one, two, three) or larger number of semiconductor memory stacks (e.g., six, eight, or even more).

[0033] As depicted in FIG101c, a processor die attached to a semiconductor memory stack and a substrate can be formed by attaching the front side 161 of the processor die 160 to the exposed portion of the memory controller die 105 and the second segment 145 of the substrate 130. For example, the processor die (e.g., processor die 160) can be flipped so that its front side 161 faces the memory controller die and the substrate 130. Furthermore, the processor die can be positioned above the memory controller die such that the first segment 165 of the processor die faces the exposed portion 110 (uncovered or unobstructed portion) of the memory controller die. Thus, each of the conductive components 115 of the memory controller die can be aligned with a corresponding conductive component 170 of the processor die. Additionally, the second segment 175 of the processor die can face the second segment 145 of the substrate such that each of the conductive components 180 can be aligned with a corresponding conductive component 150 of the substrate.

[0034] Attach the processor die to the memory controller die:

[0035] In some embodiments, the processor die 160 may be bonded to the memory controller die 105 such that each of the conductive components 115 of the memory controller die is directly bonded to a corresponding one of the conductive components 170 of the processor die. Additionally, a first dielectric material surrounding each of the conductive components 115 of the memory controller die 105 (e.g., the dielectric material of layer 108 of the controller die 105) may be bonded to a second dielectric material surrounding each of the conductive components 170 of the processor die.

[0036] In some embodiments, the processor die 160 may be routed to the memory controller die 105 such that each of the conductive components 115 of the memory controller die is in direct contact with a corresponding conductive component 170 of the processor die. Additionally, both the conductive components 115 and 170 comprise copper as a common primary component.

[0037] In some embodiments, conductive posts (not shown) may be formed on each of the conductive components 115 of the memory controller die or on each of the conductive components 170 of the processor die. The processor die may then be routed to the memory controller die such that each of the conductive components 115 of the memory controller die is connected via a conductive post to a corresponding one of the conductive components 170 of the processor die.

[0038] Attach the processor die to the substrate:

[0039] In some embodiments, conductive posts (e.g., conductive post 185) may be formed on each of the conductive components 180 of the processor die 160 (or alternatively, on each of the conductive components 150 of the substrate). The processor die may then be disposed over the substrate such that each of the conductive components 180 is aligned with a corresponding one of the conductive components 150 of the substrate. Furthermore, the processor die may be led onto the substrate such that each of the conductive components 180 is connected to a corresponding one of the conductive components 150 of the substrate via the conductive post 185.

[0040] In some embodiments, solder balls (not shown) may be formed on each of the conductive components 180 of the processor die 160 (or alternatively, on each of the conductive components 150 of the substrate). The processor die may then be disposed over the substrate such that each of the conductive components 180 is aligned with a corresponding one of the conductive components 150 of the substrate. Furthermore, the processor die may be brought onto the substrate (or vice versa) such that each of the conductive components 180 is connected to a corresponding one of the conductive components 150 of the substrate via solder balls.

[0041] Figure 2 A block diagram illustrating a system 200 comprising a semiconductor die assembly configured according to an embodiment of the present invention is provided. System 200 may include a semiconductor device assembly 270, a power supply 272, a driver 274, a processor 276, and / or other subsystems or components 278. The semiconductor device assembly 270 may be incorporated into any of a variety of larger and / or more complex systems, a representative example being… Figure 2 The system 200 is shown schematically in the image. (Reference) Figure 1C The described semiconductor die assembly may be included in the semiconductor device assembly 270 of system 200.

[0042] Semiconductor device assembly 270 may have features generally similar to those of a semiconductor die assembly. For example, semiconductor device assembly 270 may include one or more semiconductor memory stacks, each having a controller die carrying one or more memory dies (e.g., a memory die stack). Furthermore, semiconductor device assembly 270 may include a processor die attached to the controller die to provide the shortest possible path for connecting the semiconductor memory stacks and the processor die. Additionally, semiconductor device assembly 270 may include a substrate carrying both the semiconductor memory stacks and the processor die without an intermediary. The resulting system 270 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative system 270 may include, but is not limited to, handheld devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, and appliances. Components of system 270 may be housed in a single unit or distributed across multiple interconnect units (e.g., via a communication network). Components of system 270 may also include remote devices and any of a wide variety of computer-readable media.

[0043] Figure 3 A flowchart 300 is a method for manufacturing a semiconductor die assembly according to an embodiment of the present invention. Flowchart 300 may include, as referenced... Figures 1A to 1C Aspects of the described method.

[0044] The method includes attaching a memory die stack to the front side of a memory controller die, such that a portion of the front side is exposed, the exposed portion including a plurality of first conductive components (box 310). The method further includes attaching the memory controller die carrying the memory die stack to a first set of third conductive components in a first segment of a substrate, the substrate further including a second set of third conductive components in a second segment of the substrate (box 315). The method further includes attaching a processor die to the memory controller die and the substrate, the processor die including a first group of second conductive components in a first region on the front side of the processor die and a second group of second conductive components in a second region on the front side of the processor die, such that 1) the first region faces the exposed portion of the memory controller die, and each of the first conductive components is coupled to a corresponding one of the second conductive components in the first group, and 2) the second region faces the second segment of the substrate, and each of the second conductive components in the second group is coupled to a corresponding one of the third conductive components in the second set (box 320).

[0045] In some embodiments, attaching a processor die to a memory controller die includes: disposing the processor die over the memory controller die such that each of the first conductive components is aligned with a corresponding one of the second conductive components in the first group; and bonding the processor die to the memory controller die to directly bond each of the first conductive components to a corresponding one of the second conductive components in the first group, wherein a first dielectric material surrounding each of the first conductive components is simultaneously bonded to a second dielectric material surrounding each of the second conductive components in the first group.

[0046] In some embodiments, attaching a processor die to a memory controller die includes: positioning the processor die over the memory controller die such that each of the first conductive components is aligned with a corresponding one of the second conductive components in the first group; and guiding the processor die to the memory controller die such that each of the first conductive components is in direct contact with a corresponding one of the second conductive components in the first group, wherein the first conductive components and the second conductive components in the first group include copper as a common principal component.

[0047] In some embodiments, attaching a processor die to a memory controller die includes: forming a conductive post on each of the first conductive components or each of the second conductive components in the first group; and distributing the processor die over the memory controller die such that each of the first conductive components is aligned with a corresponding one of the second conductive components in the first group; and leading the processor die to the memory controller die such that each of the first conductive components is connected via a conductive post to a corresponding one of the second conductive components in the first group.

[0048] In some embodiments, attaching the processor die to the substrate includes: forming solder balls on each of the second conductive components in the second group; arranging the processor die over the substrate such that each of the second conductive components in the second group is aligned with a corresponding one of the third conductive components in the second set; and leading the processor die to the substrate such that each of the second conductive components in the second group is connected to a corresponding one of the third conductive components in the second set via solder balls.

[0049] In some embodiments, attaching the processor die to the substrate includes: forming a conductive post on each of the second conductive components in the second group; disposing the processor die over the substrate such that each of the second conductive components in the second group is aligned with a corresponding one of the third conductive components in the second set; and leading the processor die to the substrate such that each of the second conductive components in the second group is connected via the conductive post to a corresponding one of the third conductive components in the second set.

[0050] In some embodiments, the memory controller die includes a plurality of through-silicon vias (TSVs) configured to forward electrical signals between the front and back sides of the memory controller die, and attaching the memory controller die to the substrate includes: forming arrays of solder balls, each coupled to a corresponding TSV; arranging the memory controller die above the substrate such that each of the TSVs is aligned with a corresponding third conductive component in a first set; and leading the memory controller die to the substrate such that each of the TSVs is connected to a corresponding third conductive component in the first set via solder balls in the array.

[0051] It should be noted that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments of two or more of the methods may be combined. From the foregoing, it should be understood that although specific embodiments of the technology have been described herein for illustrative purposes, various modifications may be made without departing from this disclosure. Additionally, although certain features or components have been shown to have certain arrangements or configurations in the illustrated embodiments, other arrangements and configurations are possible. Furthermore, in other embodiments, certain aspects of the inventive technology described in the context of a particular embodiment may be combined or eliminated.

[0052] Devices, including semiconductor devices, can be formed on semiconductor substrates or dies such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0053] As used herein (included in the claims), “or” when used in a list of items (e.g., a list of items ending with phrases such as “at least one of” or “one or more of”) indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase “based on” should not be considered a reference to a closed set of conditions. For example, an exemplary step described as “based on condition A” may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase “based on” should be interpreted in the same manner as the phrase “at least partially based on”.

[0054] As should be understood from the foregoing, although specific embodiments of the invention have been described herein for illustrative purposes, various modifications may be made without departing from the scope of the invention. Specifically, numerous specific details are set forth in the foregoing description to provide a thorough and illustrative description of embodiments of the invention. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of these specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail so as not to obscure other aspects of the technology. Generally, it should be understood that various other devices, systems, and methods, besides those specific embodiments disclosed herein, are also within the scope of the invention.

Claims

1. A semiconductor die assembly comprising: A memory controller die that carries a stack of memory dies on its front side, wherein the edge of the memory controller die extends beyond the corresponding edge of the memory die stack, such that a portion of the front side of the memory controller die is not covered by the memory die stack, the portion comprising a plurality of first conductive components; A processor die comprising a first group of second conductive components in a first region on the front side of the processor die and a second group of second conductive components in a second region on the front side of the processor die, wherein the processor die is disposed above the memory controller die such that the first region of the processor die faces the portion of the memory controller die, and each of the first conductive components is coupled to a corresponding one of the second conductive components in the first group; as well as A substrate that carries both the memory controller die and the processor die, the substrate comprising a second set of third conductive components in a second segment of the substrate, wherein the processor die is disposed above the substrate such that the second segment of the processor die faces the second segment, and each of the second conductive components in the second set is coupled to a corresponding one of the third conductive components in the second set.

2. The semiconductor die assembly of claim 1, wherein each of the first conductive components is aligned with and directly bonded to a corresponding one of the second conductive components in the first group, and a first dielectric material surrounding each of the first conductive components is directly bonded to a second dielectric material surrounding each of the second conductive components in the first group.

3. The semiconductor die assembly of claim 1, wherein both the first conductive component and the second conductive component in the first group comprise copper as a common main component, and each of the first conductive components is in direct contact with the corresponding one of the second conductive components in the first group.

4. The semiconductor die assembly of claim 1, wherein each of the first conductive components or each of the second conductive components in the first group includes a conductive post, and each of the first conductive components is connected via the conductive post to the corresponding one of the second conductive components in the first group.

5. The semiconductor die assembly of claim 1, wherein the processor die and the memory controller die transmit and / or receive signals via at least one of the first conductive components, wherein the at least one of the first conductive components is coupled to the corresponding one of the second conductive components without including an intermediary layer comprising conductive traces.

6. The semiconductor die assembly of claim 1, wherein each of the second conductive components in the second group is connected via solder balls to the corresponding one of the third conductive components in the second set.

7. The semiconductor die assembly of claim 1, wherein each of the second conductive components in the second group includes a conductive post, and each of the second conductive components in the second group is connected via the conductive post to the corresponding one of the third conductive components in the second set.

8. The semiconductor die assembly of claim 1, wherein the processor die and the substrate transmit and / or receive signals via at least one of the second conductive components, the at least one of the second conductive components being coupled to the corresponding one of the third conductive components without including an intermediary layer comprising conductive traces.

9. The semiconductor die assembly according to claim 1, wherein: The memory controller die includes a plurality of through-silicon vias (TSVs) configured to forward electrical signals between the front side and the back side of the memory controller die. The back side of the memory controller die is attached to the substrate via an array of solder balls; and Each of the TSVs is connected via solder balls in the array to a corresponding third conductive component in a first set of third conductive components in a first segment of the substrate.

10. The semiconductor die assembly of claim 9, wherein the memory controller die and the substrate transmit and / or receive signals via at least one of the TSVs, the at least one of the TSVs being coupled to the corresponding one of the third conductive components without including an intermediary layer comprising conductive traces.

11. A method comprising: A memory die stack is attached to the front side of a memory controller die, such that a portion of the front side is exposed, the exposed portion containing a plurality of first conductive components; The memory controller die, which carries the memory die stack, is attached to a first set of third conductive components in a first segment of a substrate, the substrate also containing a second set of third conductive components in a second segment of the substrate; as well as A processor die is attached to the memory controller die and the substrate, the processor die comprising a first group of second conductive components in a first region on the front side of the processor die and a second group of second conductive components in a second region on the front side of the processor die, such that 1) the first region faces the exposed portion of the memory controller die, and each of the first conductive components is coupled to a corresponding one of the second conductive components in the first group, and 2) the second region faces the second segment of the substrate, and each of the second conductive components in the second group is coupled to a corresponding one of the third conductive components in the second set.

12. The method of claim 11, wherein attaching the processor die to the memory controller die comprises: The processor die is positioned above the memory controller die such that each of the first conductive components is aligned with a corresponding one of the second conductive components in the first group; and The processor die is bonded to the memory controller die to directly bond each of the first conductive components to the corresponding one of the second conductive components in the first group, wherein a first dielectric material surrounding each of the first conductive components is simultaneously bonded to a second dielectric material surrounding each of the second conductive components in the first group.

13. The method of claim 11, wherein attaching the processor die to the memory controller die comprises: The processor die is positioned above the memory controller die such that each of the first conductive components is aligned with a corresponding one of the second conductive components in the first group; and The processor die is led to the memory controller die such that each of the first conductive components is in direct contact with the corresponding one of the second conductive components in the first group, wherein the first conductive components and the second conductive components in the first group comprise copper as a common main component.

14. The method of claim 11, wherein attaching the processor die to the memory controller die comprises: A conductive post is formed on each of the first conductive components or on each of the second conductive components in the first group; The processor die is positioned above the memory controller die such that each of the first conductive components is aligned with a corresponding one of the second conductive components in the first group; and The processor die is routed to the memory controller die such that each of the first conductive components is connected via the conductive post to the corresponding one of the second conductive components in the first group.

15. The method of claim 11, wherein attaching the processor die to the substrate comprises: Solder balls are formed on each of the second conductive components in the second group; The processor die is positioned above the substrate such that each of the second conductive components in the second group is aligned with a corresponding one of the third conductive components in the second set; and The processor die is brought to the substrate such that each of the second conductive components in the second group is connected via the solder ball to the corresponding one of the third conductive components in the second set.

16. The method of claim 11, wherein attaching the processor die to the substrate comprises: A conductive post is formed on each of the second conductive components in the second group; The processor die is positioned above the substrate such that each of the second conductive components in the second group is aligned with a corresponding one of the third conductive components in the second set; and The processor die is brought to the substrate such that each of the second conductive components in the second group is connected via the conductive post to the corresponding one of the third conductive components in the second set.

17. The method of claim 11, wherein the memory controller die includes a plurality of through-silicon vias (TSVs) configured to forward electrical signals between the front side and the back side of the memory controller die, and wherein attaching the memory controller die to the substrate comprises: Form an array of solder balls, each coupled to its corresponding TSV; The memory controller die is arranged above the substrate such that each of the TSVs is aligned with the corresponding one of the third conductive components in the first set; as well as The memory controller die is brought to the substrate such that each of the TSVs is connected to the corresponding one of the third conductive components in the first set via solder balls in the array.

18. A semiconductor die assembly comprising: A first memory controller carries a first memory die stack on its front side, wherein the edge of the first memory controller extends beyond the corresponding edge of the first memory die stack, such that a portion of the front side of the first memory controller is exposed, the exposed portion including a first plurality of conductive components; A second memory controller carries a second memory die stack on its front side, wherein the edge of the second memory controller extends beyond the corresponding edge of the second memory die stack, such that a portion of the front side of the second memory controller is exposed, the exposed portion containing a second plurality of conductive components; A processor comprising a first group, a second group, and a third group of conductive components on its front side, wherein the processor is disposed above both the first memory controller and the second memory controller, such that each of the first plurality of conductive components is coupled to a corresponding one of the conductive components in the first group, and each of the second plurality of conductive components is coupled to a corresponding one of the conductive components in the third group. as well as A substrate that carries the first memory controller, the second memory controller, and the processor, the substrate comprising a second set of conductive components, wherein the processor is disposed above the substrate such that each of the conductive components in the second set is coupled to a corresponding one of the conductive components in the second set.

19. The semiconductor die assembly of claim 18, wherein: The first memory controller includes a first plurality of through-silicon vias (TSVs) configured to forward electrical signals between the front and back sides of the first memory controller; The back side of the first memory controller is attached to the substrate via a first array of solder balls, wherein each of the first plurality of TSVs is connected to a corresponding conductive component in a first set of conductive components of the substrate via solder balls in the first array; The second memory controller includes a second plurality of TSVs configured to forward electrical signals between the front and back sides of the second memory controller; and The back side of the second memory controller is attached to the substrate via a second array of solder balls, wherein each of the second plurality of TSVs is connected to a corresponding conductive component in a third set of conductive components of the substrate via solder balls in the second array.

20. The semiconductor die assembly of claim 18, wherein: The processor and the first memory controller transmit and / or receive signals via at least one of the first plurality of conductive components, wherein the at least one of the first plurality of conductive components is coupled to a corresponding one of the conductive components in the first group without including an intermediary layer comprising conductive traces; and The processor and the second memory controller transmit and / or receive signals via at least one of the second plurality of conductive components, wherein the at least one of the second plurality of conductive components is coupled to the corresponding one of the conductive components in the third group without including the intermediate layer.

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