Display panel and display device

Abstract

This disclosure relates to the field of display technology, providing a display panel and a display device. The display panel includes a substrate and a second source / drain metal layer. The substrate has a display area and a non-display area. The non-display area includes multiple sub-regions arrayed in a row-column direction. Each sub-region in the same column corresponds to a shift register unit of a specific level in the same gate driving circuit, and each sub-region in the same row corresponds to the same level shift register unit in each gate driving circuit. The second source / drain metal layer includes multiple output signal lines, each output signal line corresponding to a shift register unit. Among the multiple output signal lines located in the same pixel row, the output signal line connected to the shift register unit furthest from the display area, when projected onto the substrate, passes through the sub-region corresponding to the shift register unit closest to the display area. This saves space occupied by the gate driving circuit near the display area in the column direction, facilitating the implementation of a narrow bezel in the display panel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] Display devices are increasingly pursuing high PPI and narrow bezels. Therefore, the design of narrow bezels in the GOA (Graphical Object Layout) is particularly important. In related technologies, the panel cannot achieve a narrow bezel due to the limitations of the GOA circuit layout structure.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device.

[0005] According to one aspect of this disclosure, a display panel is provided, including a display area and a non-display area surrounding the display area. The non-display area includes a plurality of gate driving circuits, each gate driving circuit including a plurality of cascaded shift register units, wherein each shift register unit in each gate driving circuit that provides a gate driving signal for a sub-pixel in the same row is located in the same row. The display panel further includes a substrate having the display area and the non-display area, the non-display area including a plurality of sub-regions arrayed in a row-column direction, each sub-region in the same column corresponding to a shift register unit at each stage in the same gate driving circuit. Each sub-region of a row corresponds to the same level shift register unit of each gate driving circuit; a second source-drain metal layer is located on one side of the substrate, the second source-drain metal layer includes: multiple output signal lines extending along the row direction in the orthographic projection of the substrate, the output signal lines being correspondingly arranged with each of the shift register units; wherein, among the multiple output signal lines located in the same pixel row, the output signal line connected to the shift register unit far from the display area passes through the sub-region corresponding to the shift register unit close to the display area in the orthographic projection of the substrate, and the output signal lines of the same pixel row are separated from each other.

[0006] In an exemplary embodiment of this disclosure, the shift register unit includes a pull-up node and a pull-down node. The pull-up node is used to control the output transistor connected thereto to output a conduction level, and the pull-down node is used to control the output transistor connected thereto to output a non-conducting level. The output signal line connected to the shift register unit away from the display area is projected onto the substrate in a positive projection, while the projections of the pull-up node and the pull-down node in the shift register unit near the display area are both separated from the projections onto the substrate.

[0007] In an exemplary embodiment of this disclosure, the display panel further includes: a first conductive layer located on the side of the substrate facing the second source / drain metal layer, the first conductive layer including: a first connecting line extending in a row direction in the orthographic projection of the substrate, the first connecting line being used to form the pull-up node; and a second connecting line extending in a row direction in the orthographic projection of the substrate, the second connecting line being used to form the pull-down node; wherein, the first connecting line and the second connecting line in any Nth row of the gate driving circuit near the display area are located in the orthographic projection of the Nth row output signal line and the (N+1)th row output signal line in the gate driving circuit away from the display area between the orthographic projections of the Nth row output signal line and the (N+1)th row output signal line in the gate driving circuit away from the display area in the orthographic projection of the substrate, where N is a natural number.

[0008] In an exemplary embodiment of this disclosure, each of the gate driving circuits is located on the same side of the display area.

[0009] In an exemplary embodiment of this disclosure, at least a portion of the gate driving circuit includes a first component and a second component disposed opposite to each other on both sides of the display area. A shift register unit in the first component is connected to a portion of the sub-pixels of the display area via a first output signal line connected thereto. A shift register unit in the second component is connected to another portion of the sub-pixels in the display area via a second output signal line connected thereto. The projection of any first output signal line onto the substrate and the projection of the pull-up and pull-down nodes in the shift register unit located between the first component and the display area onto the substrate are both separate. Similarly, the projection of any second output signal line onto the substrate and the projection of the pull-up and pull-down nodes in the shift register unit located between the second component and the display area onto the substrate are both separate.

[0010] In an exemplary embodiment of this disclosure, a plurality of gate driving circuits include a first driving group and a second driving group disposed on both sides of the display area; wherein, in each output signal line of the same driving group, the orthographic projection of the output signal line connected to the shift register unit away from the display area on the substrate is separate from the orthographic projection of the pull-up node and the pull-down node in the shift register unit near the display area on the substrate.

[0011] In an exemplary embodiment of this disclosure, the plurality of gate driving circuits include at least one first structure gate driving circuit, wherein each stage of the first structure gate driving circuit is connected to a plurality of output signal lines; wherein, the projection of any output signal line connected to the first structure gate driving circuit onto the substrate and the projection of the pull-up node and pull-down node in the shift register unit located between the first structure gate driving circuit and the display area onto the substrate are both separate.

[0012] In an exemplary embodiment of this disclosure, the plurality of gate driving circuits include at least one second structure gate driving circuit. Each stage of the second structure gate driving circuit includes a first sub-shift register unit and a second sub-shift register unit disposed opposite to each other on both sides of the display area. The first sub-shift register unit and the second sub-shift register unit respectively provide gate driving signals to the same row of sub-pixels through the corresponding output signal lines. The projection of any output signal line connected to the second structure gate driving circuit onto the substrate and the projection of the pull-up node and pull-down node in the shift register unit located between the second structure gate driving circuit and the display area onto the substrate are both separate.

[0013] In an exemplary embodiment of this disclosure, the shift register unit further includes a first transistor, the gate of which is connected to the pull-up node, the first electrode receiving a first signal, and the second electrode connected to an output terminal; the display panel further includes an active layer located on the side of the substrate facing the second source / drain metal layer, the active layer including: a plurality of first active structures extending along the column direction and spaced apart in the row direction in the orthographic projection of the substrate, each first active structure including at least a first active portion and a second active portion and a third active portion connected to both sides of the first active portion in the column direction, the first active portion forming the channel region of the first transistor, and the second active portion and the third active portion forming the first electrode and the second electrode of the first transistor; a plurality of second active structures extending along the column direction and spaced apart in the row direction in the orthographic projection of the substrate. The second active structure includes at least a fourth active portion and a fifth and a sixth active portion connected in the column direction to both sides of the fourth active portion. The fourth active portion is used to form the channel region of the second transistor, and the fifth and sixth active portions are used to form the first and second electrodes of the second transistor. The first conductive layer further includes: a first gate line extending in the row direction on the orthographic projection of the first active portion on the substrate and covering the orthographic projection of the first active portion on the substrate, a portion of the structure of the first gate line being used to form the gate of the first transistor, and the first gate line being connected to the first connection line; and a second gate line extending in the row direction on the orthographic projection of the fourth active portion on the substrate, a portion of the structure of the second gate line being used to form the gate of the second transistor, and the second gate line being connected to the second connection line.

[0014] In an exemplary embodiment of this disclosure, a first active structure includes a first structural portion, a second structural portion, and a third structural portion connected sequentially in a column direction. Each of the first and third structural portions includes two first active portions and one third active portion. The second structural portion includes one second active portion. The first conductive layer includes four first gate lines, and the first connecting lines connect to each of the first gate lines. The display panel further includes a first source / drain metal layer located on the side of the first conductive layer facing the second source / drain metal layer. The first source / drain metal layer includes a first transmission line extending in a row direction on the orthographic projection of the substrate and located on the orthographic projection of the second active portion on the substrate. The first transmission line connects to each of the second active portions via vias to output a first signal to the first transistor. A second transmission line forms the output terminal. The second transmission line extends in a row direction on the orthographic projection of the substrate and is located on the orthographic projection of the third active portion on the substrate. The second transmission line connects to its corresponding third active portion and the output signal line via vias to connect the second electrode of the first transistor to the output terminal.

[0015] In an exemplary embodiment of this disclosure, the first electrode of the second transistor receives a second signal, and the second electrode is connected to an output terminal; a second active structure includes a fourth structural portion, a fifth structural portion, and a sixth structural portion connected sequentially in a column direction, each of the fourth and sixth structural portions including two fourth active portions and one sixth active portion, and the fifth structural portion including one fifth active portion; the first conductive layer includes four second gate lines, and the second connecting lines are respectively connected to each of the second gate lines; the first source-drain metal layer further includes: a third transmission line extending in the row direction of the orthographic projection of the substrate and located on the orthographic projection of the fifth active portion on the substrate, the third transmission line connecting each of the fifth active portions through vias to output a second signal to the second transistor; and a fourth transmission line extending in the row direction of the orthographic projection of the substrate and located on the orthographic projection of the sixth active portion on the substrate, the fourth transmission line connecting its corresponding sixth active portion and the output signal line through vias to connect the second electrode of the second transistor to an output terminal.

[0016] In an exemplary embodiment of this disclosure, the shift register unit further includes a first capacitor and a second capacitor. The first terminal of the first capacitor is connected to the pull-up node, and the second terminal is connected to the output terminal. The first terminal of the second capacitor is connected to the pull-down node, and the second terminal is connected to the output terminal. The capacitance values ​​of the first capacitor and the second capacitor are both greater than or equal to 2pF.

[0017] In an exemplary embodiment of this disclosure, the second connecting line is located on the side of the first connecting line near the display area; the first conductive layer further includes: a first conductive portion connected to the side of the first connecting line near the display area in the horizontal direction, the first conductive portion being used to form a first electrode of the first capacitor; a second conductive portion connected to the side of the second connecting line near the display area in the horizontal direction, the second conductive portion being used to form a first electrode of the second capacitor; the display panel further includes: a second conductive layer located between the first conductive layer and the first source / drain metal layer, the second conductive layer including: a third conductive portion, the projection of which onto the substrate intersects with the first conductive portion in the horizontal direction. The first source / drain metal layer further includes: a fifth conductive portion, whose orthogonal projection on the substrate at least partially overlaps with the orthogonal projection of the second conductive portion on the substrate, and the fifth conductive portion being connected to the first conductive portion through a via; and a sixth conductive portion, whose orthogonal projection on the substrate at least partially overlaps with the orthogonal projection of the fourth conductive portion on the substrate, and the sixth conductive portion being connected to the second conductive portion through a via.

[0018] In an exemplary embodiment of this disclosure, the display panel further includes a second conductive layer, a first source / drain metal layer, and a first planarization layer sequentially stacked on one side of the first conductive layer toward the second source / drain metal layer; wherein the thickness of the first planarization layer is inversely proportional to the capacitance value of the first capacitor and the capacitance value of the second capacitor.

[0019] In an exemplary embodiment of this disclosure, the thickness of the first planarization layer is greater than or equal to 2000 nm.

[0020] In an exemplary embodiment of this disclosure, the display panel further includes: an interlayer insulating layer located between the second conductive layer and the first source / drain metal layer; wherein the ratio of the thickness of the first planarization layer to the thickness of the interlayer insulating layer is greater than or equal to 4.

[0021] In an exemplary embodiment of this disclosure, the display panel further includes: a first passivation layer, which covers the first planarization layer on the side of the first planarization layer opposite to the substrate, wherein the thickness of the first passivation layer is less than the thickness of the first planarization layer.

[0022] In an exemplary embodiment of this disclosure, the second connecting line is located on the side of the first connecting line near the display area; the first conductive layer further includes: a first conductive portion connected to the side of the first connecting line near the display area in the horizontal direction, the first conductive portion being used to form a first electrode of the first capacitor; a second conductive portion connected to the side of the second connecting line near the display area in the horizontal direction, the second conductive portion being used to form a first electrode of the second capacitor; the second conductive layer includes: a third conductive portion whose orthogonal projection on the substrate at least partially overlaps with the orthogonal projection of the first conductive portion on the substrate, the third conductive portion being used to form a second electrode of the first capacitor; a fourth conductive portion whose orthogonal projection on the substrate at least partially overlaps with the orthogonal projection of the second conductive portion on the substrate, the fourth conductive portion being used to form a second electrode of the second capacitor; the first source / drain metal layer includes: a fifth conductive portion, on the substrate... The first conductive portion has a first cutout that overlaps at least with the first conductive portion's orthogonal projection on the substrate, and the fifth conductive portion is connected to the first conductive portion via a via; the sixth conductive portion has a first cutout that overlaps at least with the fourth conductive portion's orthogonal projection on the substrate, and the sixth conductive portion is connected to the second conductive portion via a via; the second source / drain metal layer further includes: a seventh conductive portion whose orthogonal projection on the substrate at least partially overlaps with the fifth conductive portion's orthogonal projection on the substrate, and the seventh conductive portion is connected to the third conductive portion via a via; and an eighth conductive portion whose orthogonal projection on the substrate at least partially overlaps with the sixth conductive portion's orthogonal projection on the substrate, and the eighth conductive portion is connected to the fourth conductive portion via a via; wherein the first planarization layer has a first cutout facing the seventh conductive portion and a second cutout facing the eighth conductive portion, the first cutout exposing the seventh conductive portion and the second cutout exposing the eighth conductive portion.

[0023] According to a second aspect of this disclosure, a display device is also provided, including the display panel described in any embodiment of this disclosure.

[0024] The display panel disclosed herein includes multiple gate driving circuits. The output signal lines of the gate driving circuits are arranged by adding a second source-drain metal layer. The output signal lines of the gate driving circuits away from the display overlap with the coverage area of ​​the gate driving circuits near the display area. That is, the output signal lines of the gate driving circuits away from the display area pass over the area covered by the gate driving circuits near the display area. In this way, the space occupied by the gate driving circuits near the display area in the column direction can be saved, thereby avoiding the situation where the space in the column direction is too small and the space in the row direction is squeezed. This is beneficial to the realization of narrow bezels and high ppi of the display panel.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0027] Figure 1 This is a schematic diagram of the structure of a display panel according to one embodiment of the present disclosure;

[0028] Figure 2 The layout structure of the multi-gate drive circuit GOA in the related technology is shown;

[0029] Figure 3 This is a circuit diagram of the output circuit in a shift register unit according to one embodiment of the present disclosure;

[0030] Figure 4 According to one embodiment of the present disclosure Figure 3 The structural layout of the equivalent circuit;

[0031] Figure 5 for Figure 4 Layout of the middle pull-up node and the first transistor;

[0032] Figure 6 for Figure 4 The structural layout at the middle pull-down node and the second transistor;

[0033] Figure 7 for Figure 5 The structural layout of the active layer;

[0034] Figure 8 for Figure 6 The structural layout of the active layer;

[0035] Figure 9 for Figure 5 Structural layout of the first conductive layer;

[0036] Figure 10 for Figure 6 Structural layout of the first conductive layer;

[0037] Figure 11 for Figure 5 Structural layout of the first source / drain metal layer;

[0038] Figure 12 for Figure 6Structural layout of the first source / drain metal layer;

[0039] Figure 13 for Figure 5 Structural layout of the second source / drain metal layer;

[0040] Figure 14 for Figure 6 Structural layout of the second source / drain metal layer;

[0041] Figure 15 for Figure 5 A stacked layout of an active layer and a first conductive layer;

[0042] Figure 16 for Figure 6 A stacked layout of an active layer and a first conductive layer;

[0043] Figure 17 for Figure 5 The stacked layout of the first conductive layer and the second source / drain metal layer;

[0044] Figure 18 for Figure 6 The stacked layout of the first conductive layer and the second source / drain metal layer;

[0045] Figure 19 This is a cross-sectional view of the capacitor structure in a shift register unit according to an embodiment of the present disclosure;

[0046] Figure 20 This is a cross-sectional view of the capacitor structure in a shift register unit according to another embodiment of the present disclosure;

[0047] Figure 21 This is a circuit diagram of a portion of the structure in a shift register unit in related technologies;

[0048] Figure 22 To Figure 21 The circuit diagram shown is the improved circuit diagram.

[0049] Figure 23 This is a schematic diagram of the layout structure of a gate drive circuit according to another embodiment of the present disclosure.

[0050] Figure 24 This is a schematic diagram of the layout structure of a gate driving circuit according to another embodiment of the present disclosure.

[0051] Figure 25 This is a schematic diagram of the layout structure of a gate driving circuit according to another embodiment of the present disclosure.

[0052] Figure 26 This is a schematic diagram of the layout structure of a gate drive circuit according to another embodiment of the present disclosure. Detailed Implementation

[0053] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. Matching reference numerals in the drawings denote matching or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0054] Figure 1 This is a schematic diagram of the structure of a display panel according to one embodiment of the present disclosure, as shown below. Figure 1 As shown, the display panel may include a display area and a non-display area. The non-display area may surround the display area and may include multiple gate drive circuits (GOAs). Each gate drive circuit (GOA) includes multiple cascaded shift register units (GOAs(n)). The shift register units (GOAs(n)) that provide gate drive signals for the same row of sub-pixels in each gate drive circuit (GOA) are located in the same row. The display panel may also include a substrate and a second source / drain metal layer (SD2). The substrate has a display area and a non-display area. The non-display area includes multiple sub-regions distributed in a Y-array along the row and column direction. Each sub-region in the same column corresponds to a shift register unit (GOA(n)) in the same gate drive circuit (GOA), and each sub-region in the same row corresponds to a gate drive unit (GOA(n)). The same level shift register unit GOA(n) of the dynamic circuit GOA; the second source-drain metal layer SD2 is located on one side of the substrate, and the second source-drain metal layer SD2 may include multiple output signal lines G-out. The orthographic projection of the multiple output signal lines G-out on the substrate extends along the row direction X. The output signal lines G-out are correspondingly set with each shift register unit GOA(n); among the multiple output signal lines G-out located in the same pixel row, the orthographic projection of the output signal line G-out connected to the shift register unit GOA(n) far away from the display area on the substrate passes through the sub-region corresponding to the shift register unit GOA(n) close to the display area, and the output signal lines G-out in the same pixel row are separated from each other.

[0055] The display panel disclosed herein includes multiple gate drive circuits (GOAs). The output signal lines G-out of the gate drive circuits GOA are arranged by adding a second source-drain metal layer SD2. The output signal lines G-out of the gate drive circuits GOA far from the display overlap with the coverage area of ​​the gate drive circuits GOA near the display area. That is, the output signal lines G-out of the gate drive circuits GOA far from the display area pass over the area covered by the gate drive circuits GOA near the display area. In this way, the space occupied by the gate drive circuits GOA near the display area in the column direction Y can be saved, thereby avoiding the situation where the space in the column direction Y is too small and occupies the space in the row direction X. This is beneficial to the realization of narrow bezels and high ppi of the display panel.

[0056] The gate drive circuit (GOA) can be located, for example, on the X-side of the display area in the horizontal direction. The GOA is used for horizontal scanning of the display panel. A GOA typically includes multiple shift register units (GOA(n)) cascaded to output horizontal scanning signals step-by-step. The display area of ​​the panel contains pixel circuits (e.g., 3T1C, 7T1C, etc.) corresponding to each sub-pixel. These pixel circuits provide driving current to the sub-pixels, causing them to emit light. Each pixel circuit typically contains multiple signal terminals with different functions. These terminals provide driving signals according to a specific timing sequence, causing the pixel circuit to output driving current. Different functional gate drive circuits (GOAs) are used to provide corresponding gate drive signals to different signal terminals of the pixel circuits; that is, the GOA outputs gate drive signals according to a specific timing sequence to drive the pixel circuits and provide driving current.

[0057] The shift register units GOA(n) in the gate drive circuit GOA of this disclosure can be distributed sequentially in the column direction Y and located on at least one side of the display area in the row direction X. Furthermore, the display panel typically includes multiple gate drive circuits GOA, such that the shift register units GOA(n) in the multiple gate drive circuits GOA are arrayed along the row and column direction Y in the non-display area.

[0058] In different gate drive circuits, the same-level shift register unit GOA(n) can be understood as a shift register unit GOA(n) that provides gate drive signals to different signal terminals in the same pixel circuit. For example, a display panel may include an EM gate drive circuit that provides EM signals to the pixel circuit and a Reset gate drive circuit that provides reset signals. In this case, the shift register unit GOA(n) in the EM gate drive circuit that provides EM signals to the nth row of pixel circuits and the shift register unit GOA(n) in the Reset gate drive circuit that provides Reset signals to the nth row of pixel circuits are the same-level shift register unit GOA(n).

[0059] Each sub-region in the same column corresponds to a shift register unit GOA(n) of each level in the same gate drive circuit GOA, and each sub-region in the same row corresponds to the same level shift register unit GOA(n) in each gate drive circuit GOA. Thus, one shift register unit GOA(n) corresponds to one sub-region. The sub-region disclosed herein can be understood as the area covered by the orthographic projection of the shift register unit GOA(n) onto the substrate. It is known that a shift register unit GOA(n) typically includes transistors, capacitors, and various signal lines. The structures forming transistors, capacitors, and signal lines with different functions are typically distributed across two or more conductive layers. Correspondingly, the area covered by the orthographic projection of the layers of all transistors, all capacitors, and all signal lines forming a shift register unit GOA(n) onto the substrate is the sub-region corresponding to that shift register unit GOA(n).

[0060] The output signal line G-out is located on the second source-drain metal layer SD2, and it is the trace for the output gate drive signal of the shift register unit GOA(n). The output signal line G-out and the shift register unit GOA(n) can be configured such that one shift register unit GOA(n) corresponds to one output signal line G-out, in which case one shift register unit GOA(n) drives one pixel row; or multiple output signal lines G-out can be configured for one shift register unit GOA(n), in which case one shift register unit GOA(n) drives multiple pixel rows.

[0061] The multiple output signal lines G-out located in the same pixel row of this disclosure can be understood as output signal lines G-out that transmit different types of gate drive signals to the pixel circuit of the same row. The output signal lines G-out in the same pixel row are separated from each other to avoid signal interference between the output signal lines G-out.

[0062] The output signal line G-out connected to the shift register unit GOA(n) far from the display area is projected onto the substrate and passes through the sub-region corresponding to the shift register unit GOA(n) near the display area. Specifically, the output signal line G-out connected to the shift register unit GOA(n) far from the display area overlaps with the shift register unit GOA(n) near the display area. More specifically, the output signal line G-out connected to the shift register unit GOA(n) far from the display area can cross the sub-region where the shift register unit GOA(n) near the display area is located from the second source-drain metal layer SD2, that is, it crosses over the sub-region where the shift register unit GOA(n) near the display area is located. Thus, the output signal line G-out connected to the shift register unit GOA(n) located away from the display area does not need to occupy additional column direction Y space, thereby saving column direction Y space for the shift register unit GOA(n) located closer to the display area. This ensures sufficient column direction Y space for the shift register unit GOA(n) while significantly reducing its row direction X space, allowing the display panel to achieve a narrow bezel. Furthermore, because the output signal line G-out connected to the gate drive circuit GOA located away from the display area does not occupy additional column direction Y space, the display panel of this disclosure can achieve a high PPI gate drive circuit GOA.

[0063] In contrast. Figure 2 The layout structure of the multi-gate drive circuit GOA in the related art is shown, such as... Figure 2 As shown, in a multi-GOA side-by-side design, the GOA units closer to the display area need to reserve output signal lines for GOA units further away from the display area. Therefore, the vertical layout design space of the GOA units closer to the display area is less than the size of one row of pixels. Furthermore, the closer a GOA unit is to the display area, the more output signal lines it traverses, further reducing the vertical space of the GOA unit layout. This compression of vertical space increases horizontal space, leading to a larger bezel and preventing the panel from achieving a narrow bezel. Moreover, when there are many GOAs, the vertical space of the GOA units closer to the display area may be insufficient to cover the width of a single transistor, making layout design impossible. (Comparison) Figure 1 and Figure 2 As can be seen, the display panel disclosed herein can save space occupied by the gate drive circuit in the row direction compared with the prior art, thereby enabling the panel to achieve a narrow bezel.

[0064] The following is a further introduction to this publicly disclosed plan.

[0065] Typically, a shift register unit GOA(n) includes a pull-up node PU and a pull-down node PD. The pull-up node PU controls the output transistor connected to it to output a conducting level, and the pull-down node PD controls the output transistor connected to it to output a non-conducting level. Here, the pull-up node PU controlling the output transistor connected to it to output a conducting level can be understood as the pull-up node PU controlling the output transistor connected to it to output a level signal that enables the corresponding transistor in the pixel circuit to conduct. Similarly, the pull-down node PD controlling the output transistor connected to it to output a non-conducting level can be understood as the pull-down node PD controlling the output transistor connected to it to output a level signal that enables the corresponding transistor in the pixel circuit to turn off. It should be understood that the conducting and non-conducting levels mentioned here are related to the type of transistor in the pixel circuit. For example, when the transistor in the pixel circuit connected to the output signal line G-out is an N-type transistor, then the pull-up node PU can specifically be used to control the output transistor connected to it to output a high-level signal, and the pull-down node PD can specifically be used to control the output transistor connected to it to output a low-level signal. Alternatively, when the transistor in the pixel circuit is a P-type transistor, the pull-up node PU can be used to control the output transistor connected to it to output a low-level signal, and the pull-down node PD can be used to control the output transistor connected to it to output a high-level signal.

[0066] In the layout structure of the gate driving circuit disclosed herein, the output signal line G-out connected to the shift register unit GOA(n) far from the display area crosses the sub-region corresponding to the shift register unit GOA(n) close to the display area. Each point inside the gate driving circuit GOA has a different signal, and the output signal line G-out also transmits a transition signal. Thus, capacitive coupling noise exists between the output signal line G-out and the shift register unit GOA(n) it crosses. In particular, the pull-up node PU and pull-down node PD in the shift register unit are more susceptible to capacitive coupling noise interference. This noise affects the signal output of the crossed shift register unit GOA(n), thereby causing display problems. To address this problem, this disclosure further improves the layout structure of the gate driving circuit GOA in the display panel.

[0067] As described above, the output signal line G-out connected to the shift register unit GOA(n) far from the display area needs to cross the shift register unit close to the display area. Based on this, the orthographic projection of the output signal line G-out connected to the shift register unit GOA(n) far from the display area onto the substrate is separate from the orthographic projections of the pull-up node PU and pull-down node PD in the shift register unit GOA(n) close to the display area onto the substrate. That is, the orthographic projection of the output signal line G-out connected to the shift register unit GOA(n) far from the display area onto the substrate does not overlap with the orthographic projections of the pull-up node PU and pull-down node PD in the shift register unit GOA(n) being crossed. It is worth noting that in the layout structure, the pull-up node PU and pull-down node PD are typically traces with a certain extension length. Therefore, this exemplary embodiment is equivalent to the output signal line G-out connected to the shift register unit GOA(n) far from the display area avoiding the traces forming the pull-up node PU and the traces forming the pull-down node PD in the shift register unit GOA(n) being crossed. Thus, this exemplary embodiment can reduce the noise interference of the output signal line G-out to the pull-up node PU and pull-down node PD in the crossed shift register unit GOA(n), ensuring that the crossed shift register unit GOA(n) outputs a stable gate drive signal and can perform row scanning normally.

[0068] Figure 3 Here is a circuit diagram of the output circuit in a shift register unit according to one embodiment of the present disclosure, such as... Figure 3As shown, in an exemplary embodiment, the output transistor connected to the pull-up node PU is a first transistor T1, and the output transistor connected to the pull-down node PD is a second transistor T2. The gate of the first transistor T1 is connected to the pull-up node PU, its first terminal receives a first signal S1, and its second terminal is connected to the output terminal. The gate of the second transistor T2 is connected to the pull-down node PD, its first terminal receives a second signal S2, and its second terminal is connected to the output terminal. Both the first signal S1 and the second signal S2 can be DC signals; alternatively, the first signal S1 can be a clock signal provided by a clock signal line, and the second signal S2 can be a DC signal provided by a power supply line. The first signal S1 and the second signal S2 can have opposite polarities; that is, when the first signal S1 is high, the second signal S2 is low; or, when the first signal S1 is low, the second signal S2 is high. When the pull-up node PU is on (the on-level can be, for example, high), PU controls the first transistor T1 to turn on, transmitting the first signal S1 received at the first terminal to the output, causing the shift register unit GOA(n) to output a high-level signal, thus achieving shift output. When the pull-down node PD is on (the on-level can be, for example, high), PD controls the second transistor T2 to turn on. The on-level second transistor T2 transmits the second signal S2 received at the first terminal to the output, causing the shift register unit GOA(n) to output a low-level signal. Of course, the on-level can also be low. The following only uses... Figure 3 The circuit structure shown is used as an example to further illustrate the scheme disclosed herein.

[0069] The display panel disclosed herein may include a substrate and an active layer ACT, a first conductive layer Gate1, a second conductive layer Gate2, a first source / drain metal layer SD1, and a second source / drain metal layer SD2, which are sequentially stacked on one side of the substrate. An insulating layer may be disposed between the above functional layers.

[0070] Figure 4 According to one embodiment of the present disclosure Figure 3 The structural layout of the equivalent circuit, such as Figure 4As shown in the figure, a schematic diagram illustrates the structure of the output signal line G-out connecting the region containing the pull-up node PU, pull-down node PD, first transistor T1, second transistor T2, first capacitor C1, and second capacitor C2 in a shift register unit near the display area to a shift register unit far from the display area. The output signal line G-out in the figure is the output signal line connected to the gate drive circuit GOA far from the display area. It can be seen that the output signal line G-out connected to the shift register unit far from the display area crosses over and avoids the pull-up node PU and pull-down node PD in the shift register unit being crossed. Furthermore, in the same shift register unit, the first transistor T1, first capacitor C1, second transistor T2, and second capacitor C2 are located on one side of the display area from far to near. The orthographic projections of the pull-up node PU and pull-down node PD on the substrate both extend along the row direction.

[0071] It should be understood that when a structure A in this disclosure extends along direction B, it means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip shape. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending in other directions.

[0072] Figure 5 for Figure 4 The structural layout at the pull-up node and the first transistor. Figure 6 for Figure 4 The structural layout at the middle pull-down node and the second transistor. Figure 7 for Figure 5 The structural layout of the active layer is shown. Figure 8 for Figure 6 The structural layout of the active layer is shown. Figure 9 for Figure 5 The structural layout of the first conductive layer in the middle. Figure 10 for Figure 6 The structural layout of the first conductive layer in the middle. Figure 11 for Figure 5 The structural layout of the first source / drain metal layer in the middle. Figure 12 for Figure 6 The structural layout of the first source / drain metal layer in the middle. Figure 13 for Figure 5 Structural layout of the second source / drain metal layer. Figure 14 for Figure 6 Structural layout of the second source / drain metal layer. Figure 15 for Figure 5 The stacked layout of the active layer and the first conductive layer is shown. Figure 16 for Figure 6 The stacked layout of the active layer and the first conductive layer is shown. Figure 17 for Figure 5The stacked layout of the first conductive layer and the second source / drain metal layer in the middle. Figure 18 for Figure 6 The stacked layout of the first conductive layer and the second source / drain metal layer.

[0073] like Figure 5 , Figure 7 and Figure 15 As shown, in an exemplary embodiment, the active layer ACT may include a plurality of first active structures ACT01 and a plurality of second active structures ACT02. The plurality of first active structures ACT01 extend along the column direction Y and are spaced apart in the row direction X in the orthogonal projection of the substrate. Each first active structure ACT01 includes at least a first active portion ACT1 and a second active portion ACT2 and a third active portion ACT3 connected on both sides of the first active portion ACT1 in the column direction Y. The first active portion ACT1 is used to form the channel region of the first transistor T1, and the second active portion ACT2 and the third active portion ACT3 are used to form the first electrode and the second electrode of the first transistor T1.

[0074] Continue to refer to Figure 5 , Figure 7 and Figure 15 In an exemplary embodiment, a first active structure ACT01 may include a first structural portion ACT01-1, a second structural portion ACT01-2, and a third structural portion ACT01-3 connected sequentially in the column direction Y. Both the first structural portion ACT01-1 and the third structural portion ACT01-3 may include two first active portions ACT1 and one third active portion ACT3. The second structural portion ACT01-2 may include one second active portion ACT2. Correspondingly, the first conductive layer Gate1 may include four first gate lines G1, and first connecting lines CL1 connect each first gate line G1. Thus, multiple parallel small transistors are formed through the active layer ACT and the first conductive layer Gate1, and these multiple parallel small transistors constitute... Figure 3 The first transistor T1 in the process.

[0075] like Figure 6 , Figure 8 and Figure 16 As shown, in an exemplary embodiment, a plurality of second active structures ACT02 extend along the column direction Y and are spaced apart in the row direction X in the orthogonal projection of the substrate. Each second active structure ACT02 includes at least a fourth active portion ACT4 and a fifth active portion ACT5 and a sixth active portion ACT6 connected to both sides of the fourth active portion ACT4 in the column direction Y. The fourth active portion ACT4 is used to form the channel region of the second transistor T2, and the fifth active portion ACT5 and the sixth active portion ACT6 are used to form the first electrode and the second electrode of the second transistor T2.

[0076] Continue to refer to Figure 6 , Figure 8 and Figure 16 In an exemplary embodiment, a second active structure ACT02 includes a fourth structural portion ACT02-4, a fifth structural portion ACT02-5, and a sixth structural portion ACT02-6 connected sequentially in the column direction Y. Both the fourth structural portion ACT02-4 and the sixth structural portion ACT02-6 include two fourth active portions ACT4 and one sixth active portion ACT6. The fifth structural portion ACT02-5 includes one fifth active portion ACT5. Correspondingly, the first conductive layer Gate1 includes four second gate lines G2, and second connection lines CL2 connect each second gate line G2. Thus, multiple parallel small transistors are formed through the active layer ACT and the first conductive layer Gate1. These parallel small transistors form... Figure 3 The second transistor T2 is shown.

[0077] like Figure 5 , Figure 9 and Figure 15 As shown, in an exemplary embodiment, the first conductive layer Gate1 may include a first gate line G1, a first connection line CL1, a second gate line G2, and a second connection line CL2. The first connection line CL1 can be used to form Figure 3 The pull-up node PU and the second connecting line CL2 can be used to form Figure 3 The pull-down node PD is shown in the figure. It is worth noting that in this exemplary embodiment, only a partial layout structure of the shift register unit is shown. In the complete layout structure, the orthographic projection of the first connection line CL1 onto the substrate and the orthographic projection of the second connection line CL2 onto the substrate are both traces extending along the row direction X. Furthermore, in the equivalent circuit of the shift register unit, the pull-down node PD also connects to other devices. Therefore, a portion of the structure forming the second connection line CL2 of the pull-down node PD passes through the region corresponding to the first transistor T1, such as... Figure 9 As shown, a portion of the structure of the second connection line CL2 is located between the first gate lines G1 in two adjacent rows in the region corresponding to the first transistor T1.

[0078] The first gate line G1 extends along the row direction X in the orthographic projection of the first active portion ACT1 on the substrate and covers the orthographic projection of the first active portion ACT1 on the substrate. A portion of the structure of the first gate line G1 is used to form the gate of the first transistor T1, and the first gate line G1 is connected to the first connection line CL1 to connect the gate of the first transistor T1 to the pull-up node PU. The second gate line G2 extends along the row direction X in the orthographic projection of the second active portion ACT4 on the substrate and covers the orthographic projection of the fourth active portion ACT4 on the substrate. A portion of the structure of the second gate line G2 is used to form the gate of the second transistor T2, and the second gate line G2 is connected to the second connection line CL2 to connect the gate of the second transistor T2 to the pull-down node PD.

[0079] like Figure 5and Figure 11 In an exemplary embodiment, the first source / drain metal layer SD1 may include a first transmission line TL1 to a fourth transmission line TL4. The first transmission line TL1 extends along the row direction X in the orthographic projection of the substrate and is located on the orthographic projection of the second active part ACT2 on the substrate. The first transmission line TL1 is connected to each of the second active parts ACT2 through vias to output a first signal S1 to the first transistor T1. The second transmission line TL2 can be used to form an output terminal. The second transmission line TL2 extends along the row direction X in the orthographic projection of the substrate and is located on the orthographic projection of the third active part ACT3 on the substrate. The second transmission line TL2 can be connected to the corresponding third active part ACT3 and the output signal line G-out through vias to connect the second electrode of the first transistor T1 to the output terminal.

[0080] like Figure 11 As shown, in an exemplary embodiment, the first source / drain metal layer SD1 may further include multiple first signal lines SG1. The multiple first signal lines SG1 extend along the column direction Y and are spaced apart in the row direction X in the orthogonal projection of the substrate. The first signal lines SG1 are used to transmit the first signal S1, and the first signal lines SG1 are configured in a one-to-one correspondence with the first transmission lines TL1, thereby outputting the first signal S1 to the first transmission lines TL1.

[0081] like Figure 6 and Figure 12 In an exemplary embodiment, the third transmission line TL3 extends along the row direction X in the orthographic projection of the substrate and is located on the orthographic projection of the fifth active part ACT5 on the substrate. The third transmission line TL3 is connected to each of the fifth active parts ACT5 through vias to output the second signal S2 to the second transistor T2. The fourth transmission line TL4 extends along the row direction X in the orthographic projection of the substrate and is located on the orthographic projection of the sixth active part ACT6 on the substrate. The fourth transmission line TL4 can be connected to the corresponding sixth active part ACT6 and the output signal line G-out through vias to connect the second electrode of the second transistor T2 to the output terminal.

[0082] In addition, the first source / drain metal layer SD1 may also include multiple second signal lines (not shown in the figure). The projection of the multiple second signal lines onto the substrate may extend along the column direction Y and be spaced apart in the row direction X. The second signal lines are used to transmit the second signal S2, and the second signal lines are arranged in a one-to-one correspondence with the third transmission line TL3, thereby outputting the second signal S2 to the third transmission line TL3.

[0083] like Figure 13 and Figure 14As shown, the second source-drain metal layer SD2 may include multiple output signal lines G-out. The output signal lines G-out can be connected to the second transmission line TL2 and the fourth transmission line TL4 in the shift register unit GOA(n) to be connected via vias, so as to connect to the output terminal of the shift register unit GOA(n).

[0084] In the complete layout structure, the structure forming the first transistor T1 and the structure forming the second transistor T2 can be spaced apart in the row direction X, so that the output signal line G-out of the shift register unit GOA(n) can be connected to the second transmission line TL2 through a via at the position corresponding to the second transmission line TL2, and connected to the fourth transmission line TL4 through a via at the position corresponding to the fourth transmission line TL4.

[0085] like Figure 3 As shown, each shift register unit GOA(n) may also include a first capacitor C1 and a second capacitor C2. The first terminal of the first capacitor C1 is connected to the pull-up node PU, and the second terminal is connected to the output terminal. The first terminal of the second capacitor C2 is connected to the pull-down node PD, and the second terminal is connected to the output terminal. The first capacitor C1 can use the signal at the output terminal to bootstrap the pull-up node PU and control the pull-up node PU to maintain a stable potential. Therefore, increasing the capacitance of the first capacitor C1 can improve the anti-interference capability of the pull-up node PU. Similarly, the second capacitor C2 can use its stored charge to regulate the voltage of the pull-down node PD, i.e., maintain the potential stability of the pull-down node PD. Therefore, increasing the capacitance of the second capacitor C2 can also improve the anti-interference capability of the pull-down node PD.

[0086] In the exemplary embodiment, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 can both be greater than or equal to 2pF, for example, 2pF, 2.5pF, 3pF, 3.5pF, 4pF, etc. In the prior art, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 are usually 0.5pF. Compared with the prior art, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 in this exemplary embodiment are greatly improved, thereby reducing the noise interference of the output signal line G-out on the pull-up node PU and pull-down node PD in the crossed shift register unit GOA(n).

[0087] Furthermore, it should be understood that capacitive coupling noise is inevitably generated between adjacent metal traces in the layout structure. Therefore, when setting the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2, this disclosure needs to fully consider the influence of capacitive coupling noise between traces so that the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2 are large enough to cover these capacitive coupling noises.

[0088] The following section, in conjunction with the accompanying drawings, discusses the increase... Figure 3 The structure of the first capacitor C1 and the second capacitor C2 will be further described.

[0089] Figure 19 This is a cross-sectional view of the capacitor structure in a shift register unit according to an embodiment of the present disclosure, as shown below. Figure 19 As shown, the first conductive layer Gate1 may further include a first conductive portion 100, which is connected to the side of the first connecting line CL1 in the horizontal direction X near the display area. The first conductive portion 100 is used to form the first electrode of the first capacitor C1. The second conductive layer Gate2 may further include a third conductive portion 300, the orthographic projection of the third conductive portion 300 on the substrate at least partially overlaps with the orthographic projection of the first conductive portion 100 on the substrate, and the third conductive portion 300 is used to form the second electrode of the first capacitor C1. The first source / drain metal layer SD1 may further include a fifth conductive portion 500, the orthographic projection of the fifth conductive portion 500 on the substrate at least partially overlaps with the orthographic projection of the second conductive portion on the substrate, and the fifth conductive portion 500 is connected to the first conductive portion 100 through a via.

[0090] In this configuration, the first conductive part 100 and the third conductive part 300 at least partially overlap in their orthogonal projections onto the substrate, meaning there is an overlap in the thickness direction of the substrate. This overlap forms a first capacitor structure. Similarly, the fifth conductive part 500 overlaps with the third conductive part 300 to form a second capacitor structure, and the fifth conductive part 500 is connected to the first conductive part 100 via a via. Thus, the first capacitor structure and the second capacitor structure are connected in parallel to form a first capacitor C1, giving the first capacitor C1 a "sandwich structure," which increases its capacitance. It is understood that increasing the capacitance of the first capacitor C1 enhances its voltage regulation effect on the pull-up node PU, thereby improving the anti-interference performance of the pull-up node PU and reducing noise interference from the output signal line G-out to the pull-up node PU in the crossed shift register unit GOA(n).

[0091] It should be understood. Figure 19The three-layer structure shown for increasing the first capacitor can also be applied to the second capacitor C2. For example, the first conductive layer Gate1 may further include a second conductive portion connected to the side of the second connecting line CL2 in the horizontal direction X near the display area, and the second conductive portion is used to form the first electrode of the second capacitor C2; the second conductive layer Gate2 may further include a fourth conductive portion, the orthographic projection of the fourth conductive portion on the substrate at least partially overlapping the orthographic projection of the second conductive portion on the substrate, and the fourth conductive portion is used to form the second electrode of the second capacitor C2; the first source / drain metal layer SD1 may further include a sixth conductive portion, the orthographic projection of the sixth conductive portion on the substrate at least partially overlapping the orthographic projection of the fourth conductive portion on the substrate, and the sixth conductive portion is connected to the second conductive portion through a hole. Similarly, the second conductive part overlaps with the fourth conductive part to form the third capacitor structure, and the sixth conductive part overlaps with the fourth conductive part to form the fourth capacitor structure. The sixth conductive part is connected to the second conductive part through a via, so that the first capacitor structure and the second capacitor structure are connected in parallel to form the second capacitor C2. This can increase the capacitance value of the second capacitor C2. The increased capacitance value of the second capacitor C2 can reduce the noise interference of the output signal line G-out to the pull-down node PD in the crossed shift register unit GOA(n).

[0092] In some embodiments of this disclosure, the two conductive portions forming the capacitor structure can completely overlap. For example, the first conductive portion 100 and the third conductive portion 300 can completely overlap, such that the orthographic projection of one of the first conductive portion 100 and the third conductive portion 300 onto the substrate covers the orthographic projection of the other onto the substrate, thereby maximizing the capacitance value formed by the two conductive portions. Furthermore, this structure can also be applied to capacitor structures formed by other conductive portions, thereby further increasing the capacitance values ​​of the first capacitor C1 and the second capacitor C2.

[0093] As can be seen, in this exemplary embodiment, by adding a fifth conductive part 500 and a sixth conductive part to the first source-drain metal layer SD1, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 can be increased, thereby reducing the noise interference of the output signal line G-out to the pull-up node PU and pull-down node PD in the shift register unit GOA(n) that is crossed.

[0094] Figure 20 This is a cross-sectional view of the capacitor structure in a shift register unit according to another embodiment of the present disclosure, as shown below. Figure 20As shown in this exemplary embodiment, the first conductive layer Gate1 may include a first conductive portion 100 and a second conductive portion. The first conductive portion 100 is connected to the side of the first connecting line CL1 in the horizontal direction X near the display area, and the first conductive portion 100 is used to form the first electrode of the first capacitor C1. The second conductive layer Gate2 may include a third conductive portion 300. The orthographic projection of the third conductive portion 300 on the substrate at least partially overlaps with the orthographic projection of the first conductive portion 100 on the substrate, and the third conductive portion 300 is used to form the second electrode of the first capacitor C1. The first source / drain metal layer SD1 may include a fifth conductive portion 500. The orthographic projection of the fifth conductive portion 500 on the substrate at least partially overlaps with the orthographic projection of the second conductive portion on the substrate, and the fifth conductive portion 500 is connected to the first conductive portion 100 through a via. The second source / drain metal layer SD2 may include a seventh conductive portion 700. The orthographic projection of the seventh conductive portion 700 on the substrate at least partially overlaps with the orthographic projection of the fifth conductive portion 500 on the substrate, and the seventh conductive portion 700 is connected to the third conductive portion 300 through a via.

[0095] Among them, the first conductive layer Gate1, the second conductive layer Gate2, and the first source / drain metal layer SD1 can have Figure 19 All the features in, based on this, compared to Figure 19 The capacitor structure shown in this exemplary embodiment forms a fifth capacitor structure by adding a seventh conductive part 700 to the second source-drain metal layer SD2 and the fifth conductive part 500 to the first source-drain metal layer SD1. The seventh conductive part 700 is connected to the third conductive part 300 through a via, thereby the fifth capacitor structure, the first capacitor structure and the second capacitor structure are connected in parallel to form a first capacitor C1, which further increases the capacitance value of the first capacitor C1.

[0096] It is worth noting that, in this exemplary embodiment, an insulating layer is also provided between the first source / drain metal layer SD1 and the second source / drain metal layer SD2. The insulating layer may include a first planarization layer PLN1. The first planarization layer PLN1 has a relatively thick thickness. In order to reduce the insulation between the seventh conductive part 700 and the fifth conductive part 500, this exemplary embodiment may provide a first cutout on the first planarization layer PLN1. The first cutout is directly opposite the seventh conductive part 700 in the thickness direction of the substrate, so that the seventh conductive part 700 can be exposed through the first cutout, so that the seventh conductive part 700 can form a fifth capacitor structure with the fifth conductive part 500.

[0097] Similarly, the first conductive layer Gate1 may also include a second conductive portion, which forms the first electrode of the second capacitor C2; the second conductive layer Gate2 may also include a fourth conductive portion, the orthographic projection of the fourth conductive portion onto the substrate at least partially overlaps with the orthographic projection of the second conductive portion onto the substrate, and the fourth conductive portion forms the second electrode of the second capacitor C2; the first source / drain metal layer SD1 may include a sixth conductive portion, the orthographic projection of the sixth conductive portion onto the substrate at least partially overlaps with the orthographic projection of the fourth conductive portion onto the substrate, and the sixth conductive portion is connected to the second conductive portion through a via; the second source / drain metal layer SD2 may include an eighth conductive portion, the orthographic projection of the eighth conductive portion onto the substrate at least partially overlaps with the orthographic projection of the sixth conductive portion onto the substrate, and the eighth conductive portion is connected to the fourth conductive portion through a via. Thus, by adding an eighth conductive portion to the second source / drain metal layer SD2 and forming a sixth capacitor structure with the sixth conductive portion of the first source / drain metal layer SD1, and by connecting the eighth conductive portion to the fourth conductive portion through a via, the sixth capacitor structure, the third capacitor structure, and the fourth capacitor structure are connected in parallel to form the second capacitor C2, further increasing the capacitance value of the second capacitor C2. Similarly, a second cutout is provided on the first planarization layer PLN1. The second cutout is directly opposite the eighth conductive part in the thickness direction of the substrate, so that the eighth conductive part can be exposed through the second cutout, so that the eighth conductive part can form a sixth capacitor structure with the sixth conductive part.

[0098] Continue to refer to Figure 20 In an exemplary embodiment, the display panel may further include a first planarization layer PLN1 located between the first source-drain metal layer SD1 and the second source-drain metal layer SD2. The thickness of the first planarization layer PLN1 may be inversely proportional to the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2. Specifically, when the capacitance value of the first capacitor C1 is small, the first capacitor C1 has a smaller effect on maintaining the potential stability of the pull-up node PU. At this time, the pull-up node PU is more susceptible to noise interference from the output signal line G-out located above it. Therefore, the thickness of the first planarization layer PLN1 can be increased. By increasing the thickness of the first planarization layer PLN1, the insulation effect between the first source-drain metal layer SD1 and the second source-drain metal layer SD2 can be improved, thereby reducing the noise interference of the output signal line G-out on the pull-up node PU and the pull-down node PD in the crossed shift register unit GOA(n). When the capacitance of the first capacitor C1 is large, the first capacitor C1 has a strong voltage stabilizing effect on the pull-up node PU. At this time, the pull-up node PU is not easily affected by the noise interference of the output signal line G-out located above it. Therefore, the thickness of the first planarization layer PLN1 can be reduced accordingly.

[0099] Similarly, the thickness of the first planarization layer PLN1 has a similar relationship with the capacitance of the second capacitor C2.

[0100] It is worth noting that, in this exemplary embodiment, the thickness of the first planarization layer PLN1 may be non-uniform. For example, the thickness of the first planarization layer PLN1 at the position corresponding to the pull-up node PU can be set according to the capacitance value of the first capacitor C1, and the thickness of the first planarization layer PLN1 at the position corresponding to the pull-down node PD can be set according to the capacitance value of the second capacitor C2. This allows the first planarization layer PLN1 to improve the anti-interference capability of both the pull-up node PU and the pull-down node PD, thereby reducing the noise interference experienced by the pull-up node PU and the pull-down node PD.

[0101] In an exemplary embodiment, the thickness of the first planarization layer PLN1 is greater than or equal to 2000 nm, for example, it can be 2000 nm, 2500 nm, 3000 nm, etc. In this exemplary embodiment, the first planarization layer PLN1 can be prepared using organic materials. Compared with inorganic materials, organic materials have better toughness, which is beneficial for forming a thicker first planarization layer PLN1.

[0102] like Figure 20 As shown, in an exemplary embodiment, the display panel may further include an interlayer insulating layer (ILD) located between the second conductive layer Gate2 and the first source / drain metal layer SD1. The ratio of the thickness of the first planarization layer PLN1 to the thickness of the interlayer insulating layer ILD can be greater than or equal to 4, for example, 4, 5, 6, 7, etc. For example, the thickness of the interlayer insulating layer ILD can be 500 nm, and the thickness of the first planarization layer PLN1 can be greater than or equal to 2000 nm. This exemplary embodiment can determine the thickness of the first planarization layer PLN1 based on the above-mentioned ratio after determining the thickness of the interlayer insulating layer ILD, thereby increasing the thickness of the first planarization layer PLN1.

[0103] like Figure 20 As shown, in an exemplary embodiment, the display panel may further include a first passivation layer PVX1, which covers the first planarization layer PLN1 on the side facing away from the substrate. The thickness of the first passivation layer PVX1 is less than the thickness of the first planarization layer PLN1. For example, the first passivation layer PVX1 may be prepared using inorganic materials and may have a thickness of 150 nm. By adding the first passivation layer PVX1, the thickness of the insulating layer between the first source / drain metal layer SD1 and the second source / drain metal layer SD2 can be further increased, thereby further reducing the noise interference of the output signal line G-out to the pull-up node PU and pull-down node PD in the crossed shift register unit GOA(n).

[0104] Furthermore, it is worth noting that in some embodiments, there are other noise-prone points in the shift register unit, i.e., other nodes that are easily affected by noise. For example, Figure 21 This is a circuit diagram of a portion of the structure in a shift register unit in related technologies. Figure 22 To Figure 21 The circuit diagram of the improved circuit shown is as follows: Figure 21 As shown, when the signal terminal STU outputs a low-level signal, the transistor Tm is turned off, and node N0 is floating, making it susceptible to noise interference from coupling capacitors and other sources. To address this issue, as... Figure 22 As shown, this exemplary embodiment can add a capacitor C0 at node N0 to maintain the potential stability of node N0, thereby improving the noise immunity of noisy points in the shift register unit. It should be understood that the capacitance of capacitor C0 can be increased by increasing the overlapping area, or it can be... Figure 19 or Figure 20 The structure shown is used to increase the capacitance value of capacitor C0, which will not be described in detail here.

[0105] The output signal line G-out connected to the gate drive circuit GOA located away from the display area in this disclosure has a wiring structure that crosses the gate drive circuit GOA located near the display area. This structure is applicable to various different gate drive circuit GOA layout structures. Further explanation follows with reference to the accompanying drawings.

[0106] like Figure 1 As shown, multiple gate drive circuits (GOAs) can be located on the same side of the display area. In this structure, the gate drive circuit (GOA) is driven on one side only, meaning that each gate drive circuit (GOA) provides gate drive signals to the pixel circuit of the display area from the same side of the display area.

[0107] Figure 23 This is a schematic diagram of the layout structure of a gate driving circuit according to another embodiment of the present disclosure. In the figure, GOA1 represents the first gate driving circuit, GOA2 represents the second gate driving circuit, and so on. Figure 23As shown, in an exemplary embodiment, at least a portion of the gate drive circuit GOA includes a first component Part1 and a second component Part2 disposed opposite to each other on both sides of the display area. The shift register unit GOA(n) in the first component Part1 is connected to a portion of the sub-pixels of the display area through a first output signal line G-out1 connected thereto. The shift register unit GOA(n) in the second component Part2 is connected to another portion of the sub-pixels in the display area through a second output signal line G-out2 connected thereto. The orthographic projection of any first output signal line G-out1 onto the substrate and the orthographic projection of the pull-up node PU and pull-down node PD in the shift register unit GOA(n) located between the first component Part1 and the display area onto the substrate are both separate. The orthographic projection of any second output signal line G-out2 onto the substrate and the orthographic projection of the pull-up node PU and pull-down node PD in the shift register unit GOA(n) located between the second component Part2 and the display area onto the substrate are both separate.

[0108] In this exemplary embodiment, the gate driving circuit GOA includes a first component Part 1 and a second component Part 2 disposed opposite to each other on both sides of the display area. The first component Part 1 drives a portion of sub-pixels from one side of the display area, and the second component Part 2 drives a portion of sub-pixels from the other side of the display area. Thus, the gate driving circuit GOA provides gate control signals from both sides of the display area for bilateral driving. As described above, the display area includes pixel circuits connected to each sub-pixel in a one-to-one correspondence. The output line connecting the portion of the sub-pixels in the display area as described in this disclosure can be understood as the output line connecting to the pixel circuit corresponding to this portion of the sub-pixels, thereby driving the corresponding sub-pixels through the pixel circuit.

[0109] For example, such as Figure 23 As shown, the multiple gate driving circuits include a second gate driving circuit GOA2, which includes a first component GOA2-1 and a second component GOA2-2 disposed on both sides of the display area.

[0110] It is worth noting that, in this exemplary embodiment, it can be as follows: Figure 23 As shown, all gate drive circuits (GOAs) are bilaterally driven, meaning that all gate drive circuits (GOAs) include a first component (Part1) and a second component (Part2) disposed opposite each other on both sides of the display area. Alternatively, some gate drive circuits (GOAs) may be bilaterally driven, while others may be single-sided driven.

[0111] In this structure, the orthographic projection of the first output signal line G-out1 on the substrate passes over the sub-region located between the first component Part1 and the display area, that is, it crosses the sub-region located between the first component Part1 and the display area. In other words, the first output signal line G-out1 crosses the shift register unit GOA(n) between the first component Part1 and the display area. Furthermore, the first output line also needs to be separated from the orthographic projection of the pull-up node PU and pull-down node PD in the crossed shift register unit GOA(n) on the substrate. That is, the first output signal line G-out1 avoids the pull-up node PU and pull-down node PD in the shift register unit GOA(n) corresponding to the crossed sub-region, so as to reduce the noise impact on the pull-up node PU and pull-down node PD in the crossed shift register unit GOA(n). Similarly, the orthographic projection of the second output signal line G-out2 on the substrate passes over the sub-region located between the second component Part 2 and the display area, that is, the second output signal line G-out2 crosses the sub-region between the second component Part 2 and the display area. More specifically, the second output signal line G-out2 crosses the shift register unit GOA(n) between the second component Part 2 and the display area. Furthermore, the second output signal line G-out2 also needs to be separated from the orthographic projection of the pull-up node PU and pull-down node PD in the crossed shift register unit GOA(n) on the substrate, that is, the second output signal line G-out2 avoids the pull-up node PU and pull-down node PD in the crossed shift register unit GOA(n) to reduce the noise impact on the pull-up node PU and pull-down node PD in the crossed shift register unit GOA(n).

[0112] Figure 24 This is a schematic diagram of the layout structure of a gate driving circuit according to another embodiment of the present disclosure. In the figure, GOA1 represents the first gate driving circuit, GOA2 represents the second gate driving circuit, and so on. Figure 24As shown, in an exemplary embodiment, multiple gate drive circuits (GOAs) include a first drive group Drv1 and a second drive group Drv2 disposed on both sides of the display area; wherein, in each output signal line G-out of the same drive group, the orthographic projection of the output signal line G-out connected to the shift register unit GOA(n) away from the display area onto the substrate is separate from the orthographic projection of the pull-up node PU and pull-down node PD in the shift register unit GOA(n) near the display area onto the substrate. The display panel typically includes multiple gate drive circuits (GOAs), with different gate drive circuits (GOAs) outputting gate drive signals with different functions. The multiple gate drive circuits (GOAs) include a first drive group Drv1 and a second drive group Drv2 disposed on both sides of the display area, meaning that some gate drive circuits (GOAs) of the display panel are located on one side of the display area, and other gate drive circuits (GOAs) are located on the other side of the display area. Furthermore, each gate drive circuit (GOA) is single-sided driven, meaning that each level of the shift register unit (GOA(n)) in each gate drive circuit (GOA) provides gate drive signals to the display area from the same side of the display area. Figure 24 As shown, the display panel may include a first gate driving circuit GOA1 to a fourth gate driving circuit GOA4. The first gate driving circuit GOA1 and the second gate driving circuit GOA2 are located on the same side of the display area, forming a first driving group Drv1. The third gate driving circuit GOA3 and the fourth gate driving circuit GOA4 are located on the other side of the display area, forming a second driving group Drv2.

[0113] In each output signal line G-out in the same drive group, the output signal line G-out connected to the shift register unit GOA(n) far from the display area crosses over the shift register unit GOA(n) close to the display area. Furthermore, the orthographic projection of the output signal line G-out connected to the shift register unit GOA(n) far from the display area onto the substrate is separate from the orthographic projection of the pull-up node PU and pull-down node PD in the shift register unit GOA(n) close to the display area onto the substrate. That is, the orthographic projection of the output signal line G-out connected to the shift register unit GOA(n) far from the display area onto the substrate is separate from the orthographic projection of the pull-up node PU and pull-down node PD in the shift register unit GOA(n) that is crossed, so as to avoid the pull-up node PU and pull-down node PU in the shift register unit GOA(n) that is crossed, and reduce the noise interference to the pull-up node PU and pull-down node PD in the shift register unit GOA(n) that is crossed.

[0114] Figure 25 This is a schematic diagram of the layout structure of a gate driving circuit according to another embodiment of the present disclosure. In the figure, GOA1 represents the first gate driving circuit, GOA2 represents the second gate driving circuit, and so on. Figure 25As shown, in an exemplary embodiment, the plurality of gate driving circuits GOA include at least one first structure gate driving circuit ARC1. Each shift register unit GOA(n) in the first structure gate driving circuit ARC1 is connected to a plurality of output signal lines G-out. The orthographic projection of any output signal line G-out connected to the first structure gate driving circuit ARC1 onto the substrate and the orthographic projection of the pull-up node PU and pull-down node PD in the shift register unit GOA(n) located between the first structure gate driving circuit ARC1 and the display area onto the substrate are both separated.

[0115] In this exemplary embodiment, each shift register unit GOA(n) in the first structure gate driving circuit ARC1 is connected to multiple output signal lines G-out. That is, one shift register unit GOA(n) in the first structure gate driving circuit ARC1 drives multiple pixel rows, meaning that multiple pixel rows share one shift register unit GOA(n). The term "multiple" here refers to two or more units.

[0116] For example, the first-level shift register unit GOA(n) in the first-structure gate drive circuit ARC1 outputs two rows of gate drive signals, that is, the first-level shift register unit GOA(n) drives a row of sub-pixels.

[0117] In this structure, the orthographic projection of the output signal line G-out connected to the first structure gate driving circuit ARC1 across the shift register unit GOA(n) located between the first structure gate driving circuit ARC1 and the display area. Furthermore, the orthographic projection of the output signal line G-out connected to the first structure gate driving circuit ARC1 across the substrate is separate from the orthographic projections of the pull-up node PU and pull-down node PD in the shift register unit GOA(n) located between the first structure gate driving circuit ARC1 and the display area. That is, the output signal line G-out connected to the first structure gate driving circuit ARC1 avoids the pull-up node PU and pull-down node PD in any shift register unit GOA(n) located between the first structure gate driving circuit ARC1 and the display area, so as to reduce noise interference to the pull-up node PU and pull-down node PD in the shift register unit GOA(n) located between the first structure gate driving circuit ARC1 and the display area.

[0118] Furthermore, it should be understood that in this exemplary embodiment, all gate driving circuits GOA may be first-structure gate driving circuits ARC1, that is, all gate driving circuits GOA may be single-level shift register units GOA(n) driving multiple pixel rows. Alternatively, some gate driving circuits GOA may be first-structure gate driving circuits ARC1, such as... Figure 25As shown, in the first gate driving circuit GOA1 to the fourth gate driving circuit GOA4, the third gate driving circuit GOA3 and the fourth gate driving circuit GOA4 are first-structure gate driving circuits ARC1, while the first gate driving circuit GOA1 and the second gate driving circuit GOA2 are conventional structures. This disclosure does not impose any special limitation on the number of first-structure gate driving circuits ARC1.

[0119] Figure 26 This is a schematic diagram of the layout structure of a gate driving circuit according to another embodiment of the present disclosure. In the figure, GOA1 represents the first gate driving circuit, GOA2 represents the second gate driving circuit, and so on. Figure 26 As shown, in an exemplary embodiment, the plurality of gate driving circuits GOA include at least one second structure gate driving circuit ARC2. Each stage of shift register unit GOA(n) in the second structure gate driving circuit ARC2 includes a first sub-shift register unit GOA(n1) and a second sub-shift register unit GOA(n2) disposed opposite to each other on both sides of the display area. The first sub-shift register unit GOA(n1) and the second sub-shift register unit GOA(n2) respectively provide gate driving signals to the same row of sub-pixels through corresponding output signal lines G-out. The orthographic projection of any output signal line G-out connected to the second structure gate driving circuit ARC2 onto the substrate and the orthographic projection of the pull-up node PU and the pull-down node PD in the shift register unit GOA(n) located between the second structure gate driving circuit ARC2 and the display area onto the substrate are both separated.

[0120] In this exemplary embodiment, each stage of the shift register unit GOA(n) in the second structure gate drive circuit ARC2 includes a first sub-shift register unit GOA(n1) and a second sub-shift register unit GOA(n2) disposed opposite to each other on both sides of the display area. The first sub-shift register unit GOA(n1) and the second sub-shift register unit GOA(n2) respectively provide gate drive signals to the same row of sub-pixels through the corresponding output signal line G-out. That is, each stage of the shift register unit GOA(n) in the second structure gate drive circuit ARC2 includes two parts, and the two parts are located on both sides of the display area. Furthermore, each stage of the shift register unit GOA(n) in the second structure gate drive circuit ARC2 provides the same gate drive signal to the same row of sub-pixels on both sides of the display area. For example, the transistor in the pixel circuit of the display area is a dual-gate structure. The second structure gate drive circuit ARC2 is used to provide a gate drive signal to the dual-gate structure transistor. The first sub-shift register unit GOA(n1) provides a gate drive signal to one gate of the transistor from one side of the display area, and the second sub-shift register unit GOA(n2) provides a gate drive signal to the other gate of the transistor from the other side of the display area.

[0121] In addition, this disclosure also provides a display device, which may include the display panel described in any of the above embodiments.

[0122] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A display panel, characterized by, It includes a display area and a non-display area surrounding the display area. The non-display area includes multiple gate driving circuits. Each gate driving circuit includes multiple cascaded shift register units. The shift register units in each gate driving circuit that provide gate driving signals for the same row of sub-pixels are located in the same row. The display panel also includes: The substrate has the display area and the non-display area. The non-display area includes multiple sub-regions arranged in a row and column direction. Each sub-region in the same column corresponds to a shift register unit of each level in the same gate driving circuit, and each sub-region in the same row corresponds to the same level shift register unit of each gate driving circuit. A second source / drain metal layer is located on one side of the substrate, and the second source / drain metal layer includes: Multiple output signal lines extend along the row direction of the orthogonal projection of the substrate, and the output signal lines are arranged corresponding to each of the shift register units; Among the multiple output signal lines located in the same pixel row, the output signal line connected to the shift register unit far from the display area is projected onto the substrate through the sub-region corresponding to the shift register unit near the display area, and the output signal lines in the same pixel row are separated from each other. The shift register unit includes a pull-up node and a pull-down node. The pull-up node is used to control the output transistor connected to it to output a conducting level, and the pull-down node is used to control the output transistor connected to it to output a non-conducting level. In this case, the output signal line connected to the shift register unit far from the display area is projected onto the substrate in a positive projection, while the pull-up node and the pull-down node in the shift register unit near the display area are projected onto the substrate in a positive projection. The display panel also includes: A first conductive layer is located on the side of the substrate facing the second source / drain metal layer, and the first conductive layer includes: A first connecting line extends along the row direction in the orthographic projection of the substrate, and the first connecting line is used to form the pull-up node; The second connecting line extends along the row direction in the orthographic projection of the substrate, and the second connecting line is used to form the pull-down node; The shift register unit further includes a first transistor and a second transistor. The gate of the first transistor is connected to the pull-up node, the first terminal receives a first signal, and the second terminal is connected to the output terminal. The gate of the second transistor is connected to the pull-down node. The display panel further includes: An active layer, located on the side of the substrate facing the second source / drain metal layer, comprises: Multiple first active structures extend along the column direction and are spaced apart in the row direction in the orthographic projection of the substrate. Each first active structure includes at least a first active portion and a second active portion and a third active portion connected to both sides of the first active portion in the column direction. The first active portion is used to form the channel region of the first transistor, and the second active portion and the third active portion are used to form the first electrode and the second electrode of the first transistor. Multiple second active structures extend along the column direction and are spaced apart in the row direction in the orthographic projection of the substrate. Each second active structure includes at least a fourth active portion and a fifth active portion and a sixth active portion connected to both sides of the fourth active portion in the column direction. The fourth active portion is used to form the channel region of the second transistor, and the fifth active portion and the sixth active portion are used to form the first electrode and the second electrode of the second transistor. The first conductive layer further includes: A first gate line extends along the row direction in the orthographic projection of the first active portion onto the orthographic projection of the first active portion onto the substrate. A portion of the structure of the first gate line is used to form the gate of the first transistor, and the first gate line is connected to the first connection line. The second gate line extends along the row direction in the orthographic projection of the fourth active portion onto the orthographic projection of the fourth active portion onto the substrate. A portion of the structure of the second gate line is used to form the gate of the second transistor, and the second gate line is connected to the second connection line.

2. The display panel according to claim 1, characterized in that, The first and second connecting lines in any Nth row of the gate driving circuit near the display area are projected onto the substrate between the Nth and N+1th row output signal lines in the gate driving circuit away from the display area, where N is a natural number.

3. The display panel according to claim 1, characterized in that, Each of the gate driving circuits is located on the same side of the display area.

4. The display panel according to claim 1, characterized in that, At least part of the gate driving circuit includes a first component and a second component disposed opposite to each other on both sides of the display area. The shift register unit in the first component is connected to a portion of the sub-pixels of the display area through a first output signal line connected thereto. The shift register unit in the second component is connected to another portion of the sub-pixels of the display area through a second output signal line connected thereto. Wherein, the projection of any first output signal line onto the substrate and the projection of the pull-up and pull-down nodes in the shift register unit located between the first component and the display area onto the substrate are both separate, and the projection of any second output signal line onto the substrate and the projection of the pull-up and pull-down nodes in the shift register unit located between the second component and the display area onto the substrate are both separate.

5. The display panel according to claim 1, characterized in that, Multiple gate driving circuits include a first driving group and a second driving group disposed on both sides of the display area; Among the output signal lines in the same drive group, the orthographic projection of the output signal line connected to the shift register unit far from the display area on the substrate is separate from the orthographic projection of the pull-up node and the pull-down node in the shift register unit near the display area on the substrate.

6. The display panel according to claim 1, characterized in that, The plurality of gate driving circuits include at least one first structure gate driving circuit, wherein each stage shift register unit in the first structure gate driving circuit is connected to multiple output signal lines. In this case, the projection of any output signal line connected to the first structure gate driving circuit onto the substrate and the projection of the pull-up and pull-down nodes in the shift register unit located between the first structure gate driving circuit and the display area onto the substrate are both separated.

7. The display panel according to claim 1, characterized in that, The plurality of gate driving circuits include at least one second structure gate driving circuit. Each shift register unit in the second structure gate driving circuit includes a first sub-shift register unit and a second sub-shift register unit disposed opposite to each other on both sides of the display area. The first sub-shift register unit and the second sub-shift register unit respectively provide gate driving signals to the same row of sub-pixels through the corresponding output signal lines. In this case, the projection of any output signal line connected to the second structure gate driving circuit onto the substrate and the pull-up and pull-down nodes in the shift register unit located between the second structure gate driving circuit and the display area onto the substrate are both separated.

8. The display panel according to claim 1, characterized in that, A first active structure includes a first structural portion, a second structural portion, and a third structural portion connected sequentially in a column direction. The first structural portion and the third structural portion each include two first active portions and one third active portion. The second structural portion includes one second active portion. The first conductive layer includes four first gate lines, and the first connecting lines are respectively connected to each of the first gate lines. The display panel also includes: A first source / drain metal layer is located on the side of the first conductive layer facing the second source / drain metal layer, and the first source / drain metal layer includes: A first transmission line extends along the row direction on the orthographic projection of the substrate and is located on the orthographic projection of the second active portion on the substrate. The first transmission line is connected to each of the second active portions through vias to output a first signal to the first transistor. The second transmission line is used to form the output terminal. The second transmission line extends along the row direction on the orthographic projection of the substrate and is located on the orthographic projection of the third active part on the substrate. The second transmission line is connected to the corresponding third active part and the output signal line through vias to connect the second electrode of the first transistor to the output terminal.

9. The display panel according to claim 8, characterized in that, The first terminal of the second transistor receives the second signal, and the second terminal is connected to the output terminal; a second active structure includes a fourth structure, a fifth structure, and a sixth structure connected sequentially in the column direction, the fourth structure and the sixth structure each include two fourth active parts and one sixth active part, and the fifth structure includes one fifth active part; the first conductive layer includes four second gate lines, and the second connecting lines are respectively connected to each of the second gate lines; The first source / drain metal layer further includes: The third transmission line extends along the row direction on the orthographic projection of the substrate and is located on the orthographic projection of the fifth active part on the substrate. The third transmission line connects each of the fifth active parts through vias to output a second signal to the second transistor. The fourth transmission line extends along the row direction on the orthographic projection of the substrate and is located on the orthographic projection of the sixth active part on the substrate. The fourth transmission line is connected to the corresponding sixth active part and the output signal line through vias, so as to connect the second electrode of the second transistor to the output terminal.

10. The display panel according to claim 2, characterized in that, The shift register unit further includes a first capacitor and a second capacitor. The first terminal of the first capacitor is connected to the pull-up node, and the second terminal is connected to the output terminal. The first terminal of the second capacitor is connected to the pull-down node, and the second terminal is connected to the output terminal. The capacitance values ​​of the first capacitor and the second capacitor are both greater than or equal to 2pF.

11. The display panel according to claim 10, characterized in that, The second connecting line is located on the side of the first connecting line closer to the display area; The first conductive layer further includes: A first conductive portion is connected to the side of the first connecting line near the display area in the horizontal direction, and the first conductive portion is used to form the first electrode of the first capacitor. The second conductive part is connected to the side of the second connecting line near the display area in the horizontal direction, and the second conductive part is used to form the first pole of the second capacitor; The display panel also includes: A second conductive layer is located between the first conductive layer and the second source / drain metal layer, the second conductive layer comprising: The third conductive portion overlaps at least partially with the orthographic projection of the first conductive portion on the substrate, and the third conductive portion is used to form the second electrode of the first capacitor. The fourth conductive portion, whose orthogonal projection on the substrate at least partially overlaps with the orthogonal projection of the second conductive portion on the substrate, is used to form the second electrode of the second capacitor. A first source / drain metal layer is located on the side of the second conductive layer facing the second source / drain metal layer, and the first source / drain metal layer includes: The fifth conductive part overlaps at least with the second conductive part's orthographic projection on the substrate, and the fifth conductive part is connected to the first conductive part through a via. The sixth conductive part overlaps at least with the fourth conductive part in the same way as ...

12. The display panel according to claim 2, characterized in that, The display panel further includes a second conductive layer, a first source / drain metal layer, and a first planarization layer, which are sequentially stacked on the first conductive layer toward the side of the second source / drain metal layer. The thickness of the first planarization layer is greater than or equal to 2000 nm.

13. The display panel according to claim 12, characterized in that, The display panel also includes: An interlayer insulating layer is located between the second conductive layer and the first source / drain metal layer; Wherein, the ratio of the thickness of the first planarization layer to the thickness of the interlayer insulation layer is greater than or equal to 4.

14. The display panel according to claim 12, characterized in that, The display panel also includes: A first passivation layer is formed by covering the first planarization layer on the side of the first planarization layer opposite to the substrate, wherein the thickness of the first passivation layer is less than the thickness of the first planarization layer.

15. The display panel according to claim 12, characterized in that, The shift register unit further includes a first capacitor and a second capacitor. The first terminal of the first capacitor is connected to the pull-up node, and the second terminal is connected to the output terminal. The first terminal of the second capacitor is connected to the pull-down node, and the second terminal is connected to the output terminal. The second connecting line is located on the side of the first connecting line closer to the display area; The first conductive layer further includes: A first conductive portion is connected to the side of the first connecting line near the display area in the horizontal direction, and the first conductive portion is used to form the first electrode of the first capacitor. The second conductive part is connected to the side of the second connecting line near the display area in the horizontal direction, and the second conductive part is used to form the first pole of the second capacitor; The second conductive layer includes: The third conductive portion overlaps at least partially with the orthographic projection of the first conductive portion on the substrate, and the third conductive portion is used to form the second electrode of the first capacitor. The fourth conductive portion, whose orthogonal projection on the substrate at least partially overlaps with the orthogonal projection of the second conductive portion on the substrate, is used to form the second electrode of the second capacitor. The first source / drain metal layer includes: The fifth conductive part overlaps at least with the second conductive part's orthographic projection on the substrate, and the fifth conductive part is connected to the first conductive part through a via. The sixth conductive part overlaps at least with the fourth conductive part in the orthographic projection on the substrate, and the sixth conductive part is connected to the second conductive part through a hole. The second source / drain metal layer further includes: The seventh conductive part has its orthographic projection on the substrate at least partially overlapping with the orthographic projection of the fifth conductive part on the substrate, and the seventh conductive part is connected to the third conductive part through a via. The eighth conductive part has its orthographic projection on the substrate at least partially overlapping with the orthographic projection of the sixth conductive part on the substrate, and the eighth conductive part is connected to the fourth conductive part through a via. The first planarization layer has a first cutout facing the seventh conductive portion and a second cutout facing the eighth conductive portion, wherein the first cutout exposes the seventh conductive portion and the second cutout exposes the eighth conductive portion.

16. A display device, characterized in that, Includes the display panel as described in any one of claims 1-15.

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