A two-stage protection time power device short circuit protection circuit
By designing a power device short-circuit protection circuit with two-stage protection time and using a reset signal to control the level state, the problem of the non-adjustable short-circuit protection time of power devices in the prior art is solved, improving the circuit compatibility and the safety of power devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING UNIV
- Filing Date
- 2021-11-17
- Publication Date
- 2026-06-26
Smart Images

Figure CN116137434B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power electronics technology, and specifically relates to a power device short-circuit protection circuit with two-stage protection time. Background Technology
[0002] Power devices are widely used in various types of power converters, resulting in a rich array of power conversion products. From home appliances to electric vehicle drives, industrial motion control, and electrical energy conversion, power devices are extensively used to construct high-efficiency power conversion systems. Power devices, typically represented by MOSFETs (Metal Oxide Silicon Field Effect Transistors) and IGBTs (Insulated-Gate Bipolar Transistors), are widely applied in all sectors of society, forming a rich industrial cluster.
[0003] Power devices have become core components of power conversion systems, and their stable and reliable operation is the foundation of the entire system's safety. Failure of power devices can have extremely serious consequences, ranging from system malfunction and shutdown to more serious safety accidents such as explosions, fires, and electric shocks. Therefore, safely driving power devices and providing adequate protection is crucial. Short-circuit faults are the most severe type of fault in power devices because, under short-circuit conditions, the device withstands a large amount of power. Within a very short time, this power is converted into heat, causing the device temperature to rapidly exceed the maximum permissible junction temperature, ultimately leading to chip melting and failure.
[0004] The safety of power devices is evaluated based on their Safe Operating Area (SOA). Under no circumstances should the voltage, current, or withstand time of a power device exceed the SOA. During a short-circuit fault, power devices withstand very high voltage and current, resulting in an extremely short withstand time. For specific applications, device datasheets will specifically specify short-circuit withstand time indicators, typically 5 or 10 microseconds. This necessitates controlling the short-circuit duration during the design of the power device's drive and protection circuits to ensure its safety. Generally, the short-circuit protection time for direct hardware protection is determined by the circuit component parameters. In applications, adjustments need to be made for different power devices to obtain different short-circuit protection times. Summary of the Invention
[0005] To address the problems mentioned in the background section, this invention proposes a two-stage short-circuit protection circuit for power devices. This circuit achieves the selection of two short-circuit protection times by controlling the level of the reset signal during normal operation, thereby enhancing the adaptability of the drive protection circuit to the different short-circuit withstand times of various power devices. To achieve this objective, the invention employs the following technical solution:
[0006] A two-stage protection time short-circuit protection circuit for power devices, characterized by comprising a driving section, a short-circuit locking section, a reset section, and a fault signal output section. The driving section includes a gate driver U1, a gate driver power supply capacitor C1, a gate resistor R1, a driving signal input resistor R2, and a power device Q1. The short-circuit locking section includes a locking circuit composed of R4, T1, D3, R5, R7, T2, R9, and C3, a short-circuit detection diode D1, a Zener diode D4, a bias resistor R3, and a bias diode D2. The reset section includes a reset signal input resistor R8, a reset transistor T3, a reset charging resistor R6, and a reset capacitor C2. The fault signal output section includes an output diode D5.
[0007] When the reset signal RST is low, the first-stage short-circuit protection time is selected; when the reset signal RST is high, the second-stage short-circuit protection time is selected. The first-stage short-circuit protection time is determined by R3, D4, and C3, while the second-stage short-circuit protection time is determined by R3, D4, C3, and C2. The second-stage short-circuit protection time is longer than the first-stage short-circuit protection time. This allows for two different short-circuit protection times by adjusting the values of these components. After a short circuit occurs, the short-circuit lockout circuit activates, driving pin 4 of the gate driver U1 to a high level, causing pin 5 to output a low level and shut down Q1. The short-circuit indicator D3 illuminates, and the fault signal SAT outputs a low level. To reset from the short-circuit protection state, RST must first be set low. The reset charging resistor R6 charges the reset capacitor C2, and once the voltage reaches VDD, RST is set high. At this time, T2 is turned off, the short-circuit lockout circuit is unlocked, and the reset process is completed.
[0008] The beneficial effects of adopting the above technical solution are as follows:
[0009] By controlling the RST signal level during normal operation via software, the short-circuit protection time can be controlled, thereby enabling selection of two-stage short-circuit protection time.
[0010] The two-stage protection time scheme can support changes in different MOSFET or IGBT parameters, improving the compatibility of the drive protection circuit.
[0011] Configure appropriate short-circuit protection time according to different load power to ensure the safe and reliable operation of power devices. Attached Figure Description
[0012] Figure 1 This is the circuit diagram of the present invention;
[0013] Explanation of reference numerals in the attached diagram: Gate driver U1, gate driver power supply capacitor C1, gate resistor R1, drive signal input resistor R2, power device Q1, short circuit lockout circuit consisting of resistor R4, PNP transistor T1, LED D3, resistor R5, resistor R7, NPN transistor T2, resistor R9, capacitor C3, short circuit detection diode D1, Zener diode D4, bias resistor R3, bias diode D forming the short circuit lockout circuit, reset signal input resistor R8, reset transistor T3, reset charging resistor R6, reset capacitor C2 forming the reset circuit, diode D5 outputs the fault signal. Detailed Implementation
[0014] The following will be combined with the appendix Figure 1 The technical solution of the present invention will be described in detail below.
[0015] A two-stage protection time short-circuit protection circuit for power devices, characterized by comprising a driving section, a short-circuit locking section, a reset section, and a fault signal output section. The driving section includes a gate driver U1, a gate driver power supply capacitor C1, a gate resistor R1, a driving signal input resistor R2, and a power device Q1. The short-circuit locking section includes a locking circuit composed of R4, T1, D3, R5, R7, T2, R9, and C3, a short-circuit detection diode D1, a Zener diode D4, a bias resistor R3, and a bias diode D2. The reset section includes a reset signal input resistor R8, a reset transistor T3, a reset charging resistor R6, and a reset capacitor C2. The fault signal output section includes an output diode D5.
[0016] The gate driver U1 in the driving section has two input terminals: non-inverting (3) and inverting (4). Non-inverting (3) is used for the drive signal input, and inverting (4) is used for the enable signal input. When the enable signal is low, the drive output 5 is controlled by the drive signal input 3. When the enable signal is high, the drive output 5 always outputs a low level regardless of the state of the drive signal input 3. The gate drive power supply capacitor C1 provides power to the power device Q1, and the gate resistor R1 controls the switching speed of the power device Q1.
[0017] The short-circuit lockout circuit forms a thyristor structure using PNP transistor T1, NPN transistor T2, resistors R4, R5, R7, R9, and capacitor C3. The trigger signal is input from the base of T2. When a short circuit occurs while power device Q1 is turned on, the drain voltage of Q1 rises due to the short circuit, and the anode voltage of the short-circuit detection diode D1 also rises. When Zener diode D4 breaks down, the short-circuit trigger signal is output from U1 and charges capacitor C3 through R3 and D4. When the voltage rises to the base voltage threshold of T2, T2 turns on, and current flows to the base of T1. This current then feeds back to the base of T2 through the collector of T1, forming a positive feedback loop that locks the circuit in place. The inverting input 4 of driver U1 goes high, and output 5 goes low, turning off power device Q1. The short-circuit indicator D3 lights up, and the short-circuit signal SAT goes low.
[0018] When the reset signal RST is low, the first-level short-circuit protection time is selected, and the time is determined by R3, D4, and C3; when the reset signal RST is high, the second-level short-circuit protection time is selected, and the time is determined by R3, D4, C3, and C2; the second-level short-circuit protection time is longer than the first-level short-circuit protection time. In this way, two different short-circuit protection times are obtained by adjusting the values of these components.
[0019] Resetting from short-circuit protection requires first setting RST to low. The reset charging resistor R6 charges the reset capacitor C2, and once the voltage reaches VDD, RST is set to high. At this point, T2 is turned off, and the short-circuit lockout circuit is unlocked, thus completing the reset process. D2 is used to disable the short-circuit protection function when power devices are turned off.
[0020] In summary, this invention achieves a two-stage short-circuit protection circuit with integrated high and low level control in the reset signal. Clearly, more stages of short-circuit protection time control can be achieved by replicating multiple reset circuits composed of C2, R6, R8, and T3. This invention enables adjustment of the short-circuit protection parameters of power devices, facilitating more precise provision of different levels of short-circuit protection for different power devices, and providing an effective solution for ensuring the safe and reliable operation of power devices.
Claims
1. A power device short-circuit protection circuit with two-stage protection time, characterized in that: It includes a driving section, a short-circuit locking section, a reset section, and a fault signal output section; the driving section includes a gate driver U1, a gate driver power supply capacitor C1, a gate resistor R1, a drive signal input resistor R2, and a power device Q1; The gate driver U1 has its 5th pin connected to the input terminal of the gate resistor R1, and the output terminal of the gate resistor R1 is connected to the gate of the power device Q1; the drive signal input resistor R2 is connected to the 3rd pin of the gate driver U1. The short-circuit locking section includes a locking circuit consisting of a fourth resistor R4, a PNP transistor T1, a light-emitting diode D3, a fifth resistor R5, a seventh resistor R7, an NPN transistor T2, a ninth resistor R9, and a capacitor C3. The emitter of the PNP transistor T1 is connected to the power supply VDD, the collector of the PNP transistor T1 is connected to the input terminal of the fifth resistor R5, the output terminal of the fifth resistor R5 is connected to the input terminal of the ninth resistor R9, and the output terminal of the ninth resistor R9 is grounded. The output terminal of the fifth resistor R5 is connected to the base of NPN transistor T2, and the emitter of NPN transistor T2 is grounded. The output terminal of the fourth resistor R4 is connected to the anode of the light-emitting diode D3, and the cathode of the light-emitting diode D3 is connected to the collector of the NPN transistor T2 through the seventh resistor R7. The emitter of the NPN transistor T2 is grounded. The base of the PNP transistor T1 is connected between the fourth resistor R4 and the light-emitting diode D3; The reset section includes a reset signal input resistor R8, a reset transistor T3, a reset charging resistor R6, and a reset capacitor C2. The output terminal of the gate driver U1 is connected to the reset charging resistor R6, the reset capacitor C2, and the capacitor C3 in sequence and then grounded. The input terminal of the reset signal input resistor R8 is connected to the reset signal RST, and the output terminal of the reset signal input resistor R8 is connected to the base of the reset transistor T3. The collector of the reset transistor T3 is connected between the reset charging resistor R6 and the reset capacitor C2. The fault signal output section includes an output diode D5, a short-circuit detection diode D1, a Zener diode D4, a bias resistor R3, and a bias diode D2. The anode of the output diode D5 is connected to the fault signal SAT, and the cathode of the output diode D5 is connected between the seventh resistor R7 and the NPN transistor T2. The base of the NPN transistor T2 is connected to the anode of the Zener diode D4, the cathode of the Zener diode D4 is connected to the anode of the bias diode D2, and the cathode of the bias diode D2 is connected between pin 5 of the gate driver U1 and the gate resistor R1. The anode of the short-circuit detection diode D1 is connected to the cathode of the Zener diode D4, and the cathode of the short-circuit detection diode D1 is connected to the drain of the power device Q1; the source of the power device Q1 is grounded. When the reset signal RST is low, the first-level short-circuit protection time is selected; when the reset signal RST is high, the second-level short-circuit protection time is selected. The first-level short-circuit protection time is determined by the bias resistor R3, Zener diode D4, and capacitor C3, while the second-level short-circuit protection time is determined by the bias resistor R3, Zener diode D4, capacitor C3, and reset capacitor C2.
2. The power device short-circuit protection circuit with two-stage protection time according to claim 1, characterized in that: After a short circuit occurs, the short circuit lockout circuit activates, and pin 4 of the gate driver U1 is driven to a high level, causing pin 5 to output a low level to turn off the power device Q1. The LED D3 lights up, and the fault signal SAT outputs a low level.
3. The power device short-circuit protection circuit with two-stage protection time according to claim 1, characterized in that: To reset from the short-circuit protection state, RST must first be set to low level. The reset charging resistor R6 charges the reset capacitor C2. Once the voltage reaches VDD, RST is set to high level. At this time, the NPN transistor T2 is turned off, and the short-circuit lockout circuit is unlocked, thus completing the reset process.
4. The power device short-circuit protection circuit with two-stage protection time according to claim 1, characterized in that: More levels of short-circuit protection time control can be achieved by replicating multiple reset circuits consisting of reset capacitor C2, reset charging resistor R6, reset signal input resistor R8, and reset transistor T3.