An FPGA-based front-end receiver for ultra-wideband logging radar

Abstract

The present invention belongs to the field of ultra-wideband radar, relates to the radar receiving front end, and specifically provides an ultra-wideband logging radar receiving front end based on FPGA, which includes three parts: an analog front-end circuit, a delay circuit, and an FPGA control circuit; the sampling method of the present invention combines the sequential equivalent sampling technology and the time-interleaving technology to sample signals with four channels, and performs bad point removal and averaging processing on the data; uses FPGA to generate synchronous timing signals, and further accurately delays the generation of signals by combining a coarse delay device and a fine delay device; realizes the information interaction between the upper computer and the FPGA through Ethernet, and sets the function of dynamically adjustable time window length. The present invention improves the integrity and accuracy of the sampled signals, shortens the sampling period, enables the receiving front end to collect more data within the same time, can be applied to various downhole environments and different detection distances, and is an ultra-wideband logging radar receiving front end with high accuracy and strong applicability.

Description

Technical Field

[0001] The present invention belongs to the field of ultra-wideband radar, relates to a radar receiving front end, and specifically provides an ultra-wideband well logging radar receiving front end based on FPGA. Background Art

[0002] Ultra-wideband radars typically use picosecond or nanosecond carrier-free Gaussian pulses and their derivatives as baseband signals. These continuous, extremely narrow pulses have high peak values and high repetition rates, enabling them to resist multipath interference and penetrate lossy media. Compared to other frequency-domain radars, ultra-wideband radars offer higher spatial resolution, making them widely used in well logging scenarios.

[0003] Ultra-wideband logging radars often operate with their transmit and receive antennas placed together. By continuously moving the radar at a constant speed underground, the receiver front end receives echo signals at identical time intervals, enabling detection of the downhole environment. Therefore, the receiver front end is the core component of the carrier-free ultra-wideband logging radar system, and its performance determines the radar's overall performance. Due to the high center frequency of the ultra-wideband logging radar antenna (1 GHz, for example), the Nyquist sampling theorem dictates that the analog-to-digital converter (ADC) in the sampling circuit must operate at a frequency of at least 2 GHz. This places extremely high demands on the ADC's performance, and few ADC components currently meet these requirements. Current high-frequency ultra-wideband logging radars often use equivalent sampling to address this problem. This technique exploits the quasi-periodic nature of radar signals, sampling each echo signal once or multiple times. After several repetitions, the acquired sampling points are spliced and reconstructed to obtain a complete echo signal. However, due to clock drift in the delay time, the equivalent sampling process cannot ensure that the signal time intervals within each sampling cycle are consistent. As a result, the signal collected by the receiving front end has large errors and lacks accuracy. Furthermore, because electromagnetic waves propagate at different speeds in various downhole media, or even within the same medium but at different distances from the wellbore, the receiving front end receives the target echo signal at different times. This means that the useful range of the echo signal varies randomly depending on the downhole environment and the distance from the wellbore. Therefore, using a fixed sampling time window wastes sampling time and storage space, lacking flexibility. Summary of the Invention

[0004] The purpose of the present invention is to propose an FPGA-based ultra-wideband logging radar receiving front end. The FPGA and delay circuit are used to suppress clock drift, generate accurate delayed signals for equivalent sampling, and reduce echo signal errors. The FPGA is used to perform data screening and bad pixel removal to reduce sampling signal distortion caused by signal instability during signal transmission. The time window length is dynamically adjustable to cope with different downhole environments and detection distance requirements.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] A UWB logging radar receiving front end based on FPGA, comprising: an analog front-end circuit, a delay circuit and an FPGA control circuit; characterized in that:

[0007] The analog front-end circuit is composed of four groups of analog front-end sub-circuits. Each group of analog front-end sub-circuits has the same structure, including: a limiter, a filter, an amplifier and an analog-to-digital converter (ADC); the UWB radar receiving antenna is connected to the four groups of analog front-end sub-circuits respectively through a coaxial cable and an SMA interface. The echo signal received by the receiving antenna is transmitted to the analog-to-digital converter after passing through the limiter, the filter and the amplifier in sequence;

[0008] The delay circuit is composed of four groups of delayers. Each group of delayers has the same structure. The delayers are connected to the analog front-end sub-circuits one by one. The delayers respectively output delay signals to control the analog-to-digital converter (ADC) to complete data point acquisition; among them, the first to fourth groups of delayers generate four-way delay signals at intervals of Δt in sequence, and Δt is the time interval between adjacent sampling points; each group of delayers is composed of a coarse delay chip and a fine delay chip, which jointly generate a sequential sampling pulse delay signal; the time step of the fine delay chip is 4Δt, the time step of the coarse delay chip is the maximum range of the fine delay chip, and the FPGA counter step is the maximum range of the coarse delay chip. When the fine delay chip reaches the maximum range, the delay amount of the coarse delay chip is updated, the delay amount of the fine delay chip is set to zero and starts again until the coarse delay chip reaches the maximum range; when the coarse delay chip reaches the maximum range, the FPGA counter is updated, and the delay amounts of the fine delay chip and the coarse delay chip are set to zero and start again until the FPGA counter reaches the counting target; all sampling point data are arranged in time sequence to form a segment of echo signal;

[0009] The FPGA control circuit includes a data acquisition module, a delay signal generation module and an Ethernet communication module;

[0010] The Ethernet communication module is used to transmit the data in the dual-port random access memory to the host computer, and receive the time window parameter T sent by the host computer and forward it to the delay signal generation module;

[0011] The delay signal generation module is used to provide a synchronous clock for the four groups of ADCs in the delay circuit and the analog front-end circuit, and control the delay circuit; the delay signal generation module calculates the counting target N of the FPGA counter according to the time window parameter T and the maximum range ΔT of the coarse delay chip: N = T / ΔT, and then controls the delay circuit to complete N segments of echo signals and arrange them in time sequence to form an echo signal;

[0012] The data acquisition module is used to receive data from the ADC, perform bad point removal and signal reconstruction processing on it, and then cache the processed data into the dual-port random access memory in the Ethernet communication module; the process of bad point removal is as follows: set a sliding window with a size of 3, compare the data at the same time position in three consecutive echo signals within the sliding window, if the deviation of the value of a certain point of data from the average value exceeds 3 times the standard deviation, then determine that the point of data is a bad point and perform removal; the process of signal reconstruction is as follows: after bad point removal, perform averaging processing on the data at the same time position in three consecutive echo signals within the sliding window, and store the averaging result into the dual-port random access memory in the waveform order to obtain the reconstructed echo signal.

[0013] Further, the time window parameter T is specifically: T = S / V, where V is the medium propagation rate in the environment to be measured, and S is the detection range of the ultra-wideband logging radar.

[0014] Based on the above technical solutions, the beneficial effects of the present invention are as follows:

[0015] The present invention provides a receiving front end of an ultra-wideband logging radar based on FPGA, including three parts: an analog front-end circuit, a delay circuit, and an FPGA control circuit. Among them, the FPGA control circuit further includes a delay signal generation module, a data acquisition module, and an Ethernet communication module. The present invention combines the sequential equivalent sampling technique and the time interleaving technique in the sampling method, and uses four channels to sample signals to shorten the sampling period. The synchronous timing signal in the delay circuit is generated by the phase-locked loop on the FPGA development board and drives the timing device through the global clock input pin to obtain the minimum clock jitter and delay and suppress the clock drift phenomenon; at the same time, the delay circuit adopts a combination of a coarse delay device and a fine delay device to generate a large-range and high-precision delay signal to ensure the integrity and accuracy of the echo signal. When the echo signal is transmitted to the FPGA via the coaxial cable, the analog front-end circuit, and the analog-to-digital converter ADC, the FPGA will perform data screening, bad point removal, and signal reconstruction to reduce the distortion of the echo signal caused by signal instability during the signal transmission process; at the same time, use Ethernet to realize the information interaction between the upper computer and the FPGA to ensure high-speed and stable data transmission. The upper computer can also transmit parameters from the Ethernet to the FPGA according to different downhole environments and different detection distances. After the FPGA receives the data, it automatically calculates the reflection time of the echo signal, retains the minimum effective range of the echo signal, shortens the sampling period, realizes the function of dynamically adjustable time window length, and improves the applicability.

[0016] In summary, the present invention effectively reduces the sampling error caused by signal distortion during signal transmission, significantly improves the integrity and accuracy of the echo signal; at the same time, a dynamically adjustable function for the time window parameter is set, which shortens the sampling period while ensuring that the effective part of the echo signal can be completely collected, and more data can be collected within the same time, improving the applicability of the receiving front end under different downhole environments and different detection distance requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic structural diagram of the ultra-wideband logging radar receiving front end based on FPGA in the present invention.

[0018] Figure 2 It is a schematic structural diagram of the analog front-end circuit in the present invention.

[0019] Figure 3 It is a schematic structural diagram of the FPGA control circuit and the delay circuit in the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] To make the objectives, technical solutions and beneficial effects of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the drawings and embodiments.

[0021] This embodiment provides an ultra-wideband logging radar receiving front end based on FPGA, and its structural diagram is as Figure 1 shown, including three parts: an analog front-end circuit, a delay circuit, and an FPGA control circuit; specifically:

[0022] The analog front-end circuit is composed of four groups of analog front-end sub-circuits. Each group of analog front-end sub-circuits adopts the same structure, as Figure 2 shown, including a limiter, a filter, an amplifier, and an analog-to-digital converter (ADC); the ultra-wideband radar receiving antenna is respectively connected to the four groups of analog front-end sub-circuits through a coaxial cable and an SMA interface. The echo signal received by the receiving antenna is transmitted to the analog-to-digital converter after passing through the limiter, the filter, and the amplifier in sequence; the limiter is used to step down the echo signal to prevent damage to the filter due to excessive voltage. The filter selects a low-pass filter to initially filter high-frequency noise. The variable amplifier is used to convert the echo signal into a voltage signal that meets the requirements of the analog-to-digital converter (ADC); in this embodiment, the frequency band selection of the low-tube filter is determined by the application environment and the center frequency of the antenna, and the ADC selects a 16-bit high-speed ADC.

[0023] The delay circuit is composed of four groups of delayers. Each group of delayers has the same structure. The delayers are connected to the analog front-end sub-circuits one by one. The delayers respectively output delay signals to control the analog-to-digital converter (ADC) to complete data point acquisition. Among them, the first to fourth groups of delayers generate four delay signals with an interval of Δt in sequence. Δt is the time interval between adjacent sampling points, so as to ensure that the four groups of ADCs sequentially acquire four adjacent data points of the same echo signal, that is, to implement the time interleaving technology and shorten the originally required sampling time to one-fourth. Each group of delayers consists of a coarse delay chip with a large range and a fine delay chip with high precision. As Figure 3 shown, the combination of the two can generate a sequential sampling pulse delay signal with high precision and a large range, that is, to implement the sequential equivalent sampling technology. The time step of the fine delay chip is 4Δt, that is, the delay time for each sampling of a group of ADCs is the interval time of four sampling points. The time step of the coarse delay chip is the maximum range of the fine delay chip. The FPGA counter steps by the maximum range of the coarse delay chip. When the fine delay chip reaches the maximum range, the delay amount of the coarse delay chip is updated. The delay amount of the fine delay chip is set to zero and starts again until the coarse delay chip reaches the maximum range. When the coarse delay chip reaches the maximum range, the FPGA counter is updated. The delay amounts of the fine delay chip and the coarse delay chip are set to zero and start again until the FPGA counter reaches the counting target. The data of all sampling points are arranged in time sequence to form an echo signal. In this embodiment, the coarse delay chip uses DS1023-25, and the fine delay chip uses MC100EP95. The maximum delay range of the coarse delay chip DS1023-25 can reach 63.75 ns, and the minimum delay accuracy of the fine delay chip MC100EP95 is 10 ps, which can form a delay device with a large range and high precision. The sampling interval time between two adjacent groups of the four groups of delayers is the minimum delay accuracy of 10 ps of the fine delay chip MC100EP95, and the step time generated by each group of fine delay chips MC100EP95 for each sampling is 40 ps, that is, four adjacent data points on the echo signal are acquired for each sampling, and the distance between adjacent points is 10 ps.

[0024] The FPGA control circuit includes a data acquisition module, a delay signal generation module, and an Ethernet communication module, as Figure 3 shown;

[0025] The Ethernet communication module is used to transmit the data in the dual-port random access memory to the upper computer, and receive the time window parameters sent by the upper computer and forward them to the delay signal generation module. After receiving the data, the upper computer performs subsequent signal processing. At the same time, according to the medium propagation rate V and the detection range S in the actual application environment, the upper computer calculates the time window parameter T of the received signal: T = S / V, and sends it to the delay signal generation module;

[0026] The delay signal generation module is used to provide synchronous clocks for the delay circuit and four groups of ADCs in the analog front-end circuit, and control the delay amount of the delay chip in the delay circuit to perform sampling in the equivalent sampling mode in sequence; the delay signal generation module calculates the counting target N of the FPGA counter according to the time window parameter T and the maximum range ΔT of the coarse delay chip: N = T / ΔT, and then controls the delay circuit to complete N echo signals and arrange them in chronological order to form an echo signal, that is, the dynamic adjustment of the time window parameter according to the medium propagation speed V and the detection range S in the actual application environment is realized;

[0027] The data acquisition module is used to receive the data from the ADC, perform bad point elimination and signal reconstruction processing on it, and then cache the processed data into the dual-port random access memory in the Ethernet communication module;

[0028] The specific process of bad point elimination is as follows: Since the sampling period is short and the radar moving speed is much lower than the signal propagation speed, in this invention, any three adjacent consecutive echo signals in several collected echo signals are regarded as the same echo signal when the radar is approximately stationary. Then, by comparing these three consecutive echo signals, abnormal data is judged and bad points are eliminated; that is, the three data points at the same time position in the three consecutive echo signals are compared. If the deviation of the value of a certain data point from the average value exceeds 3 times the standard deviation, it is determined that the data point is a bad point and is eliminated;

[0029] The specific process of signal reconstruction is as follows: After bad point elimination, the data at the same time position in the three consecutive echo signals is averaged, and the averaged result is stored in the dual-port random access memory in the waveform order to complete the reconstruction of the echo signal.

[0030] As mentioned above, it is only the specific implementation manner of the present invention. Any feature disclosed in this specification, unless specifically described, can be replaced by other equivalent or similar-purpose alternative features; all the features disclosed, or all the steps in all the methods or processes, except for the mutually exclusive features and / or steps, can be combined in any way.

Claims

1. An ultra-wideband logging radar receiving front end based on FPGA, comprising: an analog front-end circuit, a delay circuit, and an FPGA control circuit; characterized in that: The analog front-end circuit is composed of four groups of analog front-end sub-circuits. Each group of analog front-end sub-circuits has the same structure, including: a limiter, a filter, an amplifier, and an analog-to-digital converter (ADC); the ultra-wideband radar receiving antenna is respectively connected to the four groups of analog front-end sub-circuits through a coaxial cable and an SMA interface. The echo signal received by the receiving antenna is transmitted to the analog-to-digital converter after passing through the limiter, the filter, and the amplifier in sequence; The delay circuit is composed of four groups of delay devices. Each group of delay devices has the same structure. The delay devices are connected to the analog front-end sub-circuits one by one. The delay devices respectively output delay signals to control the analog-to-digital converter (ADC) to complete data point acquisition; among them, the first to fourth groups of delay devices generate four-way delay signals with an interval of Δt in sequence, and Δt is the time interval between adjacent sampling points; each group of delay devices consists of a coarse delay chip and a fine delay chip, which jointly generate a sequential sampling pulse delay signal; the time step of the fine delay chip is 4Δt, and the time step of the coarse delay chip is the maximum range of the fine delay chip. The FPGA counter step is the maximum range of the coarse delay chip. When the fine delay chip reaches the maximum range, the delay amount of the coarse delay chip is updated. The delay amount of the fine delay chip is set to zero and starts again until the coarse delay chip reaches the maximum range; when the coarse delay chip reaches the maximum range, the FPGA counter is updated. The delay amounts of the fine delay chip and the coarse delay chip are set to zero and start again until the FPGA counter reaches the counting target; all sampling point data are arranged in time sequence to form an echo signal segment; The FPGA control circuit includes a data acquisition module, a delay signal generation module, and an Ethernet communication module; The Ethernet communication module is used to transmit the data in the dual-port random access memory to the host computer and receive the time window parameters sent by the host computer T and forward them to the delay signal generation module; The delay signal generation module is used to provide synchronous clocks for the delay circuit and four groups of ADCs in the analog front-end circuit, and control the delay circuit; the delay signal generation module calculates the counting target of the FPGA counter according to the time window parameter T and the maximum range Δ T of the coarse delay chip, N : N = T / Δ T , and then control the delay circuit to complete N segment echo signals and arrange them in chronological order to form an echo signal; The data acquisition module is used to receive data from the ADC, perform bad point removal and signal reconstruction processing on it, and then cache the processed data into the dual-port random access memory in the Ethernet communication module; the process of bad point removal is: set a sliding window with a size of 3, compare the data at the same time position in three consecutive echo signals within the sliding window. If the deviation of the value of a certain point data from the average value exceeds 3 times the standard deviation, then determine that the point data is a bad point and perform removal; the process of signal reconstruction is: after bad point removal, perform mean value processing on the data at the same time position in three consecutive echo signals within the sliding window, and store the mean value result into the dual-port random access memory in waveform order to obtain the reconstructed echo signal; Time window parameter T Specifically: T = S / V , V is the medium propagation rate in the environment to be measured, S is the detection range of the ultra-wideband logging radar.

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