A chip testing method, device and system
By protocolizing the test program through a bus protocol library, the problem of excessive I/O port usage in chip testing methods is solved, enabling chip testing that saves resources and reduces costs, and is applicable to chips with various bus interfaces.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- AMICRO SEMICONDUCTOR CO LTD
- Filing Date
- 2022-12-21
- Publication Date
- 2026-06-05
AI Technical Summary
Existing chip testing methods require additional I/O ports on the chip as test mode pins, which prevents the testing equipment from conserving channel resources and reduces the number of chips that can be tested simultaneously, making them particularly unsuitable for small-package chips.
The test program is protocolized by using a bus protocol library to meet the bus protocol transmission requirements of the chip under test. The test program is then directly transmitted using the digital channel of the ATE platform without occupying the chip's I/O ports, thus maximizing site-to-site parallel testing.
It saves valuable chip pin resources, reduces testing costs, and increases the number of chips that can be tested simultaneously on the ATE platform, making it suitable for chips with different bus interfaces.
Smart Images
Figure CN116148629B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip testing, specifically to a chip testing method, apparatus, and system. Background Technology
[0002] The cost of a chip impacts a product's competitiveness. Given a fixed chip area, it's crucial to minimize testing costs. There are two main methods to reduce chip testing costs: one is to reduce the testing time per chip; the other is to increase the number of chips that can be tested simultaneously (the number of chips that can be tested simultaneously is determined by the number of channels in the testing equipment). In other words, the more chips tested and the faster the testing speed, the lower the testing cost. However, current chip testing methods still require excessive use of ordinary function I / O ports as test mode pins when designing test modes. This prevents the testing equipment from conserving channel resources, reducing the number of chips that can be tested simultaneously. Furthermore, excessive I / O port usage is also detrimental to small-package chips. Summary of the Invention
[0003] This application provides a chip testing method, apparatus, and system, the specific technical solutions of which are as follows:
[0004] A chip testing method is disclosed, comprising: based on the bus protocol of the chip under test (DUT) and a bus protocol library, a host computer protocolizes a test program to obtain a protocolized test program; then, the protocolized test program is converted into a test program that can run on the current ATE platform; and the ATE platform transmits the test program processed by the ATE platform to the DUT for chip testing; wherein the protocolized test program meets the transmission requirements of the bus protocol of the DUT, and the DUT receives the test program processed by the ATE platform through a bus interface.
[0005] Furthermore, the bus protocol library includes SWD protocol functions. When the bus protocol is the SWD protocol, the bus interface is the SW-DP interface. The SW-DP interface includes SWDIO pins and SWDCLK pins. The chip under test receives the test program processed by the ATE platform through the SWDIO pins and SWDCLK pins.
[0006] Furthermore, the method for the host computer to protocolize the test program and obtain the protocolized test program specifically includes: the host computer detects the bus protocol of the chip under test, sends a read / write request to the chip under test, and if the chip returns a preset level signal, it is determined that the chip under test uses the SWD protocol. Then, the host computer inserts a frame header and a frame trailer into the test program to obtain the protocolized test program; wherein, the frame header and frame trailer enable the test program to meet the transmission requirements of the SWD protocol.
[0007] Furthermore, the frame header specifically includes: resetting the chip under test; controlling the chip under test to enter debug mode; writing the test program to the register or memory of the chip under test; the frame tail specifically includes: setting the program execution pointer, releasing the reset, so that the chip under test executes the test program from the register or memory.
[0008] Furthermore, the bus protocol library includes IIC protocol functions. When the bus protocol is an IIC protocol, the bus interface is an IIC interface. The IIC interface includes an SDA pin and an SCLK pin. The chip under test receives the test program processed by the ATE platform through the SDA pin and the SCLK pin.
[0009] Furthermore, the method for the host computer to protocolize the test program and obtain the protocolized test program specifically includes: the host computer detects the bus protocol of the chip under test, sends a read / write request to the chip under test, and if the chip returns a low-level ACK signal, it is determined that the chip under test uses the IIC protocol. Then, the host computer inserts a frame header and a frame trailer into the test program to obtain the protocolized test program; wherein, the frame header and frame trailer enable the test program to meet the transmission requirements of the IIC protocol.
[0010] Furthermore, the frame header specifically includes: generating an IIC protocol start signal; specifying the address frame of the chip under test and the address frame of the accessed register or memory; writing the test program to the register or memory of the chip under test; the frame tail specifically includes: generating an IIC protocol end signal; after a preset time, sequentially sending a power-down signal and a power-on signal to the chip under test, so that the chip under test executes the test program from the register or memory.
[0011] A chip testing apparatus is provided for implementing the chip testing method described above. The apparatus includes: an ATE platform connected to the chip under test (DUT) for transmitting a test program that meets the bus protocol transmission requirements of the DUT to the DUT; and the DUT receiving the test program processed by the ATE platform through a bus interface.
[0012] Furthermore, the bus protocol library includes SWD protocol functions. When the bus protocol is the SWD protocol, the bus interface is the SW-DP interface. The SW-DP interface includes SWDIO pins and SWDCLK pins. The chip under test is connected to the digital channel of the ATE platform through the SWDIO pins and SWDCLK pins.
[0013] Furthermore, the chip under test also includes a reset pin, which is connected to the digital channel of the ATE platform and is used to control the chip under test to perform tests.
[0014] Furthermore, the bus protocol library includes IIC protocol functions. When the bus protocol is an IIC protocol, the bus interface is an IIC interface. The IIC interface includes an SDA pin and an SCLK pin. The chip under test is connected to the digital channel of the ATE platform through the SDA pin and the SCLK pin.
[0015] Furthermore, the ATE platform includes several freely definable digital channels, which are connected to the bus interface of the chip under test. The ATE platform can simultaneously connect to chips under test with different bus interfaces through the digital channels.
[0016] A chip testing system includes the aforementioned chip testing device and a host computer connected to an ATE platform. The host computer includes a bus protocol library for protocolizing test programs, and the protocolized test programs meet the transmission requirements of the bus protocol of the chip under test.
[0017] The chip testing method described in this application protocols the test program using a bus protocol library. The protocolized test program meets the bus protocol transmission requirements of the chip under test (DUT), allowing the test program to be transmitted to the DUT via the bus interface without needing to occupy other I / O ports of the DUT as test mode pins, thus saving valuable pin resources. Furthermore, it reduces the channel resources required for the ATE platform to test a single chip, enabling the ATE platform to test more chips simultaneously, maximizing site-parallel testing, and significantly reducing testing costs. Attached Figure Description
[0018] Figure 1 This is a schematic flowchart of a chip testing method according to one embodiment of this application.
[0019] Figure 2 This is a schematic diagram of a chip testing device according to one embodiment of this application.
[0020] Figure 3 This is a schematic diagram of a test apparatus for a chip under test with an SW-DP interface, according to one embodiment of this application.
[0021] Figure 4 This is a schematic diagram of a chip testing system according to one embodiment of this application. Detailed Implementation
[0022] The technical solutions of the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described below are only for explaining the present invention and are not intended to limit the present invention.
[0023] In the following description, specific details are set forth to provide a thorough understanding of the embodiments. However, those skilled in the art will understand that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams so as not to obscure the embodiments with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure the embodiments.
[0024] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0025] The cost of a chip impacts a product's competitiveness. Given a fixed chip area, it's crucial to minimize testing costs. There are two main methods to reduce chip testing costs: one is to reduce the testing time per chip; the other is to increase the number of chips that can be tested simultaneously (the number of chips that can be tested simultaneously is determined by the number of channels in the testing equipment). In other words, the more chips tested and the faster the testing speed, the lower the testing cost. However, current chip testing methods still require excessive use of ordinary function I / O ports as test mode pins when designing test modes. This prevents the testing equipment from conserving channel resources, reducing the number of chips that can be tested simultaneously. Furthermore, excessive I / O port usage is also detrimental to small-package chips.
[0026] To address the aforementioned problems, embodiments of this application provide a chip testing method, such as... Figure 1 As shown, the test method specifically includes:
[0027] Based on the bus protocol and bus protocol library of the chip under test (DUT), the host computer protocols the test program to obtain a protocolized test program. This protocolized test program is then converted into a test program that can run on the current ATE platform. The ATE platform then transmits the processed test program to the DUT for chip testing. The protocolized test program meets the transmission requirements of the DUT's bus protocol, and the DUT receives the processed test program through the bus interface. It should be noted that in this application, the ATE (Automatic Test Equipment) platform refers to an integrated circuit automatic test machine, a device used to test the functional integrity of integrated circuits. The bus protocol library is essentially a function library containing a series of functions that can be extended. These functions can convert the compiled test program into a format that conforms to the transmission requirements of the corresponding bus protocol.
[0028] In one implementation, the bus protocol library includes SWD protocol functions. When the bus protocol is SWD, the bus interface is an SW-DP interface. The SW-DP interface includes SWDIO and SWDCLK pins. The chip under test (DUT) receives the test program processed by the ATE platform through the SWDIO and SWDCLK pins. It should be noted that the SW-DP interface (Serial Wire Debug Port) is a programming and debugging interface developed by ARM for ARM processors. Through this interface, the bus can be accessed, thereby accessing the CPU's registers, peripheral circuits, and memory units.
[0029] Based on the above embodiments, the method for the host computer to protocolize the test program and obtain the protocolized test program specifically includes: the host computer detects the bus protocol of the chip under test, sends a read / write request to the chip under test, and if the chip returns a preset level signal, such as a three-bit 001 level signal, it is determined that the chip under test uses the SWD protocol. Then, the host computer inserts a frame header and a frame trailer into the test program to obtain the protocolized test program; wherein, the frame header and frame trailer enable the test program to meet the transmission requirements of the SWD protocol.
[0030] Based on the above embodiments, when the chip under test uses the SWD protocol, the frame header specifically includes: resetting the chip under test; controlling the chip under test to enter debug mode; and writing the test program to the register or memory of the chip under test. The frame tail specifically includes: setting the program execution pointer and releasing the reset, so that the chip under test executes the test program from the register or memory. Furthermore, the register or memory of the chip under test can also be read to determine whether the written data is correct. Specifically, on the rising edge of SWDCLK, the host computer serially sends the test program to the chip under test via SWDIO.
[0031] In one implementation, the bus protocol library includes IIC protocol functions. When the bus protocol is an IIC protocol, the bus interface is an IIC interface. The IIC interface includes an SDA pin and an SCLK pin. The chip under test receives the test program processed by the ATE platform through the SDA pin and the SCLK pin.
[0032] Based on the above embodiments, the method for the host computer to protocolize the test program and obtain the protocolized test program specifically includes: the host computer detects the bus protocol of the chip under test, sends a read / write request to the chip under test, and if the chip returns a low-level ACK signal, it is determined that the chip under test uses the IIC protocol. Then, the host computer inserts a frame header and a frame trailer into the test program to obtain the protocolized test program. The frame header and frame trailer enable the test program to meet the transmission requirements of the IIC protocol. The ACK (ACK knowledge character) signal is a transmission control character sent by the receiving station to the sending station in data communication transmission, indicating that the received data has been received without error.
[0033] Based on the above embodiments, when the chip under test (DUT) uses the IIC protocol, the frame header specifically includes: generating an IIC protocol start signal; specifying the address frame of the DUT and the address frame of the accessed register or memory; writing the test program to the register or memory of the DUT; the frame tail specifically includes: generating an IIC protocol end signal; and after a preset time, sequentially sending a power-down signal and a power-on signal to the DUT, causing the DUT to execute the test program from the register or memory. Specifically, the method for generating the IIC protocol start signal is to change the SDA signal from high to low when the SCLK signal is high. The method for generating the IIC protocol end signal is to change the SDA signal from low to high when the SCLK signal is high. After waiting for a preset time to allow sufficient response time for the write operation, ensuring that the test program is successfully written, the ATE platform controls the DUT to power on again, resetting the DUT, and then executing the test program from the register or memory to achieve chip testing.
[0034] The chip testing method described in this application uses a bus protocol library to protocolize the test program. The protocolized test program meets the transmission requirements of the bus protocol of the chip under test, so that the test program can be transmitted to the chip under test through the bus interface without having to occupy other I / O ports of the chip under test as test mode pins, thus saving valuable pin resources of the chip.
[0035] Reference Figure 2This application provides a chip testing apparatus for implementing the chip testing method described above. The apparatus includes: an ATE platform connected to the chip under test (DUT) for transmitting a test program that meets the bus protocol transmission requirements of the DUT to the DUT; and the DUT receiving the test program processed by the ATE platform through a bus interface.
[0036] As one implementation method, refer to Figure 3 The bus protocol library includes SWD protocol functions. When the bus protocol is SWD, the bus interface is an SW-DP interface. The SW-DP interface includes SWDIO and SWDCLK pins. The chip under test (DUT) is connected to the digital channel of the ATE platform via the SWDIO and SWDCLK pins. The DUT also includes a reset pin (nRST), which is connected to the digital channel of the ATE platform and used to control the DUT to perform tests.
[0037] In one implementation, the bus protocol library includes IIC protocol functions. When the bus protocol is IIC, the bus interface is an IIC interface, which includes an SDA pin and an SCLK pin. The chip under test (DUT) connects to the digital channel of the ATE platform via the SDA and SCLK pins. It should be noted that when the bus interface of the DUT is an IIC interface, a reset pin is not required; that is, only two pins are needed to test the DUT.
[0038] Based on the above embodiments, referring to Figure 3The ATE platform includes several freely definable digital channels, which are connected to the bus interface of the chip under test (DUT). The ATE platform can simultaneously connect to DUTs with different bus interfaces through these digital channels. In one embodiment, DUT 1 uses the SWD protocol, with its SWDIO, SWDCLK, and reset pins connected to three digital channels of the ATE platform. DUT 2 uses the IIC protocol, with its SDA and SCLK pins connected to two digital channels of the ATE platform. The host computer protocols the test program according to different bus interfaces, converting it into a format that meets the transmission requirements of different bus protocols, and then transmits it to the corresponding DUT through the ATE platform. After receiving the protocolized test program from the host computer, the ATE platform parses the test program, generates corresponding test waveforms through the internal circuitry of the ATE platform's digital channels, and transmits them to the DUT. The DUT receives the test waveforms through its bus interface, enabling it to perform various tests based on the test waveforms. In this embodiment, assuming the ATE platform has 192 digital channels, taking a chip under test using the SW-DP interface as an example, it can perform simultaneous testing at 64 sites; taking a chip under test using the IIC interface as an example, it can perform simultaneous testing at 96 sites. This application reduces the channel resources required for the ATE platform to test a single chip, enabling the ATE platform to test more chips simultaneously, maximizing site-to-site parallel testing, and significantly reducing testing costs.
[0039] Reference Figure 4 This application provides a chip testing system, which includes the aforementioned chip testing device and a host computer connected to an ATE platform. The host computer includes a bus protocol library, which is used to protocolize the test program. The protocolized test program meets the transmission requirements of the bus protocol of the chip under test.
[0040] In one implementation, the host computer and the ATE platform communicate via a GPIB (General-Purpose Interface Bus) interface or a USB interface. In one embodiment, the host computer connects to the ATE platform via the GPIB interface, and further, the host computer also detects the type of the ATE platform via the GPIB interface. Each ATE platform contains a unique address associated with its GPIB interface; therefore, based on this address, the host computer can automatically detect the type of the ATE platform to which it is connected.
[0041] This application provides a computer storage medium storing the steps of the aforementioned chip testing method. When the chip testing method is executed, the test program is protocol-ized. The protocol-ized test program meets the bus protocol transmission requirements of the chip under test (DUT), allowing the test program to be transmitted to the DUT via the bus interface without needing to occupy other I / O ports of the DUT as test mode pins, thus saving valuable pin resources. Furthermore, it reduces the channel resources required for the ATE platform to test a single chip, enabling the ATE platform to test more chips simultaneously, maximizing site-parallel testing, and significantly reducing testing costs.
[0042] Obviously, the above embodiments are only some embodiments of the present invention, not all embodiments, and the technical solutions of various embodiments can be combined with each other. Furthermore, if terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" appear in the embodiments, they indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. If terms such as "first," "second," and "third" appear in the embodiments, they are for the convenience of distinguishing related features, and should not be construed as indicating or implying their relative importance, order, or number of technical features.
[0043] Furthermore, in the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0044] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the invention. The scope of the invention is defined by the appended claims and their equivalents. The above descriptions are merely preferred embodiments of the invention and are not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the scope of protection of the invention.
Claims
1. A chip testing method, characterized in that, The testing method specifically includes: Based on the bus protocol and bus protocol library of the chip under test (DUT), the host computer protocolizes the test program to obtain the protocolized test program. Then, the protocolized test program is converted into a test program that can run on the current ATE platform. The ATE platform then transmits the test program processed by the ATE platform to the DUT for chip testing. The protocolized test program meets the transmission requirements of the bus protocol of the DUT, and the DUT receives the test program processed by the ATE platform through the bus interface. The method for the host computer to protocolize the test program and obtain the protocolized test program specifically includes: the host computer detects the bus protocol of the chip under test, sends a read / write request to the chip under test, and if the chip returns a preset level signal, it is determined that the chip under test uses the SWD protocol. Then, the host computer inserts a frame header and a frame trailer into the test program to obtain the protocolized test program; wherein the frame header and frame trailer enable the test program to meet the transmission requirements of the SWD protocol.
2. The chip testing method according to claim 1, characterized in that, The bus protocol library includes SWD protocol functions. When the bus protocol is SWD, the bus interface is an SW-DP interface. The SW-DP interface includes SWDIO pins and SWDCLK pins. The chip under test receives the test program processed by the ATE platform through the SWDIO pins and SWDCLK pins.
3. The chip testing method according to claim 2, characterized in that, The frame header specifically includes: Reset the chip under test; Control the chip under test to enter debug mode; Write the test program to the registers or memory of the chip under test; The frame tail specifically includes: Set the program execution pointer and release the reset, so that the chip under test can execute the test program from the register or memory.
4. The chip testing method according to claim 1, characterized in that, The bus protocol library includes IIC protocol functions. When the bus protocol is the IIC protocol, the bus interface is the IIC interface. The IIC interface includes SDA pins and SCLK pins. The chip under test receives the test program processed by the ATE platform through the SDA pins and SCLK pins.
5. A chip testing method according to claim 4, characterized in that, The method by which the host computer protocols the test program to obtain the protocolized test program specifically includes: The host computer detects the bus protocol of the chip under test and sends read / write requests to the chip under test. If the chip returns a low-level ACK signal, it is determined that the chip under test uses the IIC protocol. Then, the host computer inserts frame headers and trailers into the test program to obtain the protocol-encoded test program. The frame headers and trailers ensure that the test program meets the transmission requirements of the IIC protocol.
6. The chip testing method according to claim 5, characterized in that, The frame header specifically includes: Generate IIC protocol start signal; Specify the address frame of the chip under test and the address frame of the register or memory to be accessed; Write the test program to the registers or memory of the chip under test; The frame tail specifically includes: Generate an IIC protocol end signal; After a preset time, power-down and power-on signals are sent sequentially to the chip under test, causing the chip under test to execute the test program from the register or memory.
7. A chip testing device, characterized in that, The apparatus is used to implement the chip testing method according to any one of claims 1-6, and the apparatus comprises: The ATE platform connects to the chip under test (DUT) and is used to transmit test programs that meet the DUT's bus protocol transmission requirements to the DUT. The chip under test receives the test program processed by the ATE platform through the bus interface.
8. The chip testing apparatus according to claim 7, characterized in that, The bus protocol library includes SWD protocol functions. When the bus protocol is SWD, the bus interface is an SW-DP interface. The SW-DP interface includes SWDIO pins and SWDCLK pins. The chip under test is connected to the digital channel of the ATE platform through the SWDIO pins and SWDCLK pins.
9. A chip testing apparatus according to claim 8, characterized in that, The chip under test also includes a reset pin, which is connected to the digital channel of the ATE platform and is used to control the chip under test to perform tests.
10. A chip testing apparatus according to claim 7, characterized in that, The bus protocol library includes IIC protocol functions. When the bus protocol is the IIC protocol, the bus interface is the IIC interface. The IIC interface includes SDA pins and SCLK pins. The chip under test is connected to the digital channel of the ATE platform through the SDA pins and SCLK pins.
11. A chip testing apparatus according to claim 8 or 10, characterized in that, The ATE platform includes several freely definable digital channels, which are connected to the bus interface of the chip under test. The ATE platform can simultaneously connect to chips under test with different bus interfaces through the digital channels.
12. A chip testing system, characterized in that, The system includes the chip testing device according to any one of claims 7-11, and the system further includes a host computer connected to the ATE platform. The host computer includes a bus protocol library, which is used to protocolize the test program. The protocolized test program meets the transmission requirements of the bus protocol of the chip under test.