Timer correction algorithm and control device for a photovoltaic disconnector

Abstract

The present invention relates to a timer deviation correction algorithm and a control device for a photovoltaic switch, comprising obtaining a timer within a first time threshold Fs The number of rising edges of the signal; the detection timer is within the second time threshold Fs The actual number of rising edges of the signal; according to the timer within the first time threshold Fs The number of rising edges of the signal and the timer within the second time threshold Fs The actual number of rising edges of the signal determines whether the currently detected signal is correct. PLC signal; when judging that the currently detected signal is correct PLC After the signal is received, the timer counts according to the third time threshold; the remaining time of the first code element in the transmission cycle and the timing of the remaining code elements are completed according to the third time threshold; the current real clock cycle is calculated through a fixed frequency, the length of the timer is reversely corrected, and the hardware is reduced. BOM Cost, reduce costs in the case of large-scale shipments; compared with the calibration lookup table method, since there is no need to calibrate each MCU in advance, the operability is greatly increased.

Description

Technical Field

[0001] The present invention belongs to the technical field of disconnector control, and particularly relates to a timer correction algorithm and a control device for a photovoltaic disconnector. Background Art

[0002] With the increasing emphasis on the safety of photovoltaic systems across the industry, the application of disconnectors in photovoltaic systems has become more and more widespread. Currently, SunSpec the alliance has defined the communication format for the disconnection and opening commands between the inverter and the photovoltaic module. As Figure 1 、 Figure 2 shown, a complete command cycle consists of a transmission cycle of 186.96 ms (with PLC signal) and a quiet cycle of 901.12 ms (without PLC signal).

[0003] For the command in the transmission cycle ABC , it is composed of 33 consecutive ms of Fs (143.75 KHz , represented by -1 in Figure 3 ) or Fm (131.25 KHz , represented by +1 in Figure 3 ) of FSK signals.

[0004] When the disconnector identifies the command, it needs to set a 5.12 ms timer to sample these code elements in sequence and determine whether the frequency of the ms signal within this 5.12 PLC conforms to the definition of Fs or Fm . The working environment of the disconnector is often relatively high, and at the same time, the large current passing through the board is more likely to further raise the temperature of the single-chip microcomputer. When the temperature of the single-chip microcomputer rises to a certain level, if the internal RC oscillator is used as the clock source, the clock cycle will increase significantly compared to the normal temperature state, resulting in an extension of the actual timing time of the timer. The continuous accumulation of this error will cause a significant number of sampling points to be "squeezed" into the quiet cycle when sampling the last code element, resulting in an incorrect frequency judgment for this code element. To correct such frequency deviation, an external crystal oscillator can be used as the clock source. However, the disconnector is a cost-sensitive device, and using an external crystal oscillator will greatly increase the batch cost of the product.

[0005] Another method is to calibrate the internal clock cycle of the single-chip microcomputer at different temperatures in advance and make a table. During operation, through ADRead the temperature and then look up the table to obtain the current true clock cycle. However, due to the discreteness of device characteristics, it is necessary to calibrate each single-chip microcomputer, and the calibration process will consume huge time and labor costs, which is actually more infeasible.

[0006] Therefore, based on the above technical problems, it is necessary to design a new timer correction algorithm and control device for a photovoltaic disconnector. Summary of the Invention

[0007] The object of the present invention is to provide a timer correction algorithm and control device for a photovoltaic disconnector.

[0008] To solve the above technical problems, the present invention provides a timer correction algorithm for a photovoltaic disconnector, including:

[0009] Obtain the number of rising edges of the signal within the first time threshold of the timer Fs ;

[0010] Detect the actual number of rising edges of the signal within the second time threshold of the timer Fs ;

[0011] According to the number of rising edges of the signal within the first time threshold of the timer Fs and the actual number of rising edges of the signal within the second time threshold of the timer Fs to determine whether the currently detected signal is the correct PLC signal;

[0012] After determining that the currently detected signal is the correct PLC signal, the timer counts according to the third time threshold;

[0013] According to the third time threshold, complete the timing of the remaining time of the first symbol and the remaining symbols in the transmission cycle.

[0014] Furthermore, the first time threshold is T , T ∈ R , and the unit is ms ;

[0015] After setting the first time threshold T , within the range of the first time threshold T , obtain Fs the number of rising edges of the signal N .

[0016] Furthermore, the zero-crossing detection method is used to detect the number of rising edges.

[0017] Furthermore, the actual number of rising edges of the signal within the second time threshold of detecting the timer Fs , that is,

[0018] Detect that the timer is within the second time threshold when the symbol sequence first appears during the transmission cycle Fs The actual number of rising edges of the signal;

[0019] The second time threshold is T / 2;

[0020] The timer is within the second time threshold Fs The actual number of rising edges of the signal is n .

[0021] Furthermore, the method for judging whether the currently detected signal is a correct signal according to the number of actual rising edges of the signal when the timer is within the second time threshold includes: Fs If PLC The method for judging whether the currently detected signal is a correct signal includes:

[0022] If abs ( n - N / 2)> K , where K is an empirical value, then the currently detected signal is an incorrect PLC signal, and the algorithm exits at this time.

[0023] Furthermore, the method for the timer to count time according to the third time threshold after judging that the currently detected signal is a correct PLC signal includes:

[0024] If abs ( n - N / 2)≤ K , where K is an empirical value, then the currently detected signal is a correct PLC signal, and at this time the third time threshold is T * N / (2* n ).

[0025] Furthermore, the method for completing the timing of the remaining time of the first symbol and the remaining symbols in the transmission cycle according to the third time threshold includes:

[0026] Set the timer to ( N / n -1)* T / 2 to complete the timing of the remaining time of the first symbol in the transmission cycle.

[0027] Furthermore, the method for completing the timing of the remaining time of the first symbol and the remaining symbols in the transmission cycle according to the third time threshold further includes:

[0028] Set the timer to T *N / (2 * n ), to complete the timing of the remaining symbols in the transmission cycle.

[0029] On the other hand, the present invention also provides a control device adopting the timer correction algorithm of the above photovoltaic disconnector, including:

[0030] PLC A controller;

[0031] The PLC controller calculates the number of rising edges of the signal within the first time threshold of the timer; Fs for the signal.

[0032] The PLC controller detects the actual number of rising edges of the signal within the second time threshold of the timer; Fs for the signal.

[0033] The PLC controller determines whether the currently detected signal is the correct Fs signal according to the number of rising edges of the signal within the first time threshold of the timer and the actual number of rising edges of the signal within the second time threshold of the timer; Fs signal; PLC signal;

[0034] The PLC controller, after determining that the currently detected signal is the correct PLC signal, causes the timer to time according to the third time threshold;

[0035] The PLC controller completes the timing of the remaining time of the first symbol and the remaining symbols in the transmission cycle according to the third time threshold.

[0036] Furthermore, the first time threshold is T , the second time threshold is T / 2, and the actual number of rising edges of the signal within the second time threshold of the timer is Fs ; n ;

[0037] If abs ( n - N / 2) ≤ K , where K is an empirical value, then the currently detected signal is the correct PLC signal, and at this time the third time threshold is T * N / (2 * n );

[0038] The PLC controller sets the timer to (N / n -1)* T / 2 to complete the timing of the remaining time of the first symbol in the transmission cycle;

[0039] The PLC controller sets the timer to T * N / (2* n ) to complete the timing of the remaining symbols in the transmission cycle.

[0040] The beneficial effect of the present invention is that by obtaining the number of rising edges of the signal within the first time threshold of the timer; detecting the actual number of rising edges of the signal within the second time threshold of the timer; judging whether the currently detected signal is the correct signal according to the number of rising edges of the signal within the first time threshold of the timer and the actual number of rising edges of the signal within the second time threshold of the timer; after judging that the currently detected signal is the correct signal, the timer times according to the third time threshold; completing the timing of the remaining time of the first symbol and the remaining symbols in the transmission cycle according to the third time threshold; realizing the calculation of the current true clock cycle through a fixed frequency, realizing the reverse correction of the length of the timer, compared with the method of adding an external crystal oscillator, reducing the hardware Fs cost, reducing costs in the case of large - volume shipments; compared with the calibration look - up table method, since there is no need to calibrate each single - chip microcomputer in advance, the operability is greatly increased. Fs signal; after judging that the currently detected signal is the correct Fs signal, the timer times according to the third time threshold; completing the timing of the remaining time of the first symbol and the remaining symbols in the transmission cycle according to the third time threshold; realizing the calculation of the current true clock cycle through a fixed frequency, realizing the reverse correction of the length of the timer, compared with the method of adding an external crystal oscillator, reducing the hardware Fs cost, reducing costs in the case of large - volume shipments; compared with the calibration look - up table method, since there is no need to calibrate each single - chip microcomputer in advance, the operability is greatly increased. PLC signal; after judging that the currently detected signal is the correct PLC signal, the timer times according to the third time threshold; completing the timing of the remaining time of the first symbol and the remaining symbols in the transmission cycle according to the third time threshold; realizing the calculation of the current true clock cycle through a fixed frequency, realizing the reverse correction of the length of the timer, compared with the method of adding an external crystal oscillator, reducing the hardware BOM cost, reducing costs in the case of large - volume shipments; compared with the calibration look - up table method, since there is no need to calibrate each single - chip microcomputer in advance, the operability is greatly increased.

[0041] Other features and advantages of the present invention will be described in the following description of the specification, and some of them will be obvious from the description of the specification, or understood by implementing the present invention. The objectives and other advantages of the present invention are achieved and obtained by the structures specifically pointed out in the specification and the drawings.

[0042] To make the above - mentioned objectives, features and advantages of the present invention more obvious and understandable, the following specifically gives preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following - described drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0044] Figure 1It is the operation flowchart of the timer correction algorithm of the photovoltaic disconnector of the present invention;

[0045] Figure 2 It is the schematic diagram of the command cycle of the present invention;

[0046] Figure 3 It is of the present invention PLC Schematic diagram of the signal;

[0047] Figure 4 It is the schematic diagram of the transmission cycle of the present invention;

[0048] Figure 5 It is the algorithm flowchart of the timer correction algorithm of the photovoltaic disconnector of the present invention. Detailed implementation manners

[0049] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Embodiment 1

[0050] As Figures 1 to 5 shown, Embodiment 1 of the present invention provides a timer correction algorithm for a photovoltaic disconnector, including: obtaining the number of rising edges of the Fs signal within the first time threshold of the timer; detecting the actual number of rising edges of the Fs signal within the second time threshold of the timer when the symbol sequence first appears in the transmission cycle; judging whether the currently detected signal is the correct Fs signal according to the number of rising edges of the Fs signal within the first time threshold of the timer and the actual number of rising edges of the PLC signal within the second time threshold of the timer; after judging that the currently detected signal is the correct PLC signal, the timer counts according to the third time threshold; completing the timing of the remaining time of the first symbol and the remaining symbols in the transmission cycle according to the third time threshold; realizing the calculation of the current true clock cycle through a fixed frequency, realizing the reverse correction of the length of the timer, compared with the method of adding an external crystal oscillator, reducing the BOM hardware cost and reducing the cost in the case of large-scale shipments; compared with the calibration look-up table method, since it is not necessary to calibrate each single-chip microcomputer in advance, the operability is greatly increased.

[0051] In this embodiment, since the input PLCThe frequency of the symbol (such as the first symbol) at a given position of the signal is fixed. When using the zero-crossing detection method (rising edge counting) to test the frequency, the frequency value is directly proportional to the actual duration of the timer. In this embodiment, the current true clock cycle is calculated by a fixed frequency to reverse-correct the length of the timer. Compared with the method of adding an external crystal oscillator, the hardware BOM cost is reduced, and the cost is reduced in the case of large-scale shipments.

[0052] In this embodiment, the first time threshold is T , T ∈ R , with the unit of ms ; after setting the first time threshold T , within the range of the first time threshold T , the number of rising edges Fs of the N signal is obtained.

[0053] In this embodiment, assuming that the first time threshold ms of the timer corresponding to the ideal 5.12 T time, within the T time Fs the number of rising edges of the kHz signal (142.75 N ) is KHz . For a sine wave signal of 142.75 ms , within 5.12 N time,

[0054] In this embodiment, the actual number of rising edges of the Fs signal detected by the detection timer within the second time threshold, that is, the actual number of rising edges of the Fs signal detected by the detection timer within the second time threshold when the symbol sequence just appears in the transmission cycle; the second time threshold is T / 2; the actual number of rising edges of the Fs signal detected by the timer within the second time threshold is n .

[0055] In this embodiment, the second time threshold of timer TIM 1 is T / 2. Starting from when 33 symbol sequences just appear, the rising edges are counted. The actual number of rising edges obtained within the second time threshold is n , n is T / 2 ( T the timing time of / 2 is not necessarily 2.56 ms ) within the Fs signal; N is 5.12ms Inner Fs The actual number of rising edges of the signal.

[0056] In this embodiment, the method of determining whether the currently detected signal is a correct signal according to the timer within the second time threshold includes: If Fs the actual number of rising edges of the signal is such that PLC ( abs ( n - N / 2)> K , where K is an empirical value, then the currently detected signal is an incorrect PLC signal, and the algorithm exits at this time.

[0057] In this embodiment, abs means taking the absolute value. Therefore, abs ( n - N / 2) represents the absolute value of ( n - N / 2).

[0058] In this embodiment, after determining that the currently detected signal is a correct PLC signal, the method of timing the timer according to the third time threshold includes: If abs ( n - N / 2)≤ K , where K is an empirical value, then the currently detected signal is a correct PLC signal, and at this time the third time threshold is T * N / (2* n ).

[0059] In this embodiment, the true set value of the timer corresponding to 5.12 ms time should be T * N / (2* n ).

[0060] In this embodiment, the method of timing the remaining time of the first symbol and the remaining symbols in the transmission cycle according to the third time threshold includes: Setting the timer to ( N / n -1)* T / 2 to complete the timing of the remaining time of the first symbol in the transmission cycle.

[0061] In this embodiment, in actual situations, when the timer is set to T / 2, the actually obtained timing time is 5.12* n / N ( ms ), so the remaining time of the first symbol should be 5.12 * (1 - n / N ). After proportional conversion, the set value of the timer at this time is ([[]] N / n - 1) * T / 2.

[0062] In this embodiment, the method for timing the remaining time of the first symbol and the remaining symbols in the transmission cycle according to the third time threshold further includes: setting the timer to T * N / (2 * n ) to complete the timing of the remaining symbols in the transmission cycle.

[0063] In this embodiment, the actual set value of the timer TIM 2 is set to T * N / (2 * n ) to complete the timing of the remaining 32 symbols.

[0064] In this embodiment, the zero-crossing detection method is used to detect the number of rising edges. The zero-crossing detection method is the function of a comparator, which can convert a sine wave with a certain frequency into a square wave or a pulse wave. This is necessary in places such as measuring frequency because fpga it only recognizes edges and does not recognize sine waves. The algorithm is divided into two parts: the determination of the zero point and the generation of the pulse wave. Why is it necessary to determine the zero point? We know that generally ad is, for example, from 0 to 5 V converted to from 0 to 255, or it can be -2 to 2 V input, and there will be a conversion circuit inside. So generally the zero point will not be 0, but more likely 125 or 126. However, for greater accuracy, the true zero point should be ( max + min ) / 2. The program for collecting the maximum and minimum values is very common, which is to continuously update a register and assign the value to max or min after a period of time. The generation of the pulse wave is to compare the two adjacent data points. If the previous one is less than the zero point and the next one is greater than the zero point, a zero-crossing pulse is generated.

[0065] In this embodiment, since the PV module disconnector is used in conjunction with the module and has a large shipment volume, the cost control of the disconnector is very critical. Compared with the method of adding an external crystal oscillator, the timer correction algorithm of this PV disconnector reduces the hardware BOMCost. In the case of large - volume shipments, the reduction in project cost is also significant. Compared with the calibration look - up table method, due to large - volume shipments and the discreteness of each single - chip microcomputer, the practical operability is greatly improved. This algorithm is very suitable for the timer correction process of photovoltaic disconnect products. Embodiment 2

[0066] Based on Embodiment 1, Embodiment 2 further provides a control device adopting the timer correction algorithm of the photovoltaic disconnect in Embodiment 1, including: PLC A controller; the PLC The controller calculates the number of rising edges of the signal within the first time threshold of the timer Fs ; the PLC The controller detects the actual number of rising edges of the signal within the second time threshold of the timer Fs ; the PLC The controller determines whether the currently detected signal is the correct Fs signal according to the number of rising edges of the signal within the first time threshold of the timer and the actual number of rising edges of the signal within the second time threshold of the timer Fs ; the PLC After the controller determines that the currently detected signal is the correct PLC signal, it causes the timer to time according to the third time threshold PLC ; the PLC The controller completes the timing of the remaining time of the first symbol and the remaining symbols in the transmission cycle according to the third time threshold.

[0067] In this embodiment, the first time threshold is T , the second time threshold is T / 2, the actual number of rising edges of the signal within the second time threshold of the timer is Fs ; if n ; if abs ( n - N / 2)≤ K , where K is an empirical value, then the currently detected signal is the correct PLC signal. At this time, the third time threshold is T * N / (2* n ); the PLC The controller sets the timer to ([[]] N / n -1)* T / 2 to complete the timing of the remaining time of the first symbol in the transmission cycle; the PLC The controller sets the timer to T * N / (2* n) to complete the timing of the remaining code elements in the transmission cycle.

[0068] In summary, the present invention obtains the timer within the first time threshold Fs The number of rising edges of the signal; the detection timer is within the second time threshold Fs The actual number of rising edges of the signal; according to the timer within the first time threshold Fs The number of rising edges of the signal and the timer within the second time threshold Fs The actual number of rising edges of the signal determines whether the currently detected signal is correct. PLC signal; when judging that the currently detected signal is correct PLC After the signal is received, the timer counts according to the third time threshold; the remaining time of the first code element in the transmission cycle and the timing of the remaining code elements are completed according to the third time threshold; the current real clock cycle is calculated by a fixed frequency, and the length of the timer is reversely corrected, which reduces the hardware compared with the method of adding an external crystal oscillator. BOM Cost, reduce costs in the case of large-scale shipments; compared with the calibration lookup table method, since there is no need to calibrate each MCU in advance, the operability is greatly increased.

[0069] Due to the input PLC The frequency of the code element (such as the first code element) of the signal at a given position is fixed. When the zero-crossing detection method (rising edge counting) is used to test the frequency, the frequency value is directly proportional to the actual duration of the timer. The present invention calculates the current real clock cycle through a fixed frequency to achieve reverse correction of the timer length. Compared with the method of adding an external crystal oscillator, the hardware is reduced. BOM Cost, reduce costs in case of large-volume shipments.

[0070] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of devices, methods, and computer program products according to multiple embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0071] In addition, each functional module in various embodiments of the present invention may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.

[0072] If the described functions are implemented in the form of software functional modules and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: U a floppy disk, a mobile hard disk, a read-only memory ( ROM , Read - Only Memory ), a random access memory ( RAM , Random Access Memory ), a magnetic disk, or an optical disk, and other media that can store program codes.

[0073] Based on the above-mentioned ideal embodiments of the present invention as inspiration, through the above description, relevant staff can completely make various changes and modifications without departing from the technical idea of this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A timer correction algorithm for a photovoltaic disconnector, characterized in that, Including: Obtaining the number of rising edges of the Fs signal within the first time threshold by the timer; Detecting the actual number of rising edges of the Fs signal within the second time threshold by the timer when the symbol sequence just appears in the transmission cycle; Judging whether the currently detected signal is a correct PLC signal according to the number of rising edges of the Fs signal within the first time threshold by the timer and the actual number of rising edges of the Fs signal within the second time threshold by the timer; After judging that the currently detected signal is a correct PLC signal, making the timer time according to the third time threshold; Completing the timing of the remaining time of the first symbol and the remaining symbols in the transmission cycle according to the third time threshold; The first time threshold is T, and the number of rising edges of the Fs signal within the first time threshold by the timer is N; The second time threshold is T / 2, and the actual number of rising edges of the Fs signal within the second time threshold by the timer is n; If abs(n - N / 2) ≤ K, and K is an empirical value, then the currently detected signal is a correct PLC signal, and the third time threshold is T*N / (2*n); Setting the timer to (N / n - 1)*T / 2 to complete the timing of the remaining time of the first symbol in the transmission cycle; Setting the timer to T*N / (2*n) to complete the timing of the remaining symbols in the transmission cycle.

2. The timer correction algorithm of the photovoltaic disconnector according to claim 1, characterized in that The zero-crossing detection method is adopted to detect the number of rising edges.

3. A control device adopting a timer correction algorithm of a photovoltaic disconnector as described in any one of claims 1-2, characterized in that, Including: PLC controller; The PLC controller calculates the number of rising edges of the Fs signal within the first time threshold by the timer; The PLC controller calculates the actual number of rising edges of the Fs signal within the second time threshold by the timer when the symbol sequence just appears in the transmission cycle; The PLC controller judges whether the currently detected signal is a correct PLC signal according to the number of rising edges of the Fs signal within the first time threshold by the timer and the actual number of rising edges of the Fs signal within the second time threshold by the timer; After the PLC controller judges that the currently detected signal is a correct PLC signal, making the timer time according to the third time threshold; The PLC controller completes the timing of the remaining time of the first symbol and the remaining symbols in the transmission cycle according to the third time threshold.

4. The control device according to claim 3, characterized in that The first time threshold is T, the second time threshold is T / 2, the number of rising edges of the Fs signal within the first time threshold by the timer is N, and the actual number of rising edges of the Fs signal within the second time threshold by the timer is n; If abs(n - N / 2) ≤ K, and K is an empirical value, then the currently detected signal is a correct PLC signal, and the third time threshold is T*N / (2*n); The PLC controller sets the timer to (N / n - 1)*T / 2 to complete the timing of the remaining time of the first symbol in the transmission cycle; The PLC controller sets the timer to T*N / (2*n) to complete the timing of the remaining symbols in the transmission cycle.

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