Method for updating host and flash memory address comparison table, computer readable storage medium and device

Abstract

The present invention relates to a method, computer-readable storage medium, and device for updating a host-to-flash memory address comparison table. The method comprises: allocating space in a random access memory for a first host-to-flash memory address comparison subtable and intermediate information for updating a second host-to-flash memory address comparison subtable in a flash memory module; updating the first host-to-flash memory address comparison subtable and the intermediate information temporarily stored in the random access memory when a host write command is executed to write data to the flash memory module or a host discard command is executed to discard data in the flash memory module; and, in a table update procedure, writing the first host-to-flash memory address comparison subtable temporarily stored in the random access memory to a system block in the flash memory module, updating the second host-to-flash memory address comparison subtable based on the intermediate information temporarily stored in the random access memory, and writing the updated second host-to-flash memory address comparison subtable to the system block in the flash memory module. By checking random write conditions, delays in the execution of subsequent host read commands and / or host write commands due to a large number of host-to-flash memory address comparison subtable updates can be avoided.

Description

Technical Field

[0001] The present invention relates to a storage device, and in particular to a method for updating a host and flash memory address comparison table, a computer-readable storage medium and a device. Background Art

[0002] Flash memory is generally divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The central processing unit (Host) can provide any address to access the NOR flash memory on the address pin and obtain the data stored at the address from the data pin of the NOR flash memory in a timely manner. In contrast, NAND flash memory is not random access, but serial access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the CPU needs to write serial byte values to the NAND flash memory to define the type of request command (such as read, write, erase, etc.) and the address used for this command. The address can point to a page (the smallest data block for write operations in flash memory) or a block (the smallest data block for erase operations in flash memory).

[0003] In order to improve the data writing and reading performance of the flash memory module, the flash memory controller will perform data writing and reading in parallel with multiple channels. In order to achieve the purpose of parallel processing, a continuous piece of data will be stored in a dispersed manner in the flash memory units connected to multiple channels, and a host-to-flash address mapping table (Host-to-Flash Address Mapping Table, referred to as H2F table) is used to record the correspondence between the logical address (managed by the host side) and the physical address (managed by the flash memory controller) of the user data. However, the update of the H2F table also affects the performance of the entire system. Therefore, the present invention proposes a method for updating the host-to-flash address mapping table, a computer-readable storage medium and a device for improving the overall performance of the system. Summary of the Invention

[0004] In view of this, how to alleviate or eliminate the deficiencies in the above-mentioned related fields is indeed a problem to be solved.

[0005] The present invention relates to a method for updating a host-to-flash memory address comparison table, which is executed by a processing unit and comprises: allocating space in a random access memory for a first host-to-flash memory address comparison subtable and for intermediate information used to update a second host-to-flash memory address comparison subtable in a flash memory module; updating the first host-to-flash memory address comparison subtable and the intermediate information temporarily stored in the random access memory when a host write command is executed to write data to the flash memory module or a host discard command is executed to discard data in the flash memory module; and in a table update procedure, writing the first host-to-flash memory address comparison subtable temporarily stored in the random access memory into a system block in the flash memory module, updating the second host-to-flash memory address comparison subtable according to the intermediate information temporarily stored in the random access memory, and writing the updated second host-to-flash memory address comparison subtable into the system block in the flash memory module.

[0006] The present invention also relates to a computer-readable storage medium comprising a computer program. When a processing unit loads and executes the computer program, the method for updating the host and flash memory address comparison table as shown above is implemented.

[0007] The present invention also relates to a device for updating a host-to-flash memory address comparison table, comprising: a random access memory; a flash memory interface; and a processing unit. The flash memory interface is coupled to a flash memory module, and the processing unit is coupled to the random access memory and the flash memory interface. The processing unit is configured to allocate space in the random access memory for a first host-to-flash memory address comparison subtable and intermediate information for updating a second host-to-flash memory address comparison subtable in the flash memory module; update the first host-to-flash memory address comparison subtable and the intermediate information temporarily stored in the random access memory when a host write command is executed to write data to the flash memory module or a host discard command is executed to discard data in the flash memory module; and, in a table update procedure, write the first host-to-flash memory address comparison subtable temporarily stored in the random access memory to a system block in the flash memory module, update the second host-to-flash memory address comparison subtable based on the intermediate information temporarily stored in the random access memory, and write the updated second host-to-flash memory address comparison subtable to the system block in the flash memory module.

[0008] One of the advantages of the above embodiment is that by checking the random write condition as described above, it is possible to avoid delaying the execution of subsequent host read commands and / or host write commands due to a large number of host and flash memory address comparison sub-table updates.

[0009] Other advantages of the present invention will be explained in more detail with reference to the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application.

[0011] Figure 1 FIG. 4 is a system architecture diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2 FIG. 1 is a schematic diagram of a flash memory module according to an embodiment of the present invention.

[0013] Figure 3 FIG. 1 is a schematic diagram of a NAND flash memory cell according to an embodiment of the present invention.

[0014] Figure 4 FIG. 4 is a schematic diagram illustrating the association between a high-level lookup table and a host and flash memory address lookup sub-table according to an embodiment of the present invention.

[0015] Figure 5 Schematic diagram of the association between the host and flash memory address comparison sub-table and physical pages according to an embodiment of the present invention.

[0016] Figure 6 FIG. 4 is a flow chart of a method for executing a host write command according to an embodiment of the present invention.

[0017] Figure 7 4 is a flow chart of a method for executing a host discard command according to an embodiment of the present invention.

[0018] Figure 8 FIG. 4 is a flow chart of a method for executing a table update procedure according to an embodiment of the present invention.

[0019] Wherein, the reference numerals:

[0020] 10 Electronic devices

[0021] 110 host side

[0022] 130 Flash Memory Controller

[0023] 131 host interface

[0024] 132 bus architecture

[0025] 134 processing units

[0026] 136 Random Access Memory

[0027] 138 Direct Memory Access Controller

[0028] 139 flash memory interface

[0029] 150 flash memory modules

[0030] 151 interface

[0031] 153#0~153#15 NAND flash memory unit

[0032] CH#0~CH#3 channels

[0033] CE#0~CE#3 start signal

[0034] 310, 330 data plane

[0035] 310#0~310#m, 330#0~330#m physical blocks

[0036] P#0~P#n physical pages

[0037] 410 Advanced Comparison Table

[0038] 430#0~430#15H2F subtable

[0039] 510 Segments in physical page

[0040] 530 physical address information

[0041] 530-0 physical block number

[0042] 530-1 physical page number and its segment number

[0043] S610~S660 method steps

[0044] S710~S740 method steps

[0045] S810~S840 method steps DETAILED DESCRIPTION

[0046] The embodiments of the present invention will be described below with reference to the accompanying drawings. In these drawings, the same reference numerals represent the same or similar components or method flows.

[0047] It must be understood that the words "comprise", "include" and the like used in this specification are used to indicate the existence of specific technical features, values, method steps, work processes, elements and / or components, but do not exclude the addition of more technical features, values, method steps, work processes, elements, components, or any combination thereof.

[0048] The terms "first", "second", "third", etc. used in the present invention are used to modify the components in the claims and are not used to indicate a priority order, a precedence relationship, or that one component precedes another, or a temporal sequence in executing method steps. They are only used to distinguish components with the same name.

[0049] It should be understood that when a component is described as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component, and intervening components may be present. Conversely, when a component is described as being "directly connected" or "directly coupled" to another component, there are no intervening components. Other words used to describe the relationship between components should be interpreted in a similar manner, such as "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.

[0050] refer to Figure 1. The electronic device 10 includes: a host side (Host Side) 110, a flash memory controller 130 and a flash memory module 150, and the flash memory controller 130 and the flash memory module 150 can be collectively referred to as the device side (Device Side). The electronic device 10 can be implemented in electronic products such as personal computers, laptop computers (Laptop PC), tablet computers, mobile phones, digital cameras, digital video cameras, etc. The host side 110 and the host interface (Host Interface) 131 of the flash memory controller 130 can communicate with each other using communication protocols such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E), Universal Flash Storage (UFS), and Embedded Multi-Media Card (eMMC). The flash memory interface (Flash Interface) 139 of the flash memory controller 130 and the flash memory module 150 can communicate with each other using a double data rate (DDR) communication protocol, such as an open NAND flash interface (ONFI), a double data rate switch (DDR Toggle), or other communication protocols. The flash memory controller 130 includes a processing unit 134, which can be implemented in a variety of ways, such as using general-purpose hardware (e.g., a single processor, a multi-processor with parallel processing capabilities, a graphics processor, or other processor with computing capabilities), and provides the functions described below when executing software and / or firmware instructions. The processing unit 134 receives host commands, such as read commands, write commands, erase commands, etc., through the host interface 131, and schedules and executes these commands.Flash controller 130 also includes random access memory (RAM) 136, which can be implemented as dynamic random access memory (DRAM), static random access memory (SRAM), or a combination of the two. This RAM is used to configure space as a data buffer for storing user data (also referred to as host data) read from host 110 and to be written to flash memory module 150, as well as user data read from flash memory module 150 and to be output to host 110. RAM 136 can also store data required during execution, such as variables, data tables, host-to-flash (H2F) tables, and flash-to-host (F2H) tables. The flash memory interface 139 includes a NAND Flash Controller (NFC) that provides functions required for accessing the flash memory module 150 , such as a command serializer (CSerializer) and a low-density parity check (LDPC).

[0051] Flash memory controller 130 may be configured with a bus architecture 132 to couple components to each other for transmitting data, addresses, control signals, and the like. These components include a host interface 131, a processing unit 134, RAM 136, a direct memory access (DMA) controller 138, and a flash memory interface 139. In some embodiments, host interface 131, processing unit 134, RAM 136, DMA controller 138, and flash memory interface 139 may be coupled to each other via a single bus. In other embodiments, flash memory controller 130 may be configured with a high-speed bus to couple processing unit 134, DMA controller 138, and RAM 136, and a low-speed bus to couple processing unit 134, DMA controller 138, host interface 131, and flash memory interface 139. The DMA controller 138 can migrate data between components through the bus architecture 132 according to the instructions of the processing unit 134. For example, it can move data from a specific data buffer (DataBuffer) in the host interface 131 or the flash memory interface 139 to a specific address in the RAM 136, or move data from a specific address in the RAM 136 to a specific data buffer in the host interface 131 or the flash memory interface 139.

[0052] The bus consists of parallel physical lines that connect two or more components within flash controller 130. A bus is a shared transmission medium; at any given time, only two devices can communicate with each other using these lines to transfer data. Data and control signals can travel bidirectionally between components along the data and control lines, respectively, but address signals, on the other hand, can only travel in one direction along the address lines. For example, when processing unit 134 wants to read data at a specific address in RAM 136, processing unit 134 transmits this address to RAM 136 on the address line. The data at this address is then returned to processing unit 134 on the data line. To complete the data read operation, control signals are transmitted using the control lines.

[0053] Flash memory module 150 provides a large amount of storage space, typically hundreds of gigabytes (GB) or even multiple terabytes (TB), for storing large amounts of user data, such as high-resolution images and videos. Flash memory module 150 includes control circuitry and a memory array. The memory cells in the memory array can be configured as single-level cells (SLCs), multiple-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), or any combination thereof after erasure. Processing unit 134 writes user data to a specified address (destination address) in flash memory module 150 and reads user data from a specified address (source address) in flash memory module 150 via flash memory interface 139. Flash memory interface 139 coordinates the transfer of data and commands between flash memory controller 130 and flash memory module 150 using multiple electronic signals, including data lines, clock signals, and control signals. The data lines can be used to transmit commands, addresses, read and write data; the control signal lines can be used to transmit control signals such as chip enable (CE), address latch enable (ALE), command latch enable (CLE), and write enable (WE).

[0054] refer to Figure 2The interface 151 in the flash memory module 150 may include four input / output channels (I / O channels, hereinafter referred to as channels) CH#0 to CH#3, each of which connects to four NAND flash memory cells. For example, channel CH#0 connects to NAND flash memory cells 153#0, 153#4, 153#8, and 153#12, and so on. Each NAND flash memory cell may be packaged as an independent chip (die). The flash memory interface 139 may activate NAND flash memory cells 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15 by issuing one of the activation signals CE#0 to CE#3 via the interface 151, and then read user data from or write user data to the activated NAND flash memory cells in parallel.

[0055] Each NAND flash memory cell can contain multiple data planes, each data plane can contain multiple physical blocks, and each physical block can contain multiple physical pages. Figure 3 In the embodiment, NAND flash memory unit 153#0 includes two data planes 310 and 330. Data plane 310 includes physical blocks 310#0 to 310#m, and data plane 330 includes physical blocks 330#0 to 330#m. Each physical block includes n+1 physical pages. NAND flash memory units, physical blocks, and physical pages can be identified using logical unit numbers (LUNs), block numbers, and page numbers, respectively. Any combination of these numbers can be referred to as the physical address of flash memory module 150.

[0056] Each physical block can be categorized as a data block, a current block, or a system block based on its function. Processing unit 134 selects an empty physical block for each plane in each NAND flash memory cell as the current block, in preparation for writing user data received from host 110. To improve data writing efficiency, user data provided by host 110 can be written in parallel to specific pages in multiple current blocks across multiple planes in multiple NAND flash memory cells. Processing unit 134 maintains an F2H table for each current block in RAM 136, which contains multiple records storing, in page number order, the logical address associated with the user data on each page in the current block. Logical addresses can be represented using logical block addresses (LBAs), host page numbers, or other methods and are managed by host 110. For example, each logical block address is associated with 512B of user data, while each host page number is associated with 4KB of user data. After all pages in a current block are filled with user data, or after the remaining pages in a current block are filled with false values, the processing unit 134 can drive the flash memory interface 139 to write the corresponding F2H table in the RAM 136 to a specified page (e.g., the last page) of the current block, or to an empty page in another specified physical block. After the corresponding F2H table has been written to the flash memory module 150, the current block is changed to a data block. In other words, the user data stored therein will no longer be changed. The processing unit 134 can then select another empty physical block as the new current block. In addition, the processing unit 134 can set a specific physical block as a system block for storing management information, such as a flash identifier (ID), a bad block table (BBT), a bad column table (BCT), an H2F table, etc. The F2H table may be alternatively referred to as a Physical-to-Logical Address Mapping Table (P2L table), and the H2F table may be alternatively referred to as a Logical-to-Physical Address Mapping Table (L2P table).

[0057] In addition to writing the F2H table to the corresponding physical page in the flash memory module 150, the processing unit 134 also needs to update the H2F table based on the content of the F2H table of the current block, so that when executing a host read command in the future, it can quickly find out from the H2F table which physical address the user data associated with a specific logical address is actually stored. The H2F table contains multiple records, which store information on which physical address the user data of each logical address is actually stored in the order of the logical addresses. However, since the RAM 136 cannot provide enough space to store the entire H2F table for the processing unit 134 to quickly find it during future data read operations, the H2F table can be divided into multiple H2F sub-tables and stored in the flash memory module 150, so that in future data read operations, only the corresponding H2F sub-table needs to be read from the flash memory module 150 to the RAM 136. Reference Figure 4 , the entire H2F table can be divided into H2F sub-tables 430#0 to 430#15. The processing unit 134 further maintains a high-level reference table 410, which includes multiple records, and stores the physical address information of the H2F sub-table associated with each logical address segment in the order of the logical address. For example, the associated H2F sub-table 430#0 of the 0th to 4095th main pages is stored in the 0th physical page of a specific physical block of a specific LUN (the letter "Z" can represent the number of the LUN and the physical block), the associated H2F sub-table 430#1 of the 4096th to 8191th main pages is stored in the 1st physical page of a specific physical block of a specific LUN, and so on. Although Figure 4 The 16 H2F sub-tables are included, but those skilled in the art can set more H2F sub-tables according to the capacity of the flash memory module 150, and the present invention is not limited thereto.

[0058] The space required for each H2F subtable can be 4KB, 8KB, 16KB, 32KB, etc. Figure 5For example, H2F subtable 430#0 stores the physical location information corresponding to each logical location in the order of the logical addresses. Logical locations can be represented by main page numbers, and each main page number corresponds to a fixed-size physical storage space, such as 4KB. Those skilled in the art also use LBA to represent logical locations, but the present invention is not limited thereto. For example, H2F subtable 430#0 sequentially stores the physical address information from H#0 to H#4095. Physical address information 530 can be represented by four bytes: the first two bytes 530-0 record the physical block number; the second two bytes 530-1 record the physical page number and the segment number within the physical page. For example, the physical address information 530 corresponding to main page H#2 can point to physical page 510 in physical block 310#1. Byte 530-0 records the number of physical block 310#1, and byte 530-1 records the number of the physical page and the segment 510 within it.

[0059] After executing a host write command to write user data to the flash memory module 139, or executing a host discard command to discard data at a specific logical address stored in the flash memory module 139, the corresponding H2F subtable must be updated to enable efficient subsequent data read operations. Unlike when executing a host erase command, the processing unit 134 does not need to erase the storage unit originally storing the data at the specific logical address when executing a host discard command. In some system architectures, RAM 136 may be configured with sufficient space to temporarily store all H2F subtables. Whenever the processing unit 134 drives the flash memory interface 139 to write user data, or when data at a specific logical address stored in the flash memory module 139 is discarded, the corresponding H2F subtable content is updated to reflect the previous write or discard operation. At regular intervals or when default conditions are met, the processing unit 134 drives the flash memory interface 139 to write all H2F subtables in RAM 136 to a designated system block of the flash memory module 150. However, in some system architectures, RAM 136 lacks sufficient space to temporarily store all H2F subtables. Therefore, processing unit 134 must temporarily store F2H tables, which require significantly less space, in RAM 136. Once all pages in a current block are filled with user data, or after all remaining pages in a current block are filled with dummy values, processing unit 134 updates the corresponding H2F table based on the contents of the current block's F2H table. After a default number of host discard commands have been executed, processing unit 134 updates the corresponding H2F table to reflect the previous discard operations. Because previously executed host write and discard commands may involve multiple H2F subtables, processing unit 134 first searches the contents of high-level lookup table 410 to locate the physical addresses of the associated H2F subtables. It then drives flash memory interface 139 to read the associated H2F subtables from these physical addresses in flash memory module 150 and store them in RAM 136. Next, processing unit 134 updates the physical address information of the associated record of the H2F subtable in RAM 136 based on the contents of the current block's F2H table and the previously discarded logical address, and drives flash memory interface 139 to write the updated H2F subtable to the designated system block of flash memory module 150. However, in the above embodiment, when the host 110 performs a random write, the large number of H2F subtables that need to be updated delays the execution of subsequent host read commands and / or host write commands. Furthermore, subsequent host write commands may time out due to the prolonged waiting time for the H2F subtable update, causing the host 110 to expend time and computing resources to regenerate and transmit the host write command to the flash memory controller 130.

[0060] To address the issues described in the aforementioned embodiments, the present invention provides a method, computer-readable storage medium, and apparatus for updating a host-to-flash memory address table. These methods allocate space in RAM 136 for several H2F sub-tables, as well as intermediate information used to update other H2F sub-tables in flash memory module 150. In some embodiments, the system architecture may allocate sufficient space in RAM 136 to temporarily store the F2H table for the current block and a portion of the H2F sub-tables. In other embodiments, the system architecture may allocate sufficient space in RAM 136 to temporarily store the discard queue and a portion of the H2F sub-tables. In still other embodiments, the system architecture may allocate sufficient space in RAM 136 to temporarily store the F2H table for the current block, the discard queue, and a portion of the H2F sub-tables. The number of temporarily stored H2F sub-tables depends on the amount of space allocated in RAM 136. The temporarily stored H2F sub-tables and intermediate information in RAM 136 are updated when a host write command is executed to write data to flash memory module 150 or a host discard command is executed to discard data in flash memory module 150. In the Table Update Procedure, the H2F sub-table temporarily stored in RAM 136 (referred to as the first H2F sub-table) is written to a designated system block in flash memory module 150. The H2F sub-table in flash memory module 150 (referred to as the second H2F sub-table) is updated based on the intermediate information temporarily stored in RAM 136, and the updated H2F sub-table is written to the designated system block in flash memory module 150.

[0061] The embodiment of the present invention provides a method for executing a host write command, which is implemented by the processing unit 134 when loading and executing relevant firmware or software instructions. After each execution of the host write command, the method updates the H2F subtable temporarily stored in the RAM 136 and the F2H of the current block to store the latest comparison information between the logical and physical addresses and the update status of the H2F subtable. Figure 6 , the detailed steps are as follows:

[0062] Step S610: Execute the first (next) host write command. The processing unit 134 can drive the flash memory interface 139 to write the user data from the host 110 to the specified page of the current block in the flash memory module 150 according to the parameters of the host write command (including the logical address, length, etc.).

[0063] Step S620: Update the F2H table of the current block temporarily stored in the RAM 136 to store the comparison information of the written pages in the current block corresponding to the logical addresses.

[0064] Step S630: Determine whether the H2F sub-tables associated with these logical addresses are temporarily stored in the RAM 136. If yes, the process continues with the processing of step S640; otherwise, the process continues with the processing of step S660.

[0065] Step S640: Update the H2F sub-table temporarily stored in the RAM 136 to store the comparison information of which physical addresses these logical addresses correspond to.

[0066] Step S650: Set the update flag of the corresponding record in the F2H table temporarily stored in the RAM 136 to "1".

[0067] Step S660: Set the update flag of the corresponding record in the F2H table temporarily stored in the RAM 136 to "0".

[0068] The following examples illustrate that each record in the F2H table of the current block, in addition to storing the logical address information, also stores an update flag, which indicates whether the comparison information for this record has been updated to the H2F sub-table temporarily stored in RAM 136. "1" indicates updated, and "0" indicates not updated. Table 1 describes the example contents of the F2H table of the current block:

[0069] Table 1

[0070] Physical page number Logical address Update logo P#0 LBA#64~95 1 P#1 LBA#96~127 1 P#2 LBA#128~159 1 P#3 LBA#32000~32031 0 P#4 LBA#32032~32063 0 P#5 LBA#32064~32095 0

[0071] The first through third records indicate that pages P#0 through P#2 of the current block store user data at logical addresses LBA#64-95 (i.e., main page H#2), LBA#96-127 (i.e., main page H#3), and LBA#128-159 (i.e., main page H#3), respectively, and that their cross-reference information has been updated in the temporary H2F sub-table stored in RAM 136. The fourth through sixth records indicate that pages P#3 through P#5 of the current block store user data at logical addresses LBA#192000-192031 (i.e., main page H#6000), LBA#192032-192063 (i.e., main page H#6001), and LBA#192064-192095 (i.e., main page H#6002), respectively, and that their cross-reference information cannot be updated in the temporary H2F sub-table stored in RAM 136. The fourth through sixth records may be referred to as intermediate information for updating the corresponding H2F sub-table in flash memory module 150. In other words, H2F sub-table 430#1 associated with logical addresses LBA#192000-192031, LBA#192032-192063, and LBA#192064-192095 has not yet been read from flash memory module 150 and requires further table update procedures.

[0072] The embodiment of the present invention provides a method for executing a host discard command, which is implemented by the processing unit 134 when loading and executing relevant firmware or software instructions. After each execution of the host discard command, the method updates the H2F sub-table and discard queue temporarily stored in the RAM 136 to store the latest comparison information between logical and physical addresses and the update status of the H2F sub-table. Figure 7 , the detailed steps are as follows:

[0073] Step S710: Execute the first (next) host discard command. The processing unit 134 can extract the parameters of the host write command (including the logical address, length, etc.).

[0074] Step S720: Determine whether the H2F sub-tables associated with these logical addresses are temporarily stored in the RAM 136. If yes, the process continues with the processing of step S730; otherwise, the process continues with the processing of step S740.

[0075] Step S730: Update the H2F subtable temporarily stored in RAM 136 to delete the physical address mapping information corresponding to these logical addresses. Assuming the host discard command instructs to discard the user data from LBA#64 to LBA#127, processing unit 134 may fill the physical address fields associated with LBA#64 to LBA#127 (i.e., main pages H#2 to H#3) in the corresponding H2F subtable with dummy values, indicating that the user data from LBA#64 to LBA#127 does not exist in flash memory module 150.

[0076] Step S740: Push the logical addresses indicated by the host discard command into the discard queue, to indicate that the discard information of these logical addresses has not been updated into the corresponding H2F sub-table.

[0077] The following examples illustrate this, assuming that a host discard command instructs the discard of user data at logical addresses LBA#192032-192095 (i.e., main pages H#6001 to H#6002), and the H2F subtable associated with logical addresses LBA#192032-192095 is not temporarily stored in RAM 136. Since each physical page can store user data for 32 LBAs, logical addresses LBA#192032-192095 are split into logical addresses LBA#192032-192063 and LBA#192064-192095, and the split logical addresses are pushed into a discard queue. Table 2 describes the example contents of the discard queue:

[0078] Table 2

[0079] Node number Logical address N#0 LBA#192032~192063 N#1 LBA#192064~192095

[0080] The contents of the discard queue may be referred to as intermediate information for updating the corresponding H2F sub-table in the flash memory module 150 .

[0081] In general, the F2H table or discard queue for the current block stores information about whether the H2F sub-table associated with a specific logical address requires a table update. For example, each record in the F2H table for the current block with an update flag set to "0" stores information about whether the H2F sub-table associated with the specific logical address requires a table update. Each node in the discard queue stores information about whether the H2F sub-table associated with the specific logical address requires a table update.

[0082] The embodiment of the present invention provides a method for executing a table update program, which is implemented by the processing unit 134 when loading and executing related firmware or software instructions. Whenever the current block is full or a default condition is met, the table update program is executed to write the H2F sub-table temporarily stored in the RAM 136 to the flash memory module 150, and update the corresponding H2F sub-table in the flash memory module 150 based on the unupdated information of the H2F table of a specific logical address indicated in the F2H table and / or the discard queue. Figure 8 , the detailed steps are as follows:

[0083] Step S810: Write the H2F subtable temporarily stored in RAM 136 into the designated system block in flash memory module 150. Assume that H2F subtable 430 #0 is temporarily stored in RAM 136: Processing unit 134 drives flash memory interface 139 to write H2F subtable 430 #0 temporarily stored in RAM 136 into the designated system block in flash memory module 150.

[0084] Step S820: Based on the contents of the F2H table and discard queue for the current block temporarily stored in RAM 136, the H2F sub-table associated with the unupdated logical address is read from flash memory module 150 and stored in RAM 136. Continuing with the example of the F2H table for the current block described in Table 1 and the discard queue described in Table 2, the unupdated logical addresses are LBA#192000 to LBA#192031, and their associated H2F sub-table is 430#1. Processing unit 134 then drives flash memory interface 139 to read H2F sub-table 430#1 from the designated system block and store it in RAM 136.

[0085] Step S830: Update the newly read H2F sub-table (eg, H2F sub-table 430 # 1 ) in RAM 136 according to the F2H table of the current block temporarily stored in RAM 136 and the contents of the discard queue.

[0086] Step S840 : Writing the updated H2F sub-table in the RAM 136 to the designated system block in the flash memory module 150 .

[0087] The above method is applicable to system architectures where RAM 136 cannot allocate space for all H2F sub-tables, and by pre-storing a portion of H2F sub-tables in RAM 136 , the execution time of the table update procedure can be saved.

[0088] To make it easier for readers to understand, although the above embodiment uses one current block as an example to illustrate the operation details, those skilled in the art can apply it to a flash memory interface capable of writing multiple current blocks in parallel after appropriate modification, and the present invention is not limited thereto.

[0089] All or part of the steps in the method described in the present invention can be implemented by a computer program, such as a firmware translation layer (FTL) in a storage device, a driver for specific hardware, etc. In addition, it can also be implemented in other types of programs as shown above. A person skilled in the art can write the method of the embodiment of the present invention into program code, which will not be described again for the sake of simplicity. The computer program implemented according to the method of the embodiment of the present invention can be stored in an appropriate computer-readable storage medium, such as a DVD, CD-ROM, USB flash drive, hard disk, or can be placed on a network server that can be accessed through a network (e.g., the Internet, or other appropriate media).

[0090] Although Figure 1 、 Figure 2 The components described above are included in the invention, but it does not exclude the use of more additional components to achieve better technical effects without violating the spirit of the invention. Figures 6 to 8 The flowchart is executed in the specified order. However, those skilled in the art may modify the order of the steps without violating the spirit of the invention, provided that the same effect is achieved. Therefore, the present invention is not limited to the sequence described above. Furthermore, those skilled in the art may also combine several steps into one step, or perform more steps sequentially or in parallel in addition to the steps described above, and the present invention should not be limited thereby.

[0091] The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person skilled in the art may make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims of this application.

Claims

1. A method for updating a host and flash memory address comparison table, executed by a processing unit, characterized in that: The method for updating the host and flash memory address comparison table includes: Allocating space in the random access memory for the first host-to-flash memory address comparison subtable and for intermediate information used to update the second host-to-flash memory address comparison subtable in the flash memory module; When executing a host write command to write data to the flash memory module or executing a host discard command to discard data in the flash memory module, updating the first host and flash memory address comparison subtable and the intermediate information temporarily stored in the random access memory; and In the table update procedure, the first host and flash memory address comparison subtable temporarily stored in the random access memory is written into the system block in the flash memory module, the second host and flash memory address comparison subtable is updated according to the intermediate information temporarily stored in the random access memory, and the updated second host and flash memory address comparison subtable is written into the system block in the flash memory module.

2. The method for updating the host and flash memory address comparison table according to claim 1, wherein: The intermediate information is stored in a comparison table between the flash memory of the current block and the host address, and the method includes: When executing the host write command, updating the flash memory and host address comparison table of the current block temporarily stored in the random access memory to store comparison information of a plurality of write pages in the current block corresponding to a plurality of logical addresses, wherein the plurality of logical addresses include a first logical address associated with the first host and flash memory address comparison subtable and a second logical address associated with the second host and flash memory address comparison subtable; For the first logical address, updating the first host-to-flash memory address comparison subtable to store comparison information indicating which physical address the first logical address corresponds to, and setting a corresponding update flag in the flash memory-to-host address comparison table of the current block to a first value; and For the second logical address, a corresponding update flag in the flash memory and host address comparison table of the current block is set to a second value.

3. The method for updating the host and flash memory address comparison table according to claim 2, wherein: The update flag in the flash memory and host address comparison table of the current block is used to indicate whether the corresponding comparison information has been updated to the first host and flash memory address comparison sub-table.

4. The method for updating the host and flash memory address comparison table according to claim 2, wherein: include: In the table updating procedure, the second host-to-flash address comparison sub-table is updated according to comparison information associated with each update flag set to the second value in the flash-to-host address comparison table.

5. The method for updating the host and flash memory address comparison table according to claim 1, wherein the intermediate information is stored in a discard queue, The method for updating the host and flash memory address comparison table includes: When executing the host discard command, determining whether the logical address indicated by the host discard command is associated with the first host and flash memory address comparison subtable; When the logical address indicated by the host discard command is associated with the first host and flash memory address comparison sub-table, updating the first host and flash memory address comparison sub-table to store information that the user data at the logical address has been discarded; and When the logical address indicated by the host discard command is associated with the second host and flash memory address comparison subtable, the logical address is pushed into the discard queue, indicating that the user data of the logical address has been discarded and the second host and flash memory address comparison subtable needs to be updated.

6. The method for updating the host and flash memory address comparison table according to claim 5, wherein: include: In the table updating procedure, the second host and flash memory address comparison sub-table is updated according to the logical address in the discard queue.

7. A computer-readable storage medium for storing a computer program executable by a processing unit, characterized in that: When the computer program is executed by the processing unit, the method for updating the host and flash memory address comparison table according to any one of claims 1 to 6 is implemented.

8. A device for updating a host and flash memory address comparison table, characterized in that: include: Random Access Memory; A flash memory interface, coupled to the flash memory module; as well as A processing unit is coupled to the random access memory and the flash memory interface, and is used to configure space in the random access memory for a first host-to-flash memory address comparison subtable and for intermediate information used to update a second host-to-flash memory address comparison subtable in the flash memory module; when a host write command is executed to write data to the flash memory module or a host discard command is executed to discard data in the flash memory module, the first host-to-flash memory address comparison subtable and the intermediate information temporarily stored in the random access memory are updated; and in a table update procedure, the first host-to-flash memory address comparison subtable temporarily stored in the random access memory is written to a system block in the flash memory module, the second host-to-flash memory address comparison subtable is updated according to the intermediate information temporarily stored in the random access memory, and the updated second host-to-flash memory address comparison subtable is written to the system block in the flash memory module.

9. The device for updating the host and flash memory address comparison table according to claim 8, wherein: The intermediate information is stored in the flash memory of the current block and the host address comparison table. Wherein, when executing the host write command, the processing unit updates the flash memory and host address comparison table of the current block temporarily stored in the random access memory to store comparison information of multiple write pages in the current block corresponding to multiple logical addresses, wherein the multiple logical addresses include a first logical address associated with the first host and flash memory address comparison subtable and a second logical address associated with the second host and flash memory address comparison subtable; for the first logical address, the first host and flash memory address comparison subtable is updated to store comparison information of which physical address the first logical address corresponds to, and the corresponding update flag in the flash memory and host address comparison table of the current block is set to a first value; and for the second logical address, the corresponding update flag in the flash memory and host address comparison table of the current block is set to a second value.

10. The device for updating the host and flash memory address comparison table according to claim 9, wherein: The update flag in the flash memory and host address comparison table of the current block is used to indicate whether the corresponding comparison information has been updated to the first host and flash memory address comparison sub-table.

11. The device for updating the host and flash memory address comparison table according to claim 9, wherein: In the table updating procedure, the processing unit updates the second host-to-flash address comparison sub-table according to comparison information associated with each update flag set to the second value in the flash-to-host address comparison table.

12. The device for updating the host and flash memory address comparison table according to claim 8, wherein: The intermediate information is stored in a discard queue, When executing the host discard command, the processing unit determines whether the logical address indicated by the host discard command is associated with the first host and flash memory address comparison subtable; when the logical address indicated by the host discard command is associated with the first host and flash memory address comparison subtable, the first host and flash memory address comparison subtable is updated to store information that the user data of the logical address has been discarded; and when the logical address indicated by the host discard command is associated with the second host and flash memory address comparison subtable, the logical address is pushed into the discard queue, indicating that the information that the user data of the logical address has been discarded needs to be updated to the second host and flash memory address comparison subtable.

13. The device for updating the host and flash memory address comparison table according to claim 12, wherein: The processing unit updates the second host and flash memory address comparison sub-table according to the logical address in the discard queue in the table update procedure.

Images