Memristor-based storage-computing integrated system and online deep learning method

Abstract

The application discloses a storage and calculation integrated system based on a memristor and an online deep learning method, and belongs to the field of information storage, and comprises a storage module and a controller; the storage module comprises a plurality of tiles, each tile comprises a plurality of PEs, and each PE comprises one or more arrays of memristors; the controller is used for executing an inter-array wear leveling strategy based on a mapping table, and the method comprises the following steps: dividing every M times of writing into a wear leveling period; maintaining a total number of times of writing TWC and a number of times of writing in the wear leveling period IWC for each PE; cyclically executing the following steps: setting IWC of each PE to 0; accumulating the number of times of writing in the array in the PE in the running stage to IWC until the current wear leveling period ends; accumulating IWC of each PE to corresponding TWC; reconstructing the mapping table so that the larger IWC is, the smaller TWC corresponding to the physical ID mapped by the corresponding logical ID is; and performing data exchange. The application can improve the effect of wear leveling in the storage and calculation integrated system based on the memristor, thereby improving the overall service life of the system.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of information storage, and more particularly relates to a memristor-based storage-computing integrated system and an online deep learning method. BACKGROUND

[0002] With the advent of the big data era, the demand for the computing speed, power consumption and other aspects of the traditional computing system is increasing, and the von Neumann problem has become an important bottleneck restricting the further development of the current computer system. Since the proposal of the memristor, it has become one of the promising development objects of the next generation of semiconductor memories due to its non-volatility, high integration and low power consumption. The computing and storage fusion characteristics of the memristor also become a powerful basis for building a new storage-computing integrated architecture. Due to its high density and high energy efficiency, the storage-computing integrated architecture based on the memristor has shown great potential in the application of deep neural network acceleration.

[0003] Figure 1 The figure shows a classical memristor-based storage-computing integrated neural network accelerator architecture, which adopts a 3-layer architecture design (Tile / PE / Crossbar). The storage structure contains multiple Tiles, each Tile further contains multiple PEs, and each PE contains multiple memristor arrays. The memristor units in the memristor array are often organized in the form of cross-point arrays.

[0004] In the large-scale streaming data scenario represented by online deep learning, frequent writing to the memristor array will cause great challenges to the limited life of the memristor array. In addition, the uneven writing will cause the life of the memristor-based storage-computing integrated system to drop sharply, and the "short board effect" will be highlighted. In the large-scale streaming data scenario, the problem of uneven writing is more prominent.

[0005] In order to solve the influence of uneven writing on the life of the memristor, researchers have proposed corresponding wear leveling strategies, the overall idea of which is to distribute the writing as evenly as possible to different units. Figure 2 The figure shows the execution schematic diagram of the existing three array-level wear leveling strategies. (a) is the column shift (CS) scheme, which specifically realizes wear leveling by cyclically shifting all columns in the array; (b) is the row swap (RS) scheme, which specifically realizes wear leveling by swapping rows in the matrix; (c) is the row column swap (RCS) scheme, which specifically realizes wear leveling by swapping rows and columns in the array. These wear leveling strategies can prolong the life of the array to some extent, but the existing wear leveling strategies are performed in the array and cannot perform wear leveling at the system level, so the life prolonging effect is very limited. SUMMARY

[0006] In view of the defects of the prior art and the improvement needs, the present application provides a memristor-based storage-computing integrated system and an online deep learning method, which aims to improve the wear leveling effect in the memristor-based storage-computing integrated system, so as to improve the overall life of the system.

[0007] To achieve the above-mentioned purpose, according to one aspect of the present application, a memristor-based storage-computing integrated system is provided, comprising: a storage module and a controller.

[0008] The storage module comprises a plurality of interconnected Tiles, each Tile comprising a plurality of interconnected PEs, each PE comprising N memristor arrays; the mapping relationship of the logical ID to the physical ID of each PE is recorded in a mapping table; N is a positive integer, and N≥1;

[0009] The controller is used to execute an inter-array wear leveling strategy based on the mapping table, comprising:

[0010] Each M times of writing is divided into a wear leveling period, M being a preset positive integer; metadata TWC and IWC are maintained for each PE, respectively used to record the total number of times of writing of the PE and the number of times of writing in the current wear leveling period; the following steps are executed in each wear leveling period:

[0011] (S1) setting the IWC of each PE to 0;

[0012] (S2) accumulating the number of times of writing of the memristor arrays in the PE in the running phase to the corresponding IWC until the end of the current wear leveling period;

[0013] (S3) accumulating the IWC of each PE to the corresponding TWC;

[0014] (S4) reconstructing the mapping table so that the larger the IWC is, the smaller the TWC corresponding to the physical ID mapped by the corresponding logical ID is;

[0015] (S5) exchanging the data stored in the PE based on the current mapping table.

[0016] Further, N=1.

[0017] Further, the IWC of each PE is stored in a register inside the memristor array thereof.

[0018] Further, the plurality of Tiles in the storage module are interconnected through Torus routing.

[0019] Further, one or more memristor arrays in the storage module are divided into a dedicated metadata storage area.

[0020] And the TWC of each PE is stored in the metadata storage area.

[0021] According to another aspect of the present application, there is provided an online deep learning method based on the memristor-based memory-compute integrated system provided by the present application, wherein the memristor-based memory-compute integrated system is used to accelerate the online deep learning.

[0022] The online deep learning method comprises:

[0023] In the back propagation process, if the contribution rate α k of any kth hidden layer is less than a preset threshold ε, and the number of data instances that have been separated since the last update of the weight W k of the hidden layer is less than a preset value γ, then the weight W k of the hidden layer is not updated; otherwise, the weight W k of the hidden layer is updated.

[0024] Further, the online deep learning method provided by the present application further comprises that the updating of the hidden layer weight is performed simultaneously with step (S5).

[0025] Further, γ = 2.

[0026] Further, the memristor-based memory-compute integrated system further comprises an auxiliary computing unit for performing vector operations.

[0027] And in the process of back propagation of the online deep learning method, the calculation of the weight gradient is completed by the auxiliary computing unit.

[0028] Further, the memristor-based memory-compute integrated system further comprises a global cache.

[0029] And in the process of back propagation of the online deep learning method, the intermediate data required for the calculation of the weight gradient is stored in the global cache.

[0030] Overall, the above technical solutions conceived by the present application can achieve the following beneficial effects:

[0031] (1) The memory and calculation integrated system based on the memristor provided by the application adopts an inter-array wear leveling strategy based on a mapping table, metadata TWC and IWC are maintained for each PE, TWC is used to record the total number of write times of the PE, and reflects the total wear degree of the array in the whole life cycle, IWC is used to record the number of write times in the current wear leveling period, and reflects the short-term write heat of the array; at the end of each wear leveling period, the mapping table is rebuilt, so that the larger the IWC is, the smaller the TWC corresponding to the physical ID mapped by the corresponding logical ID is, thereby the "hot" logical array is remapped to the physical array with less wear, and the wear leveling between arrays is realized. Compared with the existing intra-array wear leveling method, the effect of wear leveling can be improved, and the overall life of the system can be improved.

[0032] The inter-array wear leveling strategy based on the mapping table is orthogonal to the existing intra-array wear leveling strategy, and can be used in combination with the existing intra-array wear leveling strategy to realize intra-array wear leveling on the basis of inter-array wear leveling, and further improve the wear leveling effect.

[0033] In addition, the inter-array wear leveling strategy based on the mapping table may distribute the physical arrays belonging to a logical matrix in multiple Tiles after rebuilding the mapping table, so as to disperse the calculation task to multiple Tiles and relieve the bandwidth contention in the Tile.

[0034] (2) In the preferred scheme of the memory and calculation integrated system based on the memristor provided by the application, each PE only contains a single memristor array, which is equivalent to removing the PE level in the original three-level (Tile / PE / Crossbar) architecture, and simplifying the system architecture from the three-level (Tile / PE / Crossbar) architecture to the two-level (Tile / Crossbar) architecture, thereby reducing unnecessary communication overhead, speeding up the calculation, and further improving the overall performance of the system.

[0035] (3) In the application, IWC is temporary metadata and is frequently updated, and in the preferred scheme of the application, IWC is stored in the register inside the memristor array under the two-level architecture, avoiding frequent write to the memristor array due to IWC update.

[0036] (4) In the preferred scheme of the application, under the two-level architecture, the plurality of Tiles in the storage module are interconnected through Torus routing, which can further reduce the communication overhead.

[0037] (5) In the application, TWC is an important metadata that records the total number of cell writes in the life cycle of the memristor array, and in the preferred embodiment of the application, the metadata TWC of each PE is stored in a dedicated memristor array, realizing non-volatile storage of the metadata TWC and ensuring the storage security of the metadata TWC.

[0038] (6) The online deep learning method provided by the application realizes a deep learning network by using the memristor-based storage-computing integrated system provided by the application, updates only the weights of the hidden layers with a relatively high contribution rate in the back propagation process, does not update the weights of the non-key hidden layers, and forces the update of the weights of the hidden layers every gamma data instances, thereby effectively reducing the number of updates of the weights of the hidden layers, reducing the writing of the array in the storage-computing integrated system, reducing energy consumption and prolonging the service life of the system while ensuring the deep learning effect.

[0039] (7) In the preferred embodiment of the online deep learning method provided by the application, the weights of the hidden layers are updated while performing the data exchange operation in the inter-array wear leveling strategy based on the mapping table, and since the data exchange is hidden in the weight update, the application reduces the additional writing introduced by the data exchange by overlapping the data exchange and the weight update.

[0040] (8) In the preferred embodiment of the online deep learning method provided by the application, the number of data instances that force the weight update is specifically set to gamma = 2, which can achieve the maximum balance between the deep learning effect and the improvement of the service life of the memristor array.

[0041] (9) The data relied on by online deep learning is large-scale streaming data, and in the back propagation process, the matrix operation of gradient calculation will degenerate into vector operation, and in the preferred embodiment of the application, the calculation of the weight gradient is transferred from the memristor array to the auxiliary computing unit, which can reduce the writing of the memristor array, reduce energy consumption, improve the service life, and avoid wasting space.

[0042] (10) In deep learning, the calculation of the weight gradient needs intermediate data as input, and in online deep learning, the storage demand of the intermediate data is small, and in the preferred embodiment of the application, the storage location of the intermediate data required for the calculation of the weight gradient is transferred from the memristor array to the global cache, which can avoid space waste. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 The existing architecture diagram of the memristor-based storage-computing integrated system;

[0044] Figure 2Schematic diagram of execution of the existing three intra-array wear leveling strategies; wherein (a) is a column shift (CS) scheme, (b) is a row swap (RS) scheme, and (c) is a row column swap (RCS) scheme;

[0045] Figure 3 Schematic diagram of a storage-computing integrated system based on a memristor provided by an embodiment of the present application;

[0046] Figure 4 Flowchart of an inter-array wear leveling strategy based on a mapping table provided by an embodiment of the present application;

[0047] Figure 5 Schematic diagram of an inter-array wear leveling strategy based on a mapping table provided by an embodiment of the present application;

[0048] Figure 6 Schematic diagram of an existing HBP online deep learning network structure; wherein (a) is a forward propagation process, and (b) is a backward propagation process. DETAILED DESCRIPTION

[0049] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application. In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as they do not conflict with each other.

[0050] In the present application, the terms "first", "second", etc. (if any) in the present application and the accompanying drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0051] In order to solve the technical problem that the existing intra-array wear leveling method for a storage-computing integrated system based on a memristor is not good for improving the overall life of the system, the present application provides a storage-computing integrated system based on a memristor, the overall idea of which is to improve the wear leveling algorithm, periodically remap the "hot" logical array to a physical array with less wear to achieve inter-array wear leveling, and ultimately improve the overall life of the system. On this basis, an online deep learning method is proposed, the overall idea of which is to reduce the write to the memristor array without affecting the online deep learning effect, to solve the defects of frequent weight update writing and unbalanced writing in online deep learning in the storage-computing integrated system based on a memristor, which leads to low system life.

[0052] The following are embodiments.

[0053] Embodiment 1:

[0054] A memristor-based storage-computing integrated system, as shown in Figure 3 includes a storage module and a controller.

[0055] The storage module includes a plurality of interconnected Tiles, each Tile including a plurality of interconnected PEs, each PE containing N memristor arrays; the mapping relationship of the logical ID to the physical ID of each PE is recorded in a mapping table; the logical ID is a virtual reference assigned by the system to the upper layer application for accessing the physical array, and the physical ID uniquely represents the PE in the storage-computing integrated system.

[0056] As shown in Figure 3 In this embodiment, each PE contains only a single memristor array, i.e., N = 1. Therefore, the memristor-based storage-computing integrated system provided in this embodiment is equivalent to removing the PE level in the original three-level (Tile / PE / Crossbar) architecture, simplifying the system architecture from the traditional three-level (Tile / PE / Crossbar) hierarchical architecture to a two-level (Tile / Crossbar) hierarchical architecture, thereby reducing unnecessary communication overhead and speeding up the calculation. Moreover, in order to further reduce the communication overhead, in this embodiment, the plurality of Tiles are interconnected through a Torus routing, and it should be noted that the interconnection mode of the Tiles herein is only a preferred embodiment and should not be understood as the only limitation of the present application. Other interconnection modes, such as Mesh, can also be used in the present application.

[0057] As shown in Figure 3 In this embodiment, each Tile is composed of a plurality of memristor arrays and a tile-level input / output buffer, and is interconnected through an H-Tree.

[0058] As shown in Figure 3 The memristor units in each memristor array are connected in the form of a Crossbar, i.e., a cross-point array; optionally, in this embodiment, in order to reduce the influence of write disturbance and sneak current, the memristor units in the memristor array are 1T1R units.

[0059] In this embodiment, the controller is used to execute a table-based inter-crossbar wear-leveling (TIWL) strategy based on the mapping table; the strategy includes:

[0060] Each M times of writing is divided into a wear leveling period, M is a preset positive integer, which can be determined according to actual needs; metadata TWC and IWC are maintained for each PE, which are used to record the total number of write times of the PE and the number of write times in the current wear leveling period; since each PE in the embodiment contains only one memristor array, the maintained TWC and IWC are the TWC and IWC of each memristor array;

[0061] As shown in Figure 4 and Figure 5 , the TIWL performs the following steps in each wear leveling period:

[0062] (S1) setting the IWC of each PE to 0;

[0063] (S2) accumulating the number of write times of the memristor array in the PE in the running stage to the corresponding IWC until the end of the current wear leveling period;

[0064] (S3) accumulating the IWC of each PE to the corresponding TWC;

[0065] (S4) reconstructing the mapping table so that the larger the IWC, the smaller the TWC corresponding to the physical ID mapped by the corresponding logical ID;

[0066] Similarly, each PE contains only one memristor array, and the logical ID and physical ID of the PE are the logical ID and physical ID of the memristor array;

[0067] The IWC reflects the short-term write heat of the memristor array, and the TWC reflects the total wear degree of the memristor array in the life cycle. The embodiment realizes system-level wear leveling, i.e. inter-array wear leveling, by reconstructing the mapping table to remap the "hot" logical array to a physical array with less wear, which has better wear leveling effect than the existing intra-array wear leveling and can effectively prolong the overall life of the system;

[0068] (S5) exchanging the data stored in the PE based on the current mapping table;

[0069] In the process of reconstructing the mapping table, the mapping relationship between the logical ID and the physical ID may change. For the physical ID whose mapping relationship has changed, the data stored in the corresponding memristor array needs to be exchanged to ensure the correctness of the mapping relationship.

[0070] The IWC is temporary metadata and is frequently updated. In order to avoid frequent writing to the memristor array due to IWC updating, as a preferred embodiment, the IWC is recorded in the register inside each memristor array, i.e. Figure 3The "wear counter" in the "wear counter"; TWC is important metadata, which records the total number of cell writes in the life cycle of the memristor array, and needs non-volatile storage medium to store. In order to ensure the storage security of TWC, one or more memristor arrays in the storage module are divided into a dedicated metadata storage area in the embodiment;

[0071] And the TWC of each PE is stored in the metadata storage area.

[0072] Compared with the intra-array wear leveling method, TIWL does not need to record the aging state of each word line or bit line, nor does it need to obtain the temperature of the cell. Therefore, the storage and calculation overheads are reduced. The related overheads are briefly analyzed as follows:

[0073] Assuming that IWC and TWC are 32-bit and 64-bit respectively, a 128x128 array is used to build a 4GB memristor-based in-memory computing system, and the wear metadata occupies 24MB (0.59% of 4GB), and the mapping table occupies 16MB (0.15% of 4GB), and the storage overhead is within an acceptable range; when the array size increases to 512x512, the storage of wear metadata and mapping table decreases to 1.14MB (0.03% of 4GB) and 1.5MB (0.04% of 4GB) respectively; the metadata of the array is fixed to 96-bit, which is much smaller than the existing intra-array wear leveling strategy - row exchange strategy (N x T, where N represents the number of rows, and T is the bit width of the register).

[0074] Overall, the memristor-based in-memory computing system provided by the embodiment adopts the mapping table-based inter-array wear leveling strategy (TIWL), which can remap the "hot" logical array to a physical array with less wear, achieving inter-array wear leveling. Compared with the existing intra-array wear leveling method, it can improve the effect of wear leveling and ultimately improve the overall life of the system. In addition, the mapping table-based inter-array wear leveling strategy provided by the embodiment is orthogonal to the existing intra-array wear leveling strategy, which can be used in combination with the existing intra-array wear leveling strategy to achieve intra-array wear leveling on the basis of inter-array wear leveling, further improving the wear leveling effect. Moreover, the mapping table-based inter-array wear leveling strategy may distribute the physical arrays belonging to the same logical matrix in multiple Tiles after rebuilding the mapping table, thereby dispersing the computing task to multiple Tiles and relieving the bandwidth contention within the Tile.

[0075] It should be noted that the array wear leveling strategy based on the mapping table (TIWL) provided in the embodiment can improve the wear leveling effect, and at the same time, due to the dispersion of the calculation task to multiple Tiles, additional communication overhead is introduced, but the communication overhead is within an acceptable range. Moreover, the embodiment can effectively alleviate the communication overhead caused by TIWL through optimization of the system architecture and the Tile interconnection mode. Overall, for improving the overall lifetime of the memristor-based memory-compute integration system, the embodiment can obtain greater benefits with a small amount of overhead.

[0076] It is easy to understand that the above two-level (Tile / Crossbar) hierarchical architecture is only a preferred embodiment of the present application and should not be understood as the only limitation of the present application. TIWL can achieve a balance between mapping overhead and mapping benefit by adjusting the scheduling granularity (i.e., PE size). When the number of memristor arrays contained in the PE is greater than 1, the implementation of TIWL in the memory-compute integration architecture is similar to the above process, except that after determining the mapping relationship between the logical ID and the physical ID of the PE in the remapping table, the logical ID to physical ID remapping of the memristor array is also needed according to the order of the memristor array inside the PE; in addition, the metadata IWC of the PE is shared by multiple memristor arrays therein and needs to be stored in the register corresponding to the PE.

[0077] It is also easy to understand that in the embodiment, the implementation of TIWL does not depend on the specific structure inside the Tile, and when the Tile internal structure changes, for example, the memristor unit changes, the overall lifetime of the memristor-based memory-compute integration system provided by the present application can still be effectively improved.

[0078] Embodiment 2:

[0079] An online deep learning method based on the memristor-based memory-compute integration system provided in the above embodiment 1, wherein the memristor-based memory-compute integration system is used to accelerate online deep learning.

[0080] Before explaining the technical solutions of the embodiment in detail, the existing online deep learning method is briefly introduced as follows:

[0081] Online deep learning can learn from streaming data, keep the model continuously trained and evolved, and can better learn in the streaming data scene than offline batch training. Figure 6The classical HBP online deep learning network structure is shown in the figure, where (a) is the forward propagation process, and (b) is the backward propagation process. The online deep learning network structure consists of two parts: one part is the hidden layer h, which is propagated from the first layer to the last layer like the traditional offline learning deep neural network; the other part is the output layer o, each output layer is connected with a Softmax classifier, which is used to evaluate the learning situation of the current hidden layer. In the figure, α n represents the contribution weight ratio of the nth layer in all hidden layers, o k represents the Softmax output of the kth layer classifier output layer, h k represents the output of the kth layer hidden layer after activation.

[0082] Assuming that the number of hidden layers of a deep neural network is N, the final output of the online deep learning HBP model can be represented by the following formula:

[0083] where

[0084]

[0085]

[0086] h0=x

[0087] The parameters that need to be learned by the HBP model are three, which are Θ k , W k and α k .

[0088] where Θ k represents the parameter weight of the kth layer output layer, W k represents the parameter weight of the kth layer hidden layer, and α k controls the contribution weight ratio of each layer to the output. The final output result is obtained after the weighted sum of the classifier output of each layer. The loss function of the model can be defined as: that is, the weighted sum of the loss function of each layer classifier.

[0089] The contribution weight ratio α k of each layer is initialized as a uniform distribution: In each iteration process, the output of each layer classifier is o k , and the contribution weight ratio α k of each layer is updated by the following formula after the loss function calculation with the real result: where t represents the iteration round, β ∈ (0, 1) is the decay coefficient, and the contribution weight ratio α (l)Decay after each iteration according to the loss function After all the contribution weights are updated, they are normalized to make them conform to

[0090] For the output layer weights Θ k , the weights are updated by the online gradient descent method, which is the same as the traditional offline learning. The update process of the weights Θ k is as follows:

[0091]

[0092] For the update of the hidden layer weights W k , unlike the traditional backpropagation method, the error partial derivative is obtained by backpropagation from all output layers (i.e., each classifier o k ), so the update process is represented by the following formula:

[0093]

[0094] where is obtained by backpropagation of the error from each classifier. It should be noted that the weight update of the k-th hidden layer requires the weighted accumulation of the error partial derivatives of all subsequent hidden layers .

[0095] Since the HBP optimization method reduces the weight proportion α k of the deep network to a very small value, in order to limit its impact on learning, a smoothing parameter s (s ∈ (0, 1)) is used to control the update of α k . After each weight update, it is modified as follows: to prevent the deep network from participating in the backpropagation process.

[0096] Online deep learning involves a large number of matrix operations, and memristor arrays can accelerate matrix-vector multiplication operations. Since deep learning applications involve a large number of matrix-vector multiplication operations, they can be accelerated using memristor arrays. Specifically, the network weights W are stored in the array, the array input is a vector, and the array output is the calculation result.

[0097] Currently, there are still challenges in using memristor-based storage-computing integrated systems to accelerate online deep learning. First, online deep learning on large-scale streaming data requires a much larger number of weight updates (usually more than a million) than traditional offline batch training, which will cause frequent writing to the memristor array, posing a huge challenge to the limited lifespan of the memristor array. Second, the uneven writing of the array during weight update will cause a sharp decline in system lifespan, highlighting the "short board effect", and the large-scale continuous training in the online deep learning scenario will make the problem of uneven writing more prominent.

[0098] The online deep learning method provided in this embodiment implements a deep learning network by using the storage-computing integrated system based on the memristor provided in Embodiment 1. Since the storage-computing integrated system adopts the array wear leveling strategy based on the mapping table, the influence of weight update of the online deep learning method on the system life can be alleviated in the case of unbalanced array writing caused by weight update, and the effective implementation of the online deep learning method is ensured.

[0099] Considering that the contribution rate α of the shallow network gradually decreases and the contribution rate of the deep network gradually increases as the training data is input, the training of the HBP and other online deep learning networks starts from the shallow neurons, and then gradually trains the neurons of the deep network. The final result of the network is obtained by weighted summation of the classifiers of all layers according to the contribution rate α, and the network layer with low α has less influence on the output of the network. Based on this consideration, the weight update mode in the back propagation process of the online deep learning method is improved in this embodiment, and a write-optimized weight update strategy (WARP) is proposed. The strategy dynamically controls the weight update of the hidden layer according to the weight proportion of the network layer, avoids unnecessary weight writing, and reduces array wear.

[0100] More specifically, if the α of the kth hidden layer is less than the threshold value ε (a constant set, preferably 1 / N) at each training iteration k , the contribution of this layer to the final output result of the network is also less, so the update of the weight W k of this hidden layer is reduced. At the same time, considering that if the hidden layer weight is not updated continuously, the network will converge too slowly, in order to control the degree of reducing weight update, the hidden layer weight is forced to update every γ data instances. The weight update process can be expressed as follows:

[0101]

[0102] Based on the above weight update mode, the number of hidden layer weight updates is effectively reduced in this embodiment to ensure the deep learning effect, thereby reducing the writing of the array in the storage-computing integrated system, reducing energy consumption and prolonging the system life. As a preferred embodiment, in this embodiment, γ = 2. Experiments show that such setting of the number of data instances separated by forced weight update can achieve the maximum balance between the deep learning effect and the life improvement effect of the memristor array.

[0103] As a preferred embodiment, the updating of the hidden layer weights is performed simultaneously with step (S5), i.e., in the memristor-based computing and storage integrated system, the data exchange operation in the TIWL is hidden in the weight updating, and the embodiment reduces the additional writing introduced by the data exchange by overlapping the data exchange and the weight updating, thereby further reducing the energy consumption and improving the system life.

[0104] In the online deep learning method, the calculation of the weight gradient requires the intermediate data x as input: Therefore, the forward stage needs to store x. In the existing memristor-based computing and storage integrated system, the main calculation and storage in the online deep learning method are completed by the memristor array, and the calculation of the weight gradient using the memristor will have two problems: (1) Frequent rewriting of the memristor array will introduce energy consumption and shorten the life, and in online deep learning based on large-scale streaming data, the matrix operation of gradient calculation will degenerate into vector operation, and directly using the memristor array to store the vector data will also cause the waste of the space of the memristor array. (2) Storing the banded intermediate data in the memristor array will waste space and exacerbate the wear imbalance. The intermediate data storage in online deep learning is smaller than that in offline batch training, for example, for training a 16-layer network (hidden layer size is 100) using HBP, only about 9 KB of intermediate data needs to be stored.

[0105] Therefore, as shown in Figure 3 , in the embodiment, an auxiliary compute unit (ACU) is further arranged in the memristor-based computing and storage integrated system for performing vector operations, and in the embodiment, the calculation of the weight gradient in the online deep learning method is completed by the auxiliary compute unit during the backpropagation process. By transferring the calculation of the weight gradient from the memristor array to the auxiliary compute unit, the writing of the memristor array can be reduced, the energy consumption can be reduced and the life can be improved, and the space can be avoided from being wasted. Based on the same consideration, as an optional embodiment, in the embodiment, the auxiliary compute unit is also used to complete the processing of array results from different tiles, including ReLU activation, pooling, and cumulative summation, etc.

[0106] In addition, in the embodiment, a global cache is further arranged in the memristor-based computing and storage integrated system, as shown in Figure 3 , and in the embodiment, the intermediate data required for the calculation of the weight gradient is stored in the global cache. By transferring the storage location of the intermediate data from the memristor array to the global cache, the embodiment can avoid the waste of space.

[0107] Overall, the embodiment based on the above-mentioned embodiment 1 provides an online deep learning method based on the memory resistor-based storage-computing integrated system, and through further improvement, the defects of frequent weight update writing and unbalanced writing leading to low system life of online deep learning in the memory resistor-based storage-computing integrated architecture can be overcome.

[0108] Those skilled in the art can easily understand that the above description is only the preferred embodiment of the present application, and is not intended to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A memristor-based in-memory computing system, comprising: Comprising: a storage module and a controller; the storage module comprises a plurality of interconnected Tiles, each Tile comprising a plurality of interconnected PEs, each PE containing N arrays of memristors; the mapping relationship of logical ID to physical ID of each PE is recorded in a mapping table; N is a positive integer, and N≥1; one or more arrays of memristors in the storage module are divided into a dedicated metadata storage area; the controller is configured to execute an inter-array wear leveling strategy based on the mapping table, comprising: dividing each M times of writing into a wear leveling period, M being a preset positive integer; maintaining metadata TWC and IWC for each PE, respectively used to record the total number of times of writing of the PE and the number of times of writing in the current wear leveling period; the TWC of each PE is stored in the metadata storage area; in each wear leveling period, the following steps are executed: (S1) setting the IWC of each PE to 0; (S2) accumulating the number of times of writing of the arrays of memristors in the PE in the running phase to the corresponding IWC until the end of the current wear leveling period; (S3) accumulating the IWC of each PE to the corresponding TWC; (S4) reconstructing the mapping table so that the larger the IWC, the smaller the TWC corresponding to the physical ID mapped by the corresponding logical ID; (S5) exchanging the data stored in the PE based on the current mapping table.

2. The memristor-based in-memory computing system of claim 1, wherein, N=1。 3. The memristor-based in-memory computing system of claim 2, wherein, The IWC of each PE is stored in a register inside the array of memristors thereof.

4. The memristor-based in-memory computing system of claim 2, wherein, The plurality of Tiles in the storage module are interconnected through Torus routing.

5. An online deep learning method based on the memristor-based computing-in-memory system according to any one of claims 1-4. The memristor-based storage-computing integrated system is used to accelerate online deep learning; the online deep learning method comprises: During the back propagation process, if the contribution rate of any hidden layer is less than a preset threshold, and the number of data instances since the last update of the weights of the hidden layer is less than a preset value, the weights of the hidden layer are not updated; otherwise, the weights of the hidden layer are updated. k ​​​​​​​ 6. The online deep learning method of claim 5, wherein, Further comprising: the updating of the hidden layer weights is performed simultaneously with the step (S5).

7. The online deep learning method of claim 5, wherein, 。 8. The online deep learning method of any one of claims 5-7, wherein, The memristor-based storage-computing integrated system further comprises an auxiliary computing unit for performing vector operations; and in the process of back propagation, the calculation of weight gradient is completed by the auxiliary computing unit.

9. The online deep learning method of claim 8, wherein, The memristor-based storage-computing integrated system further comprises a global cache; and in the process of back propagation, the intermediate data required for weight gradient calculation is stored in the global cache.

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