Data writing method, memory storage device, and memory control circuit unit

Abstract

The present application provides a data writing method, a memory storage device and a memory control circuit unit. The method comprises: receiving a write instruction from a host system, which indicates storing first data belonging to a first logical unit; in response to the first data being first type data, storing the first data to a first type physical unit according to the write instruction and updating first count information corresponding to a first logical range, wherein the first logical unit belongs to the first logical range; and in response to the first count information meeting a preset condition, moving the first data from the first type physical unit to a second type physical unit. Thus, the writing efficiency and continuity of data can be considered.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory management technique, and more particularly, to a data writing method, a memory storage device, and a memory control circuit unit. BACKGROUND

[0002] Smartphones, tablet computers, and personal computers have grown rapidly in recent years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memories) are very suitable for being built into various portable multimedia devices exemplified above due to their data non-volatility, power saving, small size, and lack of mechanical structure.

[0003] Some types of memory storage devices support a data shunting mechanism to write single-pen data with different data amounts to corresponding memory blocks. For example, data with an amount less than a preset data amount is written to a small data block, and data with an amount not less than the preset data amount is written to a large data block. Although this data shunting mechanism can improve the data writing efficiency, it can also easily lead to continuous data being stored in non-continuous physical addresses, thereby causing subsequent management troubles. SUMMARY

[0004] The present application provides a data writing method, a memory storage device, and a memory control circuit unit, which can take into account both data writing efficiency and writing continuity.

[0005] An exemplary embodiment of the present application provides a data writing method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units. The data writing method includes: receiving a write instruction from a host system, wherein the write instruction indicates to store first data belonging to a first logical unit; in response to the first data being first type data, storing the first data to a first type physical unit of the plurality of physical units and updating first count information corresponding to a first logical range according to the write instruction, wherein the first logical unit belongs to the first logical range; and in response to the first count information meeting a preset condition, moving the first data from the first type physical unit to a second type physical unit of the plurality of physical units.

[0006] An exemplary embodiment of the present disclosure further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is configured to connect to a host system. The rewritable non-volatile memory module includes a plurality of physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to: receive a write instruction from the host system, wherein the write instruction indicates storing first data belonging to a first logical unit; in response to the first data belonging to a first type of data, store the first data to a first type of physical unit among the plurality of physical units and update first count information corresponding to a first logical range according to the write instruction, wherein the first logical unit belongs to the first logical range; and in response to the first count information satisfying a predetermined condition, move the first data from the first type of physical unit to a second type of physical unit among the plurality of physical units.

[0007] An exemplary embodiment of the present disclosure further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is configured to connect to a host system. The memory interface is configured to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is configured to: receive a write instruction from the host system, wherein the write instruction indicates storing first data belonging to a first logical unit; in response to the first data being a first type of data, store the first data to a first type of physical unit among the plurality of physical units and update first count information corresponding to a first logical range according to the write instruction, wherein the first logical unit belongs to the first logical range; and in response to the first count information satisfying a predetermined condition, move the first data from the first type of physical unit to a second type of physical unit among the plurality of physical units.

[0008] Based on the above, after receiving a write instruction indicating storing first data belonging to a first logical unit from a host system, in response to the first data being a first type of data, the first data can be stored to a first type of physical unit, and first count information corresponding to a first logical range can be updated. Then, in response to the first count information satisfying a predetermined condition, the first data can be moved from the first type of physical unit to a second type of physical unit. In this way, the write efficiency and the write continuity of data can be effectively balanced. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown in accordance with an example embodiment of the present invention;

[0010] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown in accordance with an example embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of a host system and a memory storage device shown in accordance with an example embodiment of the present invention;

[0012] Figure 4 is a schematic diagram of a memory storage device shown in accordance with an example embodiment of the present invention;

[0013] Figure 5 is a schematic diagram of a memory control circuit unit shown in accordance with an example embodiment of the present invention;

[0014] Figure 6 is a schematic diagram of a management rewritable non-volatile memory module shown in accordance with an example embodiment of the present invention;

[0015] Figure 7 is a schematic diagram of writing data shown in accordance with an example embodiment of the present invention;

[0016] Figure 8 is a schematic diagram of moving a plurality of data belonging to a first logical range from a first type of physical unit to a second type of physical unit shown in accordance with an example embodiment of the present invention;

[0017] Figure 9 is a schematic diagram of a count table shown in accordance with an example embodiment of the present invention;

[0018] Figure 10 is a schematic diagram of reconstructing first management data and second management data shown in accordance with an example embodiment of the present invention;

[0019] Figure 11 is a flowchart of a data writing method shown in accordance with an example embodiment of the present invention. DETAILED DESCRIPTION

[0020] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings / taken to indicate the same or similar elements.

[0021] Generally speaking, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to or read data from the memory storage device.

[0022] Figure 1 FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device, according to an example embodiment of the present disclosure. Figure 2 FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device, according to an example embodiment of the present disclosure.

[0023] Please refer to Figure 1 and Figure 2 The host system 11 can include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 can be connected to a system bus 110.

[0024] In an example embodiment, the host system 11 can be connected to the memory storage device 10 through the data transfer interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 can be connected to the I / O device 12 through the system bus 110. For example, the host system 11 can transmit an output signal to or receive an input signal from the I / O device 12 via the system bus 110.

[0025] In an example embodiment, the processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 can be disposed on a host board 20 of the host system 11. The number of the data transfer interface 114 can be one or more. Through the data transfer interface 114, the host board 20 can be connected to the memory storage device 10 via a wired or wireless manner.

[0026] In an example embodiment, the memory storage device 10 can be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a Near Field Communication (NFC) memory storage device, a WiFi memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy memory storage device (e.g., iBeacon), etc. In addition, the host board 20 can also be connected to various I / O devices, such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. via the system bus 110. For example, in an example embodiment, the host board 20 can access the wireless memory storage device 204 via the wireless transmission device 207.

[0027] In an example embodiment, the host system 11 is a computer system. In an example embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 can respectively comprise a memory storage device 30 and a host system 31. Figure 3

[0028] Figure 3 is a schematic diagram of a host system and a memory storage device according to an example embodiment of the present application. Please refer to Figure 3 The memory storage device 30 can be used in cooperation with the host system 31 to store data. For example, the host system 31 can be a digital camera, a camcorder, a communication device, an audio player, a video player, or a tablet computer, etc. For example, the memory storage device 30 can be any type of non-volatile memory storage device used by the host system 31, such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded storage device 34 includes an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342, etc.

[0029] Figure 4 is a schematic diagram of a memory storage device according to an example embodiment of the present application. Please refer to​Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.

[0030] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it must be understood that the present application is not limited thereto, and the connection interface unit 41 can also be compatible with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 is disposed outside a chip that includes the memory control circuit unit 42.

[0031] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in a hardware type or a firmware type and perform operations such as writing, reading, and erasing data in the rewritable nonvolatile memory module 43 according to instructions of the host system 11.

[0032] The rewritable nonvolatile memory module 43 stores data written by the host system 11. The rewritable nonvolatile memory module 43 can include a single level cell (SLC) NAND type flash memory module (i.e., a flash memory module in which one memory cell stores one bit), a multi level cell (MLC) NAND type flash memory module (i.e., a flash memory module in which one memory cell stores two bits), a triple level cell (TLC) NAND type flash memory module (i.e., a flash memory module in which one memory cell stores three bits), a quad level cell (QLC) NAND type flash memory module (i.e., a flash memory module in which one memory cell stores four bits), another flash memory module, or another memory module having the same characteristics.

[0033] Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between a control gate and a channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer is changed, and thus the threshold voltage of the memory cell is changed. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming the memory cell". As the threshold voltage is changed, each memory cell in the rewritable nonvolatile memory module 43 has a plurality of storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, and thus it is possible to acquire one or more bits stored in the memory cell.

[0034] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programming units, and these physical programming units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than two bits, then physical programming units on the same word line can be classified into at least lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0035] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains a minimum number of storage units to be erased together. For example, a physical erase unit is a physical block.

[0036] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Please refer to... Figure 5 The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0037] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and these control instructions are executed to perform data write, read and erase operations, etc. when the memory storage device 10 is in operation. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0038] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions are executed by the microprocessor unit to perform data write, read and erase operations, etc.

[0039] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a program code form in a specific area (e.g., a system area in the memory module for storing system data) of the rewritable non-volatile memory module 43. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Then, the microprocessor unit executes these control instructions to perform data write, read and erase operations, etc.

[0040] In an example embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware type. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or the groups of memory cells of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 43 and the data read from the rewritable non-volatile memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations, etc. In an example embodiment, the memory management circuit 51 can also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct to perform corresponding operations.

[0041] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In the present example embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present application is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0042] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written into the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 transmits a corresponding instruction sequence. For example, the instruction sequence can include a write instruction sequence indicating write data, a read instruction sequence indicating read data, an erase instruction sequence indicating erase data, and a corresponding instruction sequence to indicate various memory operations (e.g., change the read voltage level or perform a garbage collection operation, etc.). These instruction sequences are generated, for example, by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences can include one or more signals, or data on a bus. These signals or data can include instruction codes or program codes. For example, in a read instruction sequence, the identification code of the read, the memory address, etc. information is included.

[0043] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0044] The error checking and correction circuit 54 is connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write instruction from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to this write instruction, and the memory management circuit 51 writes the data corresponding to this write instruction and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the corresponding error correcting code and / or error detecting code corresponding to this data is also read, and the error checking and correction circuit 54 performs error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0045] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0046] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0047] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to... Figure 6 The memory management circuit 51 can logically group the physical cells 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602.

[0048] In one exemplary embodiment, an entity unit comprises one or more entity blocks. An entity unit may comprise multiple entity nodes. In one exemplary embodiment, each entity node may store 4KB of data. In another exemplary embodiment, each entity node may store more or less data; this invention is not limited thereto.

[0049] Entity units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 (User data of host system 11). For example, entity units 610(0) to 610(A) in storage area 601 can store valid and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit can be associated (or added) to free area 602. In addition, entity units in free area 602 (or entity units that do not store valid data) can be erased. When new data is written, one or more entity units can be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0050] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map physical units 610(0) to 610(A) in memory area 601. In one exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logic unit may also correspond to a logical programmable unit or consist of multiple consecutive or non-consecutive logical addresses.

[0051] It should be noted that one logical unit can be mapped to one or more physical units. If a certain physical unit is currently mapped by a certain logical unit, it means that the data currently stored in the physical unit includes valid data. On the contrary, if a certain physical unit is not currently mapped by any logical unit, it means that the data currently stored in the physical unit is invalid data.

[0052] The memory management circuit 51 can record mapping information (also referred to as logical-to-physical mapping information) describing the mapping relationship between the logical units and the physical units in at least one mapping table (also referred to as a logical-to-physical mapping table). When the host system 11 wants to read data from or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information (i.e., the mapping information) in the mapping table.

[0053] Figure 7 is a schematic diagram of writing data according to an example embodiment of the present application. Please refer to Figure 7 The memory management circuit 51 can receive at least one write instruction from the host system 11. The write instruction indicates data (also referred to as first data) 701 belonging to a certain logical unit (also referred to as a first logical unit). According to the write instruction, the memory management circuit 51 can determine whether the data 701 is first-type data or second-type data.

[0054] In an example embodiment, in response to the data 701 being first-type data, the memory management circuit 51 can instruct the rewritable non-volatile memory module 43 to store the data 701 in a first-type physical unit 71 according to the write instruction. For example, the memory management circuit 51 can extract at least one physical unit from the free area 602 as the first-type physical unit 71. The total number of the first-type physical units 71 can be one or more. Figure 6

[0055] On the other hand, in response to the data 701 being first-type data, the memory management circuit 51 can also update the count information (also referred to as first count information) corresponding to a certain logical range (also referred to as a first logical range). In particular, the first logical unit belongs to the first logical range. For example, assuming that the first logical unit corresponds to logical block address LBA(20), the first logical range can cover logical block addresses LBA(0)~LBA(1023), and the size of each logical range can be adjusted according to practical needs.

[0056] ​After storing the data 701 to the first type of physical unit 71 and updating the first count information, the memory management circuit 51 can determine whether the first count information meets a predetermined condition. In response to the first count information meeting the predetermined condition, the memory management circuit 51 can instruct the rewritable non-volatile memory module 43 to move the data 701 from the first type of physical unit 71 to the second type of physical unit 72. For example, the memory management circuit 51 can extract at least one physical unit from the free area 602 as the second type of physical unit 72. The total number of the second type of physical unit 72 can also be one or more. Figure 6

[0057] In an example embodiment, in response to the data 701 being the second type of data, the memory management circuit 51 can instruct the rewritable non-volatile memory module 43 to store the data 701 to the second type of physical unit 72 according to the write instruction. In other words, in the case that the data 701 is the second type of data, the data 701 can be directly stored to the second type of physical unit 72 without being first stored to the first type of physical unit 71 and then moved to the second type of physical unit 72. In another aspect, according to whether the data 701 is the first type of data or the second type of data, the data 701 can be directly stored to one of the first type of physical unit 71 and the second type of physical unit 72.

[0058] In an example embodiment, the memory management circuit 51 can determine whether the data 701 is the first type of data or the second type of data according to the data amount of the data 701. For example, the memory management circuit 51 can determine whether the data amount of the data 701 is less than a critical data amount. In response to the data amount of the data 701 being less than the critical data amount, the memory management circuit 51 can determine that the data 701 is the first type of data. Alternatively, in response to the data amount of the data 701 not being less than (i.e., greater than or equal to) the critical data amount, the memory management circuit 51 can determine that the data 701 is the second type of data. The critical data amount can be set according to practical requirements, and the present application is not limited thereto.

[0059] In an example embodiment, the first type of physical unit 71 can be dedicated to storing data having a data amount less than the critical data amount, and the second type of physical unit 72 can be dedicated to storing data having a data amount not less than the critical data amount. In this way, no matter what the data amount of the data 701 received from the host system 11 is, the data 701 can be stored in the corresponding type of physical unit in the most appropriate manner, thereby improving the storage efficiency of the data 701.

[0060] ​In an example embodiment, the first count information includes a count value. The memory management circuit 51 can determine whether the first count information satisfies the predetermined condition according to the count value. For example, the memory management circuit 51 can determine whether the count value reaches a threshold value. In response to the count value reaching the threshold value, the memory management circuit 51 can determine that the first count information satisfies the predetermined condition. Alternatively, in response to the count value not reaching the threshold value, the memory management circuit 51 can determine that the first count information does not satisfy the predetermined condition.

[0061] In an example embodiment, the first count information (or the count value) can reflect how many data belonging to the first logical range have been stored into the first type of physical unit 71. In an example embodiment, if the count value reaches the threshold value, it indicates that at least part of the data belonging to the first logical range has been stored into the first type of physical unit 71. Therefore, in response to the count value reaching the threshold value (i.e. the first count information satisfies the predetermined condition), the memory management circuit 51 can instruct the rewritable non-volatile memory module 43 to move the data (including the first data) belonging to the first logical range and originally stored in the first type of physical unit 71 to the second type of physical unit 72 for continuous and / or concentrated storage. In this way, the management efficiency of the data belonging to the first logical range can be effectively improved. However, if the count value does not reach the threshold value (i.e. the first count information does not satisfy the predetermined condition), the data belonging to the first logical range can not be moved (i.e. the first data is kept in the first type of physical unit 71) temporarily.

[0062] In an example embodiment, in response to the first count information satisfying the predetermined condition, the memory management circuit 51 can move the data 701 together with another data (also referred to as second data) in the first type of physical unit 71 to the second type of physical unit 72. In particular, the second data belongs to a specific logical unit (also referred to as second logical unit), and the second logical unit also belongs to the first logical range. In addition, after the first data and the second data are moved to the second type of physical unit 72, the first data and the second data still stored in the first type of physical unit 71 can be marked as invalid data.

[0063] Figure 8 is a schematic diagram showing the moving of multiple data belonging to the first logical range from the first type of physical unit to the second type of physical unit according to an example embodiment of the present application. Please refer to Figure 8, assume that data D(R1.1), D(R2.1), D(R1.2), D(R1.3) and D(R3.1) are continuously stored in the first type of physical unit 81. The logical units to which data D(R1.1), D(R1.2) and D(R1.3) belong are continuous and included in a first logical range (labeled as R1). The logical unit to which data D(R2.1) belongs is included in a second logical range (labeled as R2). The logical unit to which data D(R3.1) belongs is included in a third logical range (labeled as R3).

[0064] It is noted that, in the first type of physical unit 81, data D(R1.1), D(R1.2) and D(R1.3) are stored in a dispersed manner in a plurality of non-continuous physical sub-units (e.g. physical pages, physical fans or physical nodes). In this case, the storage manner (i.e. non-continuous storage) of data D(R1.1), D(R1.2) and D(R1.3) in the first type of physical unit 81 is not conducive to the continuous reading of data D(R1.1), D(R1.2) and D(R1.3).

[0065] In an example embodiment, in response to the count information corresponding to the first logical range (i.e. the first count information) satisfying a predetermined condition, data D(R1.1), D(R1.2) and D(R1.3) can be moved from the first type of physical unit 81 to the second type of physical unit 82 for continuous and / or centralized storage. For example, in the second type of physical unit 82, data D(R1.1), D(R1.2) and D(R1.3) can be stored in a plurality of continuous physical sub-units (e.g. physical pages, physical fans or physical nodes). In particular, the storage manner (i.e. continuous storage) of data D(R1.1), D(R1.2) and D(R1.3) in the second type of physical unit 82 will be conducive to the continuous reading of data D(R1.1), D(R1.2) and D(R1.3) in the future. Furthermore, after data D(R1.1), D(R1.2) and D(R1.3) are moved to the second type of physical unit 82, data D(R1.1), D(R1.2) and D(R1.3) that are still stored in the first type of physical unit 81 can be marked as invalid data.

[0066] In an example embodiment, the memory management circuit 51 can store the count information corresponding to the plurality of logical ranges in one or more count tables. Then, the memory management circuit 51 can dynamically update the count information according to the data storage status of the logical ranges.

[0067] Figure 9 is a schematic diagram of a count table according to an example embodiment of the present application. Please refer to Figure 9In an example embodiment, the memory management circuit 51 can establish a count table 91. The memory management circuit 51 can generate corresponding index values according to different logical ranges. One index value corresponds to one logical range. Then, the memory management circuit 51 can record the index values corresponding to one or more logical ranges and the count values (i.e., count information) in the count table 91. For example, the index value R1 and the count value C1 correspond to the first logical range, the index value R2 and the count value C2 correspond to the second logical range, and so on.

[0068] In an example embodiment, the memory management circuit 51 can dynamically update the information in the count table 91 according to the current data write status. For example, in response to the first type of data belonging to the first logical range being stored to the first type of physical unit, the count value C1 (i.e., the first count information) corresponding to the first logical range can be updated to reflect the latest data storage status of the first logical range.

[0069] In an example embodiment, after the data 701 is moved from the first type of physical unit 71 to the second type of physical unit 72, the memory management circuit 51 can clear or reset the first count information. In addition, the memory management circuit 51 can also employ various table management and optimization techniques such as competition and / or encoding to improve the recording efficiency of the information in the count table 91, which will not be described in more detail herein.

[0070] In an example embodiment, during or after the data 701 is moved from the first type of physical unit 71 to the second type of physical unit 72, the memory management circuit 51 can detect an abnormal power-off of the memory storage device 10. In response to the abnormal power-off, after the memory storage device 10 is re-powered, the memory management circuit 51 can reconstruct the management data corresponding to the first type of physical unit 71 (also referred to as the first management data) and the management data corresponding to the second type of physical unit 72 (also referred to as the second management data). For example, the first management data includes a time stamp corresponding to the time when the data 701 is written to the first type of physical unit 71, and / or the second management data includes a time stamp corresponding to the time when the data 701 is written to the second type of physical unit 72. Then, the memory management circuit 51 can determine whether the data 701 in the first type of physical unit 71 is valid data according to the first management data and the second management data.

[0071] Figure 10 is a schematic diagram showing the reconstruction of the first management data and the second management data according to an example embodiment of the present application. Please refer to Figure 10 , which is a continuation of Figure 8In an example embodiment, when data D(R1.2) is stored in the first type of physical unit 81, the memory management circuit 51 can store a time stamp TS(1) with data D(R1.2) in the first type of physical unit 81. Alternatively, the memory management circuit 51 can store the time stamp TS(1) in the management data corresponding to the first type of physical unit 81. The time stamp TS(1) can reflect the time point at which data D(R1.2) is stored in the first type of physical unit 81. In addition, when data D(R1.2) is stored in the second type of physical unit 82, the memory management circuit 51 can store a time stamp TS(2) with data D(R1.2) in the second type of physical unit 82. Alternatively, the memory management circuit 51 can store the time stamp TS(2) in the management data corresponding to the second type of physical unit 82. The time stamp TS(2) can reflect the time point at which data D(R1.2) is stored in the second type of physical unit 82.

[0072] In an example embodiment, assume that an abnormal power-off of the memory storage device 10 occurs during or after the data migration of data D(R1.2). After the memory storage device 10 is re-powered, in response to the abnormal power-off, the memory management circuit 51 can reconstruct the management data corresponding to the first type of physical unit 81 (i.e., first management data) and the management data corresponding to the second type of physical unit 82 (i.e., second management data). For example, the first management data can include the time stamp TS(1) corresponding to data D(R1.2), and the second management data can include the time stamp TS(2) corresponding to data D(R1.2).

[0073] In an example embodiment, according to the time stamps TS(1) and TS(2) in the reconstructed management data, the memory management circuit 51 can determine whether data D(R1.2) in the first type of physical unit 81 is valid data. For example, in response to the value of the time stamp TS(2) being greater than the value of the time stamp TS(1), indicating that the time point at which data D(R1.2) is stored in the second type of physical unit 82 is later than the time point at which data D(R1.2) is stored in the first type of physical unit 81, the memory management circuit 51 can determine that the data migration of data D(R1.2) has been previously completed and that data D(R1.2) in the first type of physical unit 81 is invalid data.

[0074] On the other hand, if the value of the timestamp TS(2) is not greater than the value of TS(l) or the timestamp TS(2) does not exist in the second management data, it indicates that the previous data migration for the data D(R1.2) has not been completed or failed, and thus the memory management circuit 51 can determine that the data D(R1.2) in the first type of physical unit 81 is still valid data. In this way, the memory management circuit 51 can normally manage the data (i.e., valid data) in the first type of physical unit 81 regardless of whether an abnormal power-off occurs. Furthermore, once all the data (i.e., valid data) in the first type of physical unit 81 has been migrated to the second type of physical unit 82, the first type of physical unit 81 can be associated to the idle area 602 of the memory device 60 and can be erased. Figure 6

[0075] Figure 11 is a flowchart of a data write method according to an exemplary embodiment of the present application. Please refer to Figure 11 , in step S1101, a write instruction is received from a host system. The write instruction instructs to store a first data belonging to a first logical unit. In step S1102, it is determined whether the first data belongs to a first type of data. If the first data belongs to the first type of data, in step S1103, the first data is stored to a first type of physical unit according to the write instruction. In step S1104, a first count information corresponding to a first logical range to which the first logical unit belongs is updated.

[0076] In step S1105, it is determined whether the first count information meets a predetermined condition. If the first count information meets the predetermined condition, in step S1106, the first data is migrated from the first type of physical unit to a second type of physical unit. However, if the first count information does not meet the predetermined condition, step S1101 can be repeatedly executed to successively process a next instruction (e.g., a write instruction) from the host system. On the other hand, if it is determined in step S1102 that the first data does not belong to the first type of data (e.g., the first data belongs to a second type of data), in step S1107, the first data is stored to a second type of physical unit according to the write instruction.

[0077] However, Figure 11 have been described above, and thus will not be repeated here. It is noted that, Figure 11 each of the steps in FIG. 10 can be implemented as a plurality of program codes or circuits, and the present application is not limited thereto. Furthermore, Figure 11 the method of FIG. 10 can be used in combination with the above exemplary embodiments or can be used alone, and the present application is not limited thereto.

[0078] ​To sum up, the data writing method, the memory storage device and the memory control circuit unit provided by the example embodiments of the present application can ensure the continuity of the data belonging to the same logical range in the physical storage space by performing the subsequent data moving and merging under the premise of meeting the preset data shunting storage, thereby taking into account the writing efficiency and the writing continuity of the data.

[0079] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data writing method, characterized in that, For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical units, and the data writing method includes: Receive a write instruction from the host system, wherein the write instruction indicates that first data belonging to the first logical unit is stored; In response to the first data being of a first type, the first data is stored in a first type of entity unit among the plurality of entity units according to the write instruction, and the first count information corresponding to a first logical range is updated. The first logical unit belongs to the first logical range, and the first type of entity unit also stores third data belonging to a second logical range, which is different from the first logical unit. The first count information includes a count value, which is updated based on the amount of data belonging to the first logical range and currently stored in the first type of entity unit, rather than based on all or any data in the first type of entity unit. In response to the first counting information meeting preset conditions, the first data belonging to the first logical range is moved from the first type of entity unit to the second type of entity unit among the plurality of entity units, while the third data belonging to the second logical range is retained in the first type of entity unit. The first type of entity unit is dedicated to storing data whose data volume is less than the critical data volume, and the second type of entity unit is dedicated to storing data whose data volume is not less than the critical data volume.

2. The data writing method according to claim 1 further includes: In response to the first data being second type of data, the first data is stored in the second type of entity unit according to the write instruction.

3. The data writing method according to claim 1 further includes: Based on the amount of data in the first data, it is determined whether the first data belongs to the first type of data or the second type of data.

4. The data writing method according to claim 1 further includes: Whether the first counting information meets the preset conditions is determined based on whether the count value reaches the critical value.

5. The data writing method according to claim 1, wherein the step of moving the first data from the first type of entity unit to the second type of entity unit includes: The first data, together with the second data in the first type of entity unit, is moved to the second type of entity unit, wherein the second data belongs to the second logical unit and the second logical unit also belongs to the first logical scope.

6. The data writing method according to claim 1 further includes: After the first data is moved from the first type of entity unit to the second type of entity unit, the first counting information is cleared or reset.

7. The data writing method according to claim 1 further includes: During or after the transfer of the first data from the first type of entity unit to the second type of entity unit, an abnormal power outage is detected; In response to the abnormal power outage, the first management data corresponding to the first type of entity unit and the second management data corresponding to the second type of entity unit are reconstructed; as well as Based on the first management data and the second management data, determine whether the first data in the first type of entity unit is valid data.

8. A memory storage device, characterized in that, include: A connection interface unit for connecting to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical units; as well as The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: Receive a write instruction from the host system, wherein the write instruction indicates that first data belonging to the first logical unit is stored; In response to the first data being of the first type, the first data is stored in the first type of entity unit among the plurality of entity units according to the write instruction, and the first count information corresponding to the first logical range is updated, wherein the first logical unit belongs to the first logical range, the first type of entity unit also stores third data belonging to the second logical range, the second logical range is different from the first logical unit, the first count information includes a count value, the count value is updated based on the amount of data belonging to the first logical range and currently stored in the first type of entity unit, rather than based on all data or arbitrary data in the first type of entity unit; as well as In response to the first counting information meeting preset conditions, the first data belonging to the first logical range is moved from the first type of entity unit to the second type of entity unit among the plurality of entity units, while the third data belonging to the second logical range is retained in the first type of entity unit. The first type of entity unit is dedicated to storing data whose data volume is less than the critical data volume, and the second type of entity unit is dedicated to storing data whose data volume is not less than the critical data volume.

9. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to: In response to the first data being second type of data, the first data is stored in the second type of entity unit according to the write instruction.

10. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to: Based on the amount of data in the first data, it is determined whether the first data belongs to the first type of data or the second type of data.

11. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to: Whether the first counting information meets the preset conditions is determined based on whether the count value reaches the critical value.

12. The memory storage device of claim 8, wherein the operation of the memory control circuit unit moving the first data from the first type of entity unit to the second type of entity unit includes: The first data, together with the second data in the first type of entity unit, is moved to the second type of entity unit, wherein the second data belongs to the second logical unit and the second logical unit also belongs to the first logical scope.

13. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to: After the first data is moved from the first type of entity unit to the second type of entity unit, the first counting information is cleared or reset.

14. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to: During or after the transfer of the first data from the first type of entity unit to the second type of entity unit, an abnormal power outage is detected; In response to the abnormal power outage, the first management data corresponding to the first type of entity unit and the second management data corresponding to the second type of entity unit are reconstructed; as well as Based on the first management data and the second management data, determine whether the first data in the first type of entity unit is valid data.

15. A memory control circuit unit, characterized in that, This is used to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple physical units, and the memory control circuit unit includes: Host interface, used to connect to the host system; A memory interface for connecting to the rewritable non-volatile memory module; and The memory management circuit is connected to the host interface and the memory interface. The memory management circuit mentioned above is used for: Receive a write instruction from the host system, wherein the write instruction indicates that first data belonging to the first logical unit is stored; In response to the first data being of a first type, the first data is stored in a first type of entity unit among the plurality of entity units according to the write instruction, and the first count information corresponding to a first logical range is updated. The first logical unit belongs to the first logical range, and the first type of entity unit also stores third data belonging to a second logical range, which is different from the first logical unit. The first count information includes a count value, which is updated based on the amount of data belonging to the first logical range and currently stored in the first type of entity unit, rather than based on all or any data in the first type of entity unit. In response to the first counting information meeting preset conditions, the first data belonging to the first logical range is moved from the first type of entity unit to the second type of entity unit among the plurality of entity units, while the third data belonging to the second logical range is retained in the first type of entity unit. The first type of entity unit is dedicated to storing data whose data volume is less than the critical data volume, and the second type of entity unit is dedicated to storing data whose data volume is not less than the critical data volume.

16. The memory control circuit unit according to claim 15, wherein the memory management circuit is further configured to: In response to the first data being second type of data, the first data is stored in the second type of entity unit according to the write instruction.

17. The memory control circuit unit according to claim 15, wherein the memory management circuit is further configured to: Based on the amount of data in the first data, it is determined whether the first data belongs to the first type of data or the second type of data.

18. The memory control circuit unit according to claim 15, wherein the memory management circuit is further configured to: Whether the first counting information meets the preset conditions is determined based on whether the count value reaches the critical value.

19. The memory control circuit unit of claim 15, wherein the operation of the memory management circuit moving the first data from the first type of entity unit to the second type of entity unit includes: The first data, together with the second data in the first type of entity unit, is moved to the second type of entity unit, wherein the second data belongs to the second logical unit and the second logical unit also belongs to the first logical scope.

20. The memory control circuit unit according to claim 15, wherein the memory management circuit is further configured to: After the first data is moved from the first type of entity unit to the second type of entity unit, the first counting information is cleared or reset.

21. The memory control circuit unit according to claim 15, wherein the memory management circuit is further configured to: During or after the transfer of the first data from the first type of entity unit to the second type of entity unit, an abnormal power outage is detected; In response to the abnormal power outage, the first management data corresponding to the first type of entity unit and the second management data corresponding to the second type of entity unit are reconstructed; as well as Based on the first management data and the second management data, determine whether the first data in the first type of entity unit is valid data.

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