A method for manufacturing a schottky diode and a device
By forming growth steps on the semiconductor structure layer and implanting barrier ions, the problems of complex structure or poor crystal quality in the prior art are solved, and high-quality Schottky diodes are fabricated, which improves reverse breakdown voltage and reduces leakage current.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHU RES INST OF XIAN UNIV OF ELECTRONIC SCI & TECH
- Filing Date
- 2023-01-10
- Publication Date
- 2026-05-01
AI Technical Summary
Existing technologies that use P-type buried layers to improve the reverse bias withstand voltage of diodes have relatively complex structures, or relatively simple structures but make it difficult to achieve high-quality growth of the structural layers within the device, resulting in poor diode performance.
Semiconductor structure layers are grown on a substrate, and growth steps are formed at both ends of the layers. Barrier ions are injected to form ion implantation regions, and cathode and anode electrodes are grown separately. Carrier blocking is achieved through a simple process, ensuring the crystal quality and electric field distribution of each layer structure.
This method enables the fabrication of high-quality Schottky diodes, improves reverse withstand voltage, reduces leakage current, and simplifies the process flow.
Smart Images
Figure CN116153780B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a Schottky diode and a Schottky diode device. Background Technology
[0002] Gallium nitride (GaN), a wide-bandgap, high-mobility semiconductor material, is considered suitable for fabricating power diodes with high breakdown electric fields and low on-resistance. These devices will be widely used in energy, aerospace, transportation, and many other fields. However, achieving the theoretical critical breakdown electric field (3.3 MV / cm) for GaN remains challenging. The fundamental reason is that excessively high local electric fields under electrical stress can trigger pre-breakdown. To address this issue, existing technologies propose using p-type buried layers based on theoretical modeling to improve the electric field distribution under reverse bias voltage, thereby enhancing the reverse bias withstand voltage. However, these solutions are often complex, or while possessing relatively simple structures, they involve non-planar GaN film re-growth processes. This results in poor crystal quality within the grown GaN film, ultimately affecting the overall diode performance. Summary of the Invention
[0003] Therefore, the technical problem to be solved by the present invention is to address the issue that existing technical solutions for improving the reverse bias withstand voltage level of diodes using P-type buried layers have complex structures, or relatively simple structures but the structural layers within the device are difficult to grow with high quality, resulting in poor diode performance. The present invention provides a method for fabricating a Schottky diode device with a relatively simple structure and high quality, as well as a Schottky diode device fabricated by the method.
[0004] Therefore, according to a first aspect, the present invention provides a method for fabricating a Schottky diode, comprising the following steps:
[0005] A semiconductor structure layer is grown on a substrate; the semiconductor structure layer includes a high-resistivity layer, a P-type buried layer, a channel layer, and a barrier layer grown sequentially.
[0006] Etch the semiconductor structure layer to form a first growth step and a second growth step at its two ends, respectively, to reach the P-type buried layer;
[0007] Blocking ions are injected into the P-type buried layer at the first growth step to form an ion implantation region. The ion implantation region penetrates the P-type buried layer and extends beyond the first growth step.
[0008] Cathodes and anodes are grown on the first growth step and the second growth step, respectively.
[0009] In one possible implementation, the step of implanting barrier ions into the P-type buried layer at the first growth step to form an ion implantation region, and the ion implantation region extending beyond the first growth step, specifically includes:
[0010] Barrier ions were implanted into the P-type buried layer at the first growth step using an ion implantation process.
[0011] An annealing process is used to prevent ions from diffusing beyond the first growth step, forming an ion implantation region.
[0012] In one possible implementation, the anode also extends onto the semiconductor structure layer.
[0013] In one possible implementation, the semiconductor structure layer further includes a P-type cap layer disposed on the barrier layer.
[0014] In one possible implementation, prior to the steps of growing the cathode and anode on the first growth step and the second growth step, respectively, the method further includes:
[0015] The P-type cap layer is etched at one end near the first growth step to create an isolation gap between the cathode and the P-type cap layer.
[0016] In one possible implementation, the high-resistivity layer is an AlGaN high-resistivity layer, the P-type buried layer is a P-type AlGaN buried layer, the channel layer is an AlGaN channel layer, the barrier layer is an AlGaN barrier layer, and the P-type cap layer is a P-type AlGaN cap layer; wherein the Al content in the AlGaN high-resistivity layer, the P-type AlGaN buried layer, the AlGaN channel layer, and the P-type AlGaN cap layer is all less than the Al content in the AlGaN barrier layer.
[0017] According to a second aspect, the present invention also provides a Schottky diode device, comprising:
[0018] The substrate and a semiconductor structure layer disposed on the substrate, the semiconductor structure layer including a high resistive layer, a P-type buried layer, a channel layer and a barrier layer disposed sequentially; a first growth step and a second growth step reaching the P-type buried layer are respectively disposed at both ends of the semiconductor structure layer; the P-type buried layer at the first growth step has an ion implantation region, and the ion implantation region extends beyond the first growth step.
[0019] The negative electrode and the positive electrode are respectively disposed on the first growth step and the second growth step.
[0020] In one possible implementation, the anode also extends onto the semiconductor structure layer.
[0021] In one possible implementation, the semiconductor structure layer further includes a P-type cap layer disposed on the barrier layer, and an isolation gap exists between the P-type cap layer and the cathode.
[0022] The technical solution provided by this invention has the following advantages:
[0023] The Schottky diode fabrication method provided by this invention involves directly stacking and growing each layer of the semiconductor structure layer, ensuring that the growth substrate of each layer is a flat plane, thus guaranteeing the crystal quality of each layer and providing a foundation for fabricating a high-quality Schottky diode. Simultaneously, by including a P-type buried layer beneath the barrier layer and the channel layer within the semiconductor structure layer, the carrier transport channels in the channel layer are blocked, improving the electric field distribution and thereby increasing the reverse breakdown voltage and reducing the leakage current. Furthermore, by etching a first growth step and a second growth step at the two ends of the semiconductor structure layer, and injecting barrier ions into the P-type buried layer at the first growth step to form an ion implantation region, the method achieves a relatively simple process to block carriers between the cathode and anode, preventing direct conduction between them and thus enabling the fabrication of a high-quality Schottky diode. Attached Figure Description
[0024] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0025] Figure 1 A flowchart illustrating a method for fabricating a Schottky diode according to an embodiment of the present invention;
[0026] Figure 2 This is a schematic diagram of the structure of the device prepared in step S10;
[0027] Figure 3 This is a schematic diagram of the structure of the device prepared in step S20;
[0028] Figure 4 This is a schematic diagram of the structure of the device prepared in step S30;
[0029] Figure 5 This is a schematic diagram of the structure of the device prepared in step S50;
[0030] Figure 6 A schematic diagram of a Schottky diode device provided for an embodiment of the invention;
[0031] Figure 7 Another schematic diagram of the structure of a Schottky diode device provided for an embodiment of the invention;
[0032] Explanation of reference numerals in the attached figures:
[0033] 2-Semiconductor structure layer; 21-High resistivity layer; 22-P-type buried layer; 23-Channel layer; 24-Barrier layer; 25-P-type cap layer; 2a-First growth step; 2b-Second growth step; 2c-Ion implantation region; 3-Cathode electrode; 4-Anode electrode. Detailed Implementation
[0034] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0035] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0036] Example 1
[0037] Figure 1 A flowchart illustrating a method for fabricating a Schottky diode according to this embodiment is shown. Figure 1 As shown, the method includes the following steps:
[0038] S10: Grow semiconductor structure layer 2 on the substrate.
[0039] Specifically, such as Figure 2 As shown, the semiconductor structure layer 2 includes a high-resistivity layer 21, a P-type buried layer 22, a channel layer 23, and a barrier layer 24 grown sequentially. Figure 2 Although the substrate is not shown, those skilled in the art should understand that the high-resistivity layer 21 is grown on the substrate. Specifically, the high-resistivity layer 21 can be a GaN high-resistivity layer, the p-type buried layer 22 can be a p-type GaN buried layer, the channel layer 23 can be a GaN channel layer, and the barrier layer 24 can be Al. x Ga 1-xThe N-type barrier layer (where x refers to the content of Al component therein) can also be configured as an AlGaN high-resistivity layer 21, a P-type buried layer 22 as a P-type AlGaN buried layer, an AlGaN channel layer 23 as an AlGaN channel layer, and an AlGaN barrier layer 24. In this case, the Al component content in the high-resistivity layer 21, the P-type buried layer 22, and the channel layer 23 is all less than the Al component content in the barrier layer 24.
[0040] In specific implementation, processes such as metal-organic chemical vapor deposition, molecular beam epitaxy, or hydride vapor phase epitaxy can be used to grow the semiconductor structure layer 2. At the same time, the thickness of the high-resistivity layer 21 can be set between 1 μm and 10 μm, the thickness of the P-type buried layer 22 can be between 0.1 μm and 1 μm, the thickness of the channel layer 23 can be between 100 nm and 500 nm, and the thickness of the barrier layer 24 can be between 10 nm and 50 nm.
[0041] In this embodiment, the substrate can be a substrate made of materials such as silicon, silicon carbide, GaN, or sapphire.
[0042] In this embodiment, to balance the stress between the substrate and the semiconductor structure layer 2 and ensure the growth quality of the semiconductor structure layer 2, at least one buffer layer can be grown between the substrate and the semiconductor structure layer 2 (i.e., between the substrate and the high-resistivity layer 21). Specifically, the buffer layer can be any existing buffer layer such as an AlN buffer layer. It should be noted that the high-resistivity layer 21 in the semiconductor structure layer 2 is set up precisely to prevent the conductivity of the buffer layer from affecting the performance of the semiconductor structure layer 2. Therefore, if the conductivity of the buffer layer can be avoided in practical applications, the high-resistivity layer 21 may not be provided in the semiconductor structure layer 2 in this embodiment.
[0043] In this embodiment, in order to further improve the electrical performance of the prepared Schottky diode device, such as... Figure 2 As shown, the semiconductor structure layer 2 can also include a P-type cap layer 25, which is disposed on the barrier layer 24. Similarly, the P-type cap layer 25 can be a P-type GaN cap layer or a P-type AlGaN cap layer (of course, the Al content in the P-type AlGaN cap layer is also less than the Al content in the AlGaN barrier layer). In specific implementations, the P-type cap layer 25 can be grown using processes such as metal-organic chemical vapor deposition, molecular beam epitaxy, or hydride vapor phase epitaxy. At the same time, the thickness of the P-type cap layer 25 can be set between 100 nm and 500 nm.
[0044] S20: Etch semiconductor structure layer 2 to form a first growth step 2a and a second growth step 2b at its two ends, respectively, to reach the P-type buried layer 22.
[0045] Specifically, when the semiconductor structure layer 2 includes a high-resistivity layer 21, a P-type buried layer 22, a channel layer 23, and a barrier layer 24 grown sequentially, both ends of the channel layer 23 and the barrier layer 24 are etched away; when the semiconductor structure layer 2 includes a high-resistivity layer 21, a P-type buried layer 22, a channel layer 23, a barrier layer 24, and a P-type cap layer 25 grown sequentially, then as... Figure 3 As shown, both ends of the channel layer 23, barrier layer 24, and P-type cap layer 25 are etched away. In practice, this etching step can be performed using either dry or wet etching processes. When using a dry etching process, chlorine gas can be introduced simultaneously to increase the etching rate.
[0046] S30: Ion blocking ions are injected into the P-type buried layer 22 at the first growth step 2a to form an ion implantation region 2c. The ion implantation region 2c penetrates the P-type buried layer 22 and extends to the outside of the first growth step 2a.
[0047] The device structure prepared through this step is as follows: Figure 4 As shown.
[0048] Specifically, the blocking ions can be hydrogen ions, oxygen ions, nitrogen ions, or fluoride ions, etc. In practice, inductively coupled plasma technology, microwave plasma chemical vapor deposition technology, or high-energy ion implantation technology can be used to implant the blocking ions.
[0049] Specifically, the extension of the ion implantation region 2c beyond the first growth step 2a can be achieved through an annealing process. Taking the implantation of barrier ions using an ion implantation process as an example, this step S30 may specifically include the following steps:
[0050] Step S31: Ion implantation process is used to implant barrier ions into the P-type buried layer 22 at the first growth step 2a.
[0051] Step S32: An annealing process is used to block ions from diffusing to the outside of the first growth step 2a, forming an ion implantation region 2c.
[0052] Specifically, the annealing temperature and annealing time can be set according to specific scenarios such as the specific type of blocking ions and the specific type of P-type buried layer 22. For example, if the blocking ions are hydrogen ions and the P-type buried layer 22 is a P-type GaN buried layer, the annealing temperature can be set between 300℃ and 500℃ and the annealing time can be set between 50s and 500s.
[0053] In this embodiment, in order to reduce the surface damage caused by blocking ion implantation to the P-type buried layer 22 and further improve the quality of the device prepared by this method, a passivation layer (such as an aluminum oxide layer or a silicon oxide layer) can be deposited on the semiconductor structure layer 2 before implementing step S30, and the passivation layer is cleaned and removed after step S30 is completed.
[0054] S40: Cathode 3 and anode 4 are grown on the first growth step 2a and the second growth step 2b, respectively.
[0055] The device structure prepared through this step is as follows: Figure 6 or Figure 7 As shown.
[0056] Specifically, the material of the cathode 3 can be Ti, Al, Ni, Au, Mo, or TiN, or an alloy formed from any two or more of Ti, Al, Ni, and Au. The material of the anode 4 can be the same as or different from that of the cathode 3, and the anode 4 can be grown using two metal materials sequentially. For example, Ni can be used to grow the first sub-electrode at one end of the second growth step 2b near the channel layer 23 and the barrier layer 24, and Au can be used to grow the second sub-electrode in the remaining part of the second growth step 2b, thus completing the growth of the anode 4.
[0057] Additionally, when the semiconductor structure layer 2 includes a high-resistivity layer 21, a P-type buried layer 22, a channel layer 23, a barrier layer 24, and a P-type cap layer 25, a step S50 should also be performed before performing step S40:
[0058] Step S50: Etch the P-type cap layer 25 at one end near the first growth step 2a.
[0059] To make, such as Figure 5 and Figure 6 As shown, there is an isolation gap between the cathode 3 grown in step S40 and the P-type cap layer 25.
[0060] Specifically, step S50 can be performed after step S30 or after step S20.
[0061] In this embodiment, to further improve the withstand voltage performance of the device prepared by this method, such as... Figure 6 and Figure 7 As shown, the anode 4 can be configured to extend further onto the semiconductor structure layer 2, thereby ensuring a uniform electric field distribution in the fabricated Schottky diode under reverse bias voltage. This avoids local electric field spikes exceeding the rated values of wide-bandgap semiconductors near the anode 4, thus reducing the probability of material breakdown and leakage, and improving the device's withstand voltage performance. Specifically, when the semiconductor structure layer 2 includes a high-resistivity layer 21, a P-type buried layer 22, a channel layer 23, a barrier layer 24, and a P-type cap layer 25, as shown... Figure 6 As shown, the anode 4 extends onto the P-type cap layer 25. In this case, the anode 4 can extend to cover the entire upper surface of the P-type cap layer 25. When the semiconductor structure layer 2 only includes the high-resistivity layer 21, the P-type buried layer 22, the channel layer 23, and the barrier layer 24, as shown... Figure 7As shown, the anode 4 also extends onto the barrier layer 24. However, in this case, the anode 4 only extends to cover a portion of the upper surface of the barrier layer 24 to ensure isolation between the anode 4 and the cathode 3. Specifically, when the anode 4 includes the first sub-electrode and the second sub-electrode as described above, then only the second sub-electrode can extend onto the semiconductor structure layer 2.
[0062] The Schottky diode fabrication method in this embodiment achieves high-quality Schottky diode fabrication by directly stacking and growing each layer of the semiconductor structure layer 2 sequentially. This ensures that the growth substrates of each layer are flat and plane, guaranteeing the crystal quality of each layer and providing a foundation for high-quality Schottky diode fabrication. Simultaneously, the inclusion of a P-type buried layer 22 beneath the barrier layer 24 and the channel layer 23 within the semiconductor structure layer 2 helps to block the carrier transport channels of the channel layer 23, improving the electric field distribution and thus increasing the reverse breakdown voltage and reducing leakage current. Furthermore, by etching a first growth step 2a and a second growth step 2b at both ends of the semiconductor structure layer 2, and implanting barrier ions into the P-type buried layer 22 at the first growth step 2a to form an ion implantation region 2c, a relatively simple process is used to block the carriers between the cathode 3 and anode 4, preventing direct conduction between them and achieving high-quality Schottky diode fabrication.
[0063] Example 2
[0064] This embodiment provides a Schottky diode device, which is prepared by the Schottky diode preparation method in Embodiment 1 above. Therefore, the content already stated in Embodiment 1 will not be repeated in this embodiment.
[0065] like Figure 6 and Figure 7 As shown, the device includes: a substrate, a semiconductor structure layer 2, a cathode 3, and a cathode 4.
[0066] The semiconductor structure layer 2 is disposed on the substrate and includes a high-resistivity layer 21, a P-type buried layer 22, a channel layer 23, and a barrier layer 24 disposed sequentially. A first growth step 2a and a second growth step 2b reaching the P-type buried layer 22 are respectively disposed at both ends of the semiconductor structure layer 2. An ion implantation region 2c is located within the P-type buried layer 22 at the first growth step 2a and extends beyond the first growth step 2a. A cathode 3 and a cathode 4 are respectively disposed on the first growth step 2a and the second growth step 2b.
[0067] In one possible implementation, such as Figure 6 and Figure 7 As shown, the anode 4 also extends onto the semiconductor structure layer 2.
[0068] In one possible implementation, such as Figure 6 As shown, the semiconductor structure layer 2 also includes a P-type cap layer 25, which is disposed on the barrier layer 24, and there is an isolation gap between the P-type cap layer 25 and the cathode 3.
[0069] The Schottky diode device in this embodiment has a high reverse breakdown voltage, low leakage current, and a simple structure with high crystal quality in each internal structural layer.
[0070] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.
Claims
1. A method for fabricating a Schottky diode, characterized in that, Includes the following steps: A semiconductor structure layer is grown on a substrate; the semiconductor structure layer includes a high-resistivity layer, a P-type buried layer, a channel layer, and a barrier layer grown sequentially. The semiconductor structure layer is etched to form a first growth step and a second growth step at its two ends, respectively, leading to the P-type buried layer; Blocking ions are injected into the P-type buried layer at the first growth step to form an ion implantation region, which penetrates the P-type buried layer and extends beyond the first growth step. A cathode and a cathode are grown on the first growth step and the second growth step, respectively.
2. The method for fabricating a Schottky diode according to claim 1, characterized in that, The step of implanting barrier ions into the P-type buried layer at the first growth step to form an ion implantation region, and the ion implantation region extending beyond the first growth step, specifically includes: The barrier ions are implanted into the P-type buried layer at the first growth step using an ion implantation process. An annealing process is used to diffuse the barrier ions outside the first growth step, forming the ion implantation region.
3. The method for fabricating a Schottky diode according to claim 1 or 2, characterized in that, The anode also extends onto the semiconductor structure layer.
4. The method for fabricating a Schottky diode according to claim 3, characterized in that, The semiconductor structure layer further includes a P-type cap layer, which is grown on the barrier layer.
5. The method for fabricating a Schottky diode according to claim 4, characterized in that, Before the step of growing the cathode and anode on the first growth step and the second growth step respectively, the method further includes: The P-type cap layer is etched at one end near the first growth step to create an isolation gap between the cathode and the P-type cap layer.
6. The method for fabricating a Schottky diode according to claim 4, characterized in that, The high-resistivity layer is an AlGaN high-resistivity layer, the P-type buried layer is a P-type AlGaN buried layer, the channel layer is an AlGaN channel layer, the barrier layer is an AlGaN barrier layer, and the P-type cap layer is a P-type AlGaN cap layer; wherein, the Al content in the AlGaN high-resistivity layer, the P-type AlGaN buried layer, the AlGaN channel layer, and the P-type AlGaN cap layer is all less than the Al content in the AlGaN barrier layer.
7. A Schottky diode device, characterized in that, include: The substrate and a semiconductor structure layer disposed on the substrate, the semiconductor structure layer comprising a high-resistivity layer, a P-type buried layer, a channel layer and a barrier layer grown sequentially; a first growth step and a second growth step reaching the P-type buried layer are respectively disposed at both ends of the semiconductor structure layer; the P-type buried layer at the first growth step has an ion implantation region, and the ion implantation region extends beyond the first growth step. The negative electrode and the positive electrode are respectively disposed on the first growth step and the second growth step.
8. The Schottky diode device according to claim 7, characterized in that, The anode also extends onto the semiconductor structure layer.
9. The Schottky diode device according to claim 7 or 8, characterized in that, The semiconductor structure layer further includes a P-type cap layer, which is disposed on the barrier layer, and there is an isolation gap between the P-type cap layer and the cathode.
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