A low-noise phase-locked loop circuit structure

Abstract

The present invention discloses a low-noise phase-locked loop circuit structure, comprising a first level conversion module, a second level conversion module, a high-voltage phase frequency detector, a high-voltage charge pump module, a loop filter, a voltage-controlled oscillator, and a duty cycle expansion divider. This structure fully utilizes the device characteristic of high-voltage tube noise being superior to low-voltage tube noise under advanced processes, maximally reducing the noise of the phase frequency detector and charge pump. At the same time, it solves the difficult problem of level conversion of narrow pulses between the low-voltage phase frequency detector and the high-voltage charge pump in traditional practices at a very low cost, improves the linearity of the charge pump and thus improves the overall jitter of the phase-locked loop. In addition, due to the use of a high-voltage charge pump, this structure effectively increases the output voltage range of the charge pump, thereby reducing Kvco (the voltage-controlled gain of the voltage-controlled oscillator) to further reduce the overall loop jitter.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular to a low-noise phase-locked loop circuit structure. Background Art

[0002] Phase-locked loop (PLL) circuits are widely used in various chips and are an integral part of RF circuits. The phase noise and jitter performance of their output clock signals determine the spectral purity of the local oscillator (LO) signal, and thus the overall RF system performance. Applications such as high-order QAM communications and radar place extremely high demands on the PLL's in-band phase noise. This in-band noise is limited by modules such as the charge pump and the phase frequency detector (PFD). Therefore, to achieve superior noise performance, high-voltage transistors are often considered for charge pump design. Charge pumps implemented with high-voltage power supplies typically have lower current mismatch and a wider output tuning voltage range than low-voltage charge pumps. However, since modules such as frequency dividers typically use low-voltage power supplies, a level shifter is often required to properly drive the high-voltage charge pump. The current mainstream implementation involves adding a level shifter after the PFD to convert the low-voltage control signal to a high-voltage control signal to control the high-voltage charge pump. However, because the pulse width of the control signal output by the PFD when the PLL is locked is too narrow to meet the conversion time of the level shifter circuit, this narrow pulse width causes the level shifter module to output a quasi-triangular wave, rendering it inoperative. This quasi-triangular wave increases the charge pump mismatch current and nonlinearizes the charge pump gain, degrading the overall circuit's noise performance. Therefore, how to properly design the PLL circuit to avoid the noise degradation caused by the level shifter module has become a pressing issue.

[0003] like Figure 5 The figure shows a phase-locked loop circuit structure from the document "Y.Fu, L.Li and D.Wang, Design of Improved PhaseFrequency Detector and Charge-Pump for a 12-18GHz CMOS PLL, 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology [J], 2018, pp. 1-3". This structure uses a high-speed level conversion circuit to connect the phase frequency detector. The circuit uses a capacitor bootstrap method to increase the level conversion rate, but this solution cannot fundamentally solve the above-mentioned nonlinear problem. When the output pulse width of the phase frequency detector is too small, it will still cause the noise performance to deteriorate. At the same time, the circuit stability is reduced due to the presence of the bootstrap capacitor. The output phase noise of this structure is compared with that of the level conversion module of the present invention. Figure 6 shown. Summary of the Invention

[0004] In response to the above-mentioned existing problems, the present invention proposes a low-noise phase-locked loop circuit structure, which fully utilizes the device characteristic that high-voltage tube noise is better than low-voltage tube noise under advanced technology, maximizes the reduction of frequency detector and charge pump noise, and solves the difficult problem of level conversion of narrow pulses between low-voltage frequency detector and high-voltage charge pump in traditional practices, improves the linearity of the charge pump and thus improves the noise performance of the overall loop.

[0005] To achieve the above-mentioned purpose, a low-noise phase-locked loop circuit structure of the present invention adopts the following technical solutions:

[0006] A low-noise phase-locked loop circuit structure controls the frequency and phase of the output clock based on an external reference clock signal CLKREF and a feedback clock signal CLKFB, and provides a controlled reference clock signal for subsequent circuits. The circuit structure includes a first level conversion module, a second level conversion module, a high-voltage phase frequency detector (PFD), a high-voltage charge pump module, a loop filter, a voltage-controlled oscillator (VCO), and a duty cycle expansion divider. The reference clock signal CLKREF is connected to the input of the first level conversion module, and the feedback clock signal CLKFB is connected to the input of the second level conversion module for high-to-low level conversion. The outputs of the first and second level conversion modules are connected to the first and second inputs of the high-voltage phase frequency detector (PFD), respectively, for phase and frequency comparison. A control signal for the high-voltage charge pump is directly generated based on the frequency and phase differences. The first and second outputs of the high-voltage phase frequency detector are connected to the first and second inputs of the high-voltage charge pump, respectively. The output of the high-voltage charge pump is connected to the input of the loop filter. The loop filter output is connected to the input of a voltage-controlled oscillator (VCO). This module generates the VCO's modulation voltage by charging and discharging according to the high-voltage charge pump control signal. The VCO output is connected to the input of a duty-cycle frequency divider, which in turn is connected to the input of a second level-shifting module as the CLKFB input. The VCO module output serves as the output of the phase-locked loop circuit, providing a reference clock signal for subsequent circuits.

[0007] Furthermore, the level conversion module includes a first MOS tube (M1), a second MOS tube (M2), a third MOS tube (M3), a fourth MOS tube (M4), a fifth MOS tube (M5), a sixth MOS tube (M6), a seventh MOS tube (M7), an eighth MOS tube (M8), a ninth MOS tube (M9), a tenth MOS tube (M10), an eleventh MOS tube (M11), a twelfth MOS tube (M12), and a voltage source (VB); the source of the first MOS tube (M1), the source of the second MOS tube (M2), the source of the ninth MOS tube (M9), and the source of the eleventh MOS tube (M11) are connected to the power supply, the gate of the first MOS tube (M1) is connected to the drain of the fourth MOS tube (M4), the drain of the sixth MOS tube (M6), the gate of the ninth MOS tube (M9), and the gate of the tenth MOS tube (M10), the gate of the second MOS tube (M2) is connected to the drain of the third MOS tube (M3), the drain of the fifth MOS tube (M5), and the gate of the eleventh MOS tube (M11). The gate of the eleventh MOS tube (M11), the gate of the twelfth MOS tube (M12), the drain of the first MOS tube (M1) are connected to the source of the third MOS tube (M3), the drain of the second MOS tube (M2) is connected to the source of the fourth MOS tube (M4), the gate of the fifth MOS tube (M5) and the gate of the sixth MOS tube (M6) are connected to the voltage source VB, the gate of the seventh MOS tube (M7) and the gate of the third MOS tube (M3) are connected to the non-inverting input terminal VIN, and the eighth MOS tube (M8) is connected to the positive input terminal VIN. ) and the gate of the fourth MOS transistor (M4) are connected to the inverting input terminal VINB, the drain of the ninth MOS transistor (M9) and the drain of the tenth MOS transistor (M10) are connected to the inverting output terminal VOB, the drain of the eleventh MOS transistor (M11) and the drain of the twelfth MOS transistor (M12) are connected to the non-inverting output terminal VO, and the source of the seventh MOS transistor (M7), the source of the eighth MOS transistor (M8), the source of the tenth MOS transistor (M10) and the source of the twelfth MOS transistor (M12) are grounded.

[0008] Furthermore, the fifth MOS tube and the sixth MOS tube in the level conversion module are low-voltage tubes.

[0009] Furthermore, the voltage conversion range of the first level conversion module and the second level conversion module is from the power supply voltage of the frequency divider to the operating voltage of the high-voltage phase frequency detector and the high-voltage charge pump.

[0010] Furthermore, the DFF circuit inside the high-voltage phase and frequency detector module adopts a TSPC structure, and the operating voltage is consistent with the high-voltage charge pump.

[0011] Furthermore, when the frequency division ratio of the duty cycle expansion divider is N, the duty cycle of the output feedback clock signal is approximately 50%.

[0012] Compared with the prior art, the present invention has the following beneficial effects:

[0013] First: It solves the problem of overall jitter reduction caused by narrow pulse level conversion between the traditional structure frequency detector and charge pump.

[0014] Second: It makes full use of the device characteristics of high-voltage tube noise being better than low-voltage tube noise under advanced technology to maximize the reduction of frequency detector and charge pump noise.

[0015] Third: It effectively improves the output voltage range of the charge pump, thereby reducing Kvco (voltage-controlled gain of the voltage-controlled oscillator) to further reduce the overall loop jitter.

[0016] Fourth: It avoids the nonlinearity of the charge pump caused by the traditional practice of level conversion of narrow pulses between the low-voltage phase frequency detector and the high-voltage charge pump, thereby improving the linearity of the charge pump. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the existing traditional phase-locked loop circuit structure;

[0018] Figure 2 A schematic diagram of a low-noise phase-locked loop circuit structure of the present invention;

[0019] Figure 3 This is a schematic diagram of the structure of the level conversion module of the present invention;

[0020] Figure 4 This is a schematic structural diagram of a high-voltage frequency and phase detector according to the present invention;

[0021] Figure 5 This is a phase-locked loop circuit structure diagram described in the document ICSICT2018.

[0022] Figure 6 A comparison of the phase noise between the level conversion module described in the present invention and the level conversion module described in the ICSICT2018 document DETAILED DESCRIPTION

[0023] The technical solution of the present invention is described in detail below with reference to specific implementation methods and accompanying drawings.

[0024] Example 1: Figure 1 The following diagram shows the structure of a conventional phase-locked loop circuit. This structure incorporates a level shifter circuit after a low-voltage phase-frequency detector (PFD) to drive a high-voltage charge pump. As shown in the figure, after the circuit stabilizes, the outputs of both the frequency divider and the low-voltage phase-frequency detector are narrow pulse signals. This results in a triangular-like output from the level shifter circuit, degrading the charge pump's linearity and, in turn, affecting the circuit's noise performance.

[0025] like Figure 2As shown, a low-noise phase-locked loop circuit structure of the present invention includes a first level conversion module 11, a second level conversion module 12, a high-voltage phase frequency detector 13, a high-voltage charge pump module 14, a loop filter 15, a voltage-controlled oscillator 16, and a duty cycle expansion divider 17. The reference clock signal CLKREF is connected to the input terminal 111 of the first level conversion module, and the feedback clock signal CLKFB is connected to the input terminal 121 of the second level conversion module for high-to-low level conversion. The output 112 of the first level conversion module and the output 122 of the second level conversion module are respectively connected to the first input terminal 131 and the second input terminal 132 of the high-voltage phase frequency detector 13 for phase and frequency comparison. The control signal for the high-voltage charge pump is directly generated based on the frequency and phase differences. The first output terminal 133 and the second output terminal 134 of the high-voltage phase frequency detector are respectively connected to the first input terminal 141 and the second input terminal 142 of the high-voltage charge pump 14. The high-voltage charge pump output terminal 143 is connected to the input terminal 151 of the loop filter 15. The loop filter output 152 is connected to the input 161 of the voltage-controlled oscillator 16. This module generates the modulation voltage of the voltage-controlled oscillator by charging and discharging according to the high-voltage charge pump control signal. The voltage-controlled oscillator output 162 is connected to the input 171 of the duty cycle expansion divider 17. The duty cycle expansion divider output 172 is connected to the input 121 of the second level conversion module 12 as the CLKFB input. The voltage-controlled oscillator module output 162 serves as the output of the phase-locked loop circuit, providing a reference clock signal for subsequent circuits.

[0026] The level conversion module includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, and a voltage source VB; the source of the first MOS transistor M1, the source of the second MOS transistor M2, the source of the ninth MOS transistor M9, and the source of the eleventh MOS transistor M11 are connected to the power supply, the gate of the first MOS transistor M1 is connected to the drain of the fourth MOS transistor M4, the drain of the sixth MOS transistor M6, the gate of the ninth MOS transistor M9, and the gate of the tenth MOS transistor M10, the gate of the second MOS transistor M2 is connected to the drain of the third MOS transistor M3, the drain of the fifth MOS transistor M5, and the drain of the eleventh MOS transistor M11. The gate of the seventh MOS transistor M7 and the gate of the third MOS transistor M3 are connected to the non-inverting input terminal VIN, the gate of the eighth MOS transistor M8 and the gate of the fourth MOS transistor M4 are connected to the inverting input terminal VINB, the drain of the ninth MOS transistor M9 and the drain of the tenth MOS transistor M10 are connected to the inverting output terminal VOB, the drain of the eleventh MOS transistor M11 and the drain of the twelfth MOS transistor M12 are connected to the non-inverting output terminal VO, and the source of the seventh MOS transistor M7, the source of the eighth MOS transistor M8, the source of the tenth MOS transistor M10, and the source of the twelfth MOS transistor M12 are grounded.

[0027] Among them, the fifth MOS tube and the sixth MOS tube of the level conversion module are low-voltage tubes.

[0028] The voltage conversion range of the first level conversion module and the second level conversion module is from the power supply voltage of the frequency divider to the operating voltage of the high-voltage phase frequency detector and the high-voltage charge pump.

[0029] Among them, such as Figure 4 As shown in FIG, the internal DFF circuit of the high-voltage phase and frequency detector module adopts a TSPC structure, and the operating voltage is consistent with the high-voltage charge pump.

[0030] When the frequency division ratio of the duty cycle expansion frequency divider is N, the duty cycle of the output feedback clock signal is approximately 50%.

[0031] The circuit structure principle of a low-noise phase-locked loop of the present invention is as follows:

[0032] The output clock signal is passed through a duty-cycle expansion divider to generate a feedback clock signal CLKFB with a duty cycle of approximately 50%. This avoids the narrow pulses typically seen in conventional phase-locked loops (PLLs) when the divider ratio is high. The feedback clock signal CLKFB and the reference clock signal CLKREF are converted into high-voltage clock signals via a first level conversion module and a second level conversion module, respectively. Neither CLKFB nor CLKREF is a narrow pulse signal. The converted high-voltage clock signal is then compared with its phase and frequency by a high-voltage phase frequency detector (PFD). This PFD directly generates the control signal for the high-voltage charge pump based on the frequency and phase differences. This high-voltage signal requires no further level conversion, thus avoiding the difficulty encountered by the level conversion module in conventional designs in converting narrow pulses. Furthermore, the use of a TSPC phase detector eliminates the significant delay and dead time issues associated with high-voltage devices, further reducing charge pump noise. The charge pump output is charged and discharged through a loop filter to generate a modulation voltage for the voltage-controlled oscillator (VCO). Based on the modulation voltage, the VCO generates an output clock signal with the corresponding frequency and phase.

[0033] The advantages of the circuit proposed in this article are:

[0034] First: It solves the problem of overall jitter reduction caused by narrow pulse level conversion between the traditional structure frequency detector and charge pump.

[0035] Second: It makes full use of the device characteristics of high-voltage tube noise being better than low-voltage tube noise under advanced technology to maximize the reduction of frequency detector and charge pump noise.

[0036] Third: It effectively improves the output voltage range of the charge pump, thereby reducing Kvco (voltage-controlled gain of the voltage-controlled oscillator) to further reduce the overall loop jitter.

[0037] Fourth: It avoids the nonlinearity of the charge pump caused by the traditional practice of level conversion of narrow pulses between the low-voltage phase frequency detector and the high-voltage charge pump, thereby improving the linearity of the charge pump.

[0038] As described above, although the present invention has been shown and described with reference to specific preferred embodiments, it should not be construed as limiting the present invention itself. Various changes may be made to it in form and detail without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A low-noise phase-locked loop circuit structure that controls the frequency and phase of an output clock based on an external reference clock signal CLKREF and a feedback clock signal CLKFB, and provides a controlled reference clock signal to subsequent circuits, characterized in that: The invention comprises a first level conversion module (11), a second level conversion module (12), a high-voltage phase and frequency detector (13), a high-voltage charge pump module (14), a loop filter (15), a voltage-controlled oscillator (16), and a duty cycle expansion divider (17), wherein the reference clock signal CLKREF is connected to the input end (111) of the first level conversion module, and the feedback clock signal CLKFB is connected to the input end (121) of the second level conversion module for high-low level conversion, the output (112) of the first level conversion module and the output (122) of the second level conversion module are respectively connected to the first input end (131) and the second input end (132) of the high-voltage phase and frequency detector (13) for phase and frequency comparison, and a control signal of the high-voltage charge pump is directly generated according to the frequency difference and the phase difference, and the first output end (111) of the high-voltage phase and frequency detector is connected to the first output end (111) of the high-voltage phase and frequency detector. 33) and the second output end (134) are respectively connected to the first input end (141) and the second input end (142) of the high-voltage charge pump (14); the high-voltage charge pump output end (143) is connected to the input end (151) of the loop filter (15); the loop filter output end (152) is connected to the input end (161) of the voltage-controlled oscillator (16); the module is charged and discharged according to the high-voltage charge pump control signal to generate a modulation voltage of the voltage-controlled oscillator; the voltage-controlled oscillator output end (162) is connected to the input end (171) of the duty cycle expansion divider (17); the duty cycle expansion divider output end (172) is connected to the input end (121) of the second level conversion module (12) as the CLKFB input; the voltage-controlled oscillator output end (162) serves as the output end of the phase-locked loop circuit to provide a reference clock signal for subsequent circuits.

2. A low-noise phase-locked loop circuit structure according to claim 1, characterized in that: The level conversion module comprises a first MOS tube (M1), a second MOS tube (M2), a third MOS tube (M3), a fourth MOS tube (M4), a fifth MOS tube (M5), a sixth MOS tube (M6), a seventh MOS tube (M7), an eighth MOS tube (M8), a ninth MOS tube (M9), a tenth MOS tube (M10), an eleventh MOS tube (M11), a twelfth MOS tube (M12), and a voltage source (VB); the source of the first MOS tube (M1), the source of the second MOS tube (M2), the source of the ninth MOS tube (M9), and the source of the eleventh MOS tube (M11) are connected to the power supply, the gate of the first MOS tube (M1) is connected to the drain of the fourth MOS tube (M4), the drain of the sixth MOS tube (M6), the gate of the ninth MOS tube (M9), and the gate of the tenth MOS tube (M10), and the gate of the second MOS tube (M2) is connected to the drain of the third MOS tube (M3), the drain of the fifth MOS tube (M5), and the drain of the eleventh MOS tube (M11). The gate of the S tube (M11), the gate of the twelfth MOS tube (M12), the drain of the first MOS tube (M1) are connected to the source of the third MOS tube (M3), the drain of the second MOS tube (M2) is connected to the source of the fourth MOS tube (M4), the gate of the fifth MOS tube (M5) and the gate of the sixth MOS tube (M6) are connected to the voltage source (VB), the gate of the seventh MOS tube (M7) and the gate of the third MOS tube (M3) are connected to the in-phase input terminal VIN, and the eighth MOS tube (M8) is connected to the in-phase input terminal VIN. The gate of the fourth MOS tube (M4) is connected to the inverting input terminal VINB, the drain of the ninth MOS tube (M9) and the drain of the tenth MOS tube (M10) are connected to the inverting output terminal VOB, the drain of the eleventh MOS tube (M11) and the drain of the twelfth MOS tube (M12) are connected to the non-inverting output terminal VO, and the source of the seventh MOS tube (M7), the source of the eighth MOS tube (M8), the source of the tenth MOS tube (M10) and the source of the twelfth MOS tube (M12) are grounded.

3. A low-noise phase-locked loop circuit structure according to claim 1, characterized in that: The fifth MOS tube and the sixth MOS tube of the level conversion module are low-voltage tubes.

4. A low-noise phase-locked loop circuit structure according to claim 1, characterized in that: The voltage conversion range of the first level conversion module and the second level conversion module is from the power supply voltage of the frequency divider to the operating voltage of the high-voltage phase frequency detector and the high-voltage charge pump.

5. The low-noise phase-locked loop circuit structure according to claim 1, wherein: The DFF circuit inside the high-voltage phase and frequency detector module adopts a TSPC structure, and its operating voltage is consistent with that of the high-voltage charge pump.

6. A low-noise phase-locked loop circuit structure according to claim 1, characterized in that: The duty cycle expansion divider outputs a feedback clock signal with a duty cycle of 50% when the frequency division ratio is N.

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