Time-interleaved analog-to-digital converter

Abstract

The present disclosure relates to time-interleaved analog-to-digital converters. A time-interleaved analog-to-digital converter operates in a first mode or a second mode and includes M analog-to-digital converters, a reference analog-to-digital converter, a digital correction circuit, and a control circuit, M being an integer greater than one. The M analog-to-digital converters sample an input signal according to M enable signals to generate M digital output codes. The reference analog-to-digital converter samples the input signal according to a reference enable signal to generate a reference digital output code. The digital correction circuit corrects the M digital output codes to generate M corrected digital output codes. The control circuit generates the M enable signals and the reference enable signal according to a clock.

Description

Technical Field

[0001] This invention relates to a time-interleaved analog-to-digital converter (TIADC), and more particularly to the suppression of timing skew tone caused by sampling timing skew in a TIADC. Background Technology

[0002] A time-interleaved ADC comprises multiple sub-analog-to-digital converters (ADCs). Each sub-ADC samples the input signal according to a sampling clock with the same frequency but different phase, and generates its own digital output code in turn, which serves as the output of the time-interleaved ADC. For example, when a time-interleaved ADC comprises four sub-ADCs (ADC1, ADC2, ADC3, and ADC4), and samples the input signal sequentially in the order ADC1→ADC2→ADC3→ADC4→ADC1→ADC2→…, then the phase difference between the sampling clocks of ADC1 and ADC2 is 90 degrees, the phase difference between the sampling clocks of ADC2 and ADC3 is 90 degrees, the phase difference between the sampling clocks of ADC3 and ADC4 is 90 degrees, and the phase difference between the sampling clocks of ADC4 and ADC1 is 90 degrees. If the operating clock frequency of the time-interleaved ADC is fs (i.e., the time-interleaved ADC outputs a digital output code every 1 / fs seconds), then the sampling clock frequency of ADC1, ADC2, ADC3 and ADC4 is fs / 4.

[0003] Due to factors such as trace length and component mismatch, the phase difference between the sampling clocks of sub-analog-to-digital converters ADC2, ADC3, and ADC4 and the sampling clock of sub-analog-to-digital converter ADC1 will not be exactly 90 degrees, 180 degrees, and 270 degrees, respectively, but rather 90+x degrees, 180+y degrees, and 270+z degrees (where x, y, and z are rational numbers). The literature "Behzad Razavi. Design Considerations for Interleaved ADCs. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.48, NO.8, AUGUST 2013" provides a method for obtaining the values ​​of x, y, and z.

[0004] A conventional method for correcting time-interleaved ADCs uses three filters to adjust the digital output codes of sub-analog-to-digital converters ADC2, ADC3, and ADC4 respectively based on the values ​​of x, y, and z, to compensate for or correct errors caused by phase errors (i.e., x, y, z). One drawback of this method is its slow convergence speed. Another drawback is that the corrected time-interleaved ADC often exhibits residual time skew tone, gain tone, and offset tone in the frequency domain. The most difficult to handle is the residual time skew tone, which is caused by the fact that the phase difference of the corrected sampling clock is not 90 degrees, 180 degrees, or 270 degrees. For example, the equivalent phase differences after correction are 90 + x1 degrees, 180 + y1 degrees, and 270 + z1 degrees, where x1, y1, and z1 are residual values. Undesired time skew tones occur because the residual values ​​x1, y1, and z1 are non-zero constants. Undesired time skew tones will cause a decrease in the quality of time-interleaved ADCs and may even cause other circuits to malfunction. Summary of the Invention

[0005] In view of the shortcomings of the prior art, one of the objectives of the present invention is to provide a time-interleaved analog-to-digital converter to improve upon the shortcomings of the prior art.

[0006] One embodiment of the present invention provides a time-interleaved analog-to-digital converter (ADC) operating in a first mode or a second mode, comprising: M ADCs, a reference ADC, a digital correction circuit, and a control circuit. The M ADCs sample the input signal according to M enable signals to generate M digital output codes, where M is an integer greater than 1. The reference ADC samples the input signal according to a reference enable signal to generate a reference digital output code. The digital correction circuit corrects the M digital output codes to generate M corrected digital output codes. The control circuit generates the M enable signals and the reference enable signal according to a clock. In the first mode, the control circuit outputs the M corrected digital output codes in turn, but does not output the reference digital output code. In the second mode, the control circuit randomly outputs the M corrected digital output codes and the reference digital output code.

[0007] Another embodiment of the present invention provides a time-interleaved analog-to-digital converter (ADC) operating in a first mode or a second mode for converting an input signal into a digital output signal. The ADC includes: a first ADC, a second ADC, a third ADC, a fourth ADC, a reference ADC, a digital correction circuit, and a control circuit. The first ADC receives the input signal and samples the input signal according to a first enable signal to generate a first digital output code. The second ADC receives the input signal and samples the input signal according to a second enable signal to generate a second digital output code. The third ADC receives the input signal and samples the input signal according to a third enable signal to generate a third digital output code. The fourth ADC receives the input signal and samples the input signal according to a fourth enable signal to generate a fourth digital output code. The reference ADC receives the input signal and samples the input signal according to a reference enable signal to generate a reference digital output code. A digital correction circuit is used to correct the first digital output code, the second digital output code, the third digital output code, and the fourth digital output code to generate a first corrected digital output code, a second corrected digital output code, a third corrected digital output code, and a fourth corrected digital output code, respectively. A control circuit is used to generate a first enable signal, a second enable signal, a third enable signal, a fourth enable signal, and a reference enable signal according to a clock. In the first mode, the digital output signal is selected from a group of first digital output codes including the first corrected digital output code, the second corrected digital output code, the third corrected digital output code, and the fourth corrected digital output code. In the second mode, the digital output signal is selected from a group of second digital output codes including the first corrected digital output code, the second corrected digital output code, the third corrected digital output code, the fourth corrected digital output code, and the reference digital output code.

[0008] The time-interleaved ADC of this invention can suppress time skew tone, gain tone and bias tone, and can accelerate convergence speed.

[0009] The features, implementation, and effects of this invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0010] Figure 1 This is a functional block diagram of an embodiment of the time-interleaved ADC of the present invention;

[0011] Figure 2 This is a functional block diagram of another embodiment of the time-interleaved ADC of the present invention;

[0012] Figure 3 This is a timing diagram of the enable signal of the time-interleaved ADC of the present invention in the first mode;

[0013] Figure 4 Displays the calibration target and digital output signal of the digital calibration circuit;

[0014] Figure 5 This is a timing diagram of the enable signal of the time-interleaved ADC of the present invention in the second mode;

[0015] Figure 6 Display candidate values ​​and the digital output signal; and

[0016] Figure 7 This is a functional block diagram of one embodiment of the control circuit. Detailed Implementation

[0017] The technical terms used in the following description refer to the common terms in this technical field. If this specification provides explanations or definitions for certain terms, the explanations or definitions in this specification shall prevail.

[0018] The disclosure of this invention includes a time-interleaved analog-to-digital converter. Since some components of the time-interleaved analog-to-digital converter of this invention may be known individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the device invention.

[0019] Figure 1 This is a functional block diagram of an embodiment of the time-interleaved ADC of the present invention. The time-interleaved ADC 100 includes M ADCs 110 (including ADC 110_1, ADC 110_2, ..., ADC 110_M, where M is an integer greater than 1), a reference ADC 115, a digital correction circuit 120, a control circuit 130, and a demultiplexer (DEMUX) 140. ADCs 110 and the reference ADC 115 receive the input signal Vin. The digital correction circuit 120 is coupled to ADCs 110, the control circuit 130, and the demultiplexer 140. The demultiplexer 140 is coupled to the reference ADC 115, the digital correction circuit 120, and the control circuit 130.

[0020] ADC 110_1 samples the input signal Vin based on the enable signal EN_1 and generates a digital output code D_1; ADC 110_2 samples the input signal Vin based on the enable signal EN_2 and generates a digital output code D_2; ADC 110_M samples the input signal Vin based on the enable signal EN_M and generates a digital output code D_M. Reference ADC 115 samples the input signal Vin based on the reference enable signal EN_R and generates a reference digital output code D_R.

[0021] Digital correction circuit 120 corrects digital output codes D_1, D_2, ..., D_M to generate corrected digital output codes D_1', D_2', ..., D_M', respectively. These M corrected digital output codes form a first digital output code group G_1. These M corrected digital output codes and a reference digital output code D_R form a second digital output code group G_2. Digital correction circuit 120 corrects the skew tone, gain tone, and bias tone caused by mismatches among the M ADCs 110. In some embodiments, digital correction circuit 120 includes multiple filters, and the digital correction circuit 120 improves its correction effect by adjusting the coefficients of these filters; adjusting or correcting digital output codes using filters is well known to those skilled in the art and will not be described in detail here. In some cases, if digital output code D_k does not need correction, then the corrected digital output code D_k' is equal to the digital output code D_k (1 ≦ k ≦ M).

[0022] The control circuit 130 receives the first digital output code group G_1 and the second digital output code group G_2, outputs the digital output signal Dout, and generates the M enable signals (EN_1, EN_2, ..., EN_M) and the reference enable signal EN_R according to the clock CK.

[0023] The demultiplexer 140 receives the reference digital output code D_R and outputs the reference digital output code D_R to the digital correction circuit 120 or the control circuit 130 according to the selection signal SEL_1.

[0024] The time-interleaved ADC 100 operates in either the first or second mode. Figure 2 This invention demonstrates a time-interleaved ADC when M=4. The following is in conjunction with... Figures 2-6 Taking M=4 as an example, the first and second modes of the time-interleaved ADC of the present invention are explained.

[0025] In the first mode, the control circuit 130 controls the demultiplexer 140 to output a reference digital output code D_R to the digital correction circuit 120 using the selection signal SEL_1. The digital correction circuit 120 corrects M digital output codes (D_1', D_2', ..., D_M) based on the reference digital output code D_R to generate M corrected digital output codes (D_1', D_2', ..., D_M'). The control circuit 130 then selects one corrected digital output code from the first digital output code group G_1 and outputs it as the digital output signal Dout. In some embodiments, when the digital correction circuit 120 is implemented with multiple filters, the digital correction circuit 120 continuously adjusts the coefficients of these filters in the first mode.

[0026] Please see Figures 2-4 . Figure 3This is a timing diagram of the enable signal of the time-interleaved ADC 100 of the present invention in the first mode. Figure 4 The digital calibration circuit 120 displays the calibration target. The clock CK has a period of T, and the enable signals EN_1, EN_2, EN_3, and EN_4 all have periods of 4T, while the reference enable signal EN_R has a period of 5T. When the reference enable signal EN_R aligns with a certain enable signal, the digital calibration circuit 120 calibrates the ADC corresponding to that enable signal. Figure 3 and Figure 4 In the example, the digital correction circuit 120 corrects ADC 110_1, ADC 110_2, ADC 110_3 and ADC 110_4 at time points t3, t8, t13 and t18 (not shown) respectively according to the reference digital output code D_R, while the control circuit 130 periodically outputs digital output codes D_1'→D_2'→D_3'→D_4'→D_1'→D_2', ... as digital output signals Dout in sequence (i.e., in turn).

[0027] In the first mode, the period of the reference enable signal EN_R is greater than the period of the M enable signals (EN_1, EN_2, ..., EN_M). In some embodiments, the period of the M enable signals is P units, and the period of the reference enable signal EN_R is Q units, where P and Q are both integers and coprime.

[0028] In the second mode, the control circuit 130 controls the demultiplexer 140 to output a reference digital output code D_R to the control circuit 130 via the selection signal SEL_1, and the control circuit 130 selects a digital output code from the second digital output code group G_2 and outputs it as a digital output signal Dout.

[0029] Please see Figure 2 , Figure 5 and Figure 6 . Figure 5 This is a timing diagram of the enable signal of the time-interleaved ADC 100 of the present invention in the second mode. Figure 6 Displays the candidate ADCs and the selected ADC.

[0030] Control circuit 130 generates enable signals EN_1, EN_2, EN_3, EN_4, and a reference enable signal EN_R based on clock CK. These enable signals exhibit an irregular pattern. In some embodiments, control circuit 130 generates these enable signals in a pseudo-random manner, which will be used in conjunction with the following... Figure 6 Detailed explanation.

[0031] Please also refer to Figure 5 and Figure 6 At time point t1, the candidate ADCs are ADC 110_4 and reference ADC 115. The control circuit 130 selects one of them based on a pseudo-random method (in...). Figure 6 In the example, ADC 110_4 is selected, so in Figure 5 The energizing signal EN_4 is at a high level at time t1; at time t2, the candidate ADCs are ADC 110_1 and the reference ADC 115, and the control circuit 130 selects one of them based on a pseudo-random method (in... Figure 6 In the example, ADC 110_1 is selected, so in Figure 5 (EN_1 is at a high level at time t2); and so on.

[0032] Continuing from above. Over a long period of time, the digital output signal Dout will exhibit a random pattern (for example, corresponding to...). Figure 5 The timing sequence is Dout = D_4'→D_1'→D_2'→D_3'→D_R→D_1'→D_2'→D_4'→D_3'→D_R→D_2'→D_1'→D_3'→D_R→…), rather than a fixed pattern (e.g., D_1'→D_2'→D_3'→D_4'→D_1'→D_2'→D_3'→…). This is equivalent to the control circuit 130 randomly outputting the M correction digital output codes and the reference digital output code D_R as the digital output signal Dout in the second mode. The random digital output signal Dout helps to suppress time skew tone and improve the quality of the time-interleaved ADC 100. For the implementation of pseudo-randomness, please refer to: https: / / en.wikipedia.org / wiki / Pseudorandom_generator.

[0033] Figure 7 This is a functional block diagram of one embodiment of the control circuit 130. The control circuit 130 includes a selection circuit 132 (e.g., a multiplexer (MUX)), a control unit 134, and a clock generation circuit 136. The control unit 134 is coupled to the selection circuit 132 and the clock generation circuit 136.

[0034] The selection circuit 132 receives either a first digital output code group G_1 (corresponding to the first mode) or a second digital output code group G_2 (corresponding to the second mode), and outputs a correction digital output code as a digital output signal Dout from the first digital output code group G_1 (when the time-interleaved ADC 100 operates in the first mode) or outputs a digital output code as a digital output signal Dout from the second digital output code group G_2 (when the time-interleaved ADC 100 operates in the second mode) according to the selection signal SEL_2 generated by the control unit 134.

[0035] The clock generation circuit 136 generates M enable signals (EN_1, EN_2, ..., EN_M) and a reference enable signal EN_R based on the clock CK and the control signal Ctrl. More specifically, in a first mode, the control unit 134 controls the clock generation circuit 136 with the control signal Ctrl, such that the period of the reference enable signal EN_R is not equal to the period of the M enable signals (e.g., the period of the M enable signals is M*T, while the period of the reference enable signal EN_R is (M+1)*T); in a second mode, the control unit 134 controls the clock generation circuit 136 with the control signal Ctrl, such that the M enable signals and the reference enable signal EN_R do not have a fixed period (i.e., exhibiting a pseudo-random pattern). In some embodiments, the clock generation circuit 136 can be implemented by a phase interpolator. The use of a phase interpolator to generate and / or adjust multiple clocks is well known to those skilled in the art and will not be described further.

[0036] In some embodiments, the control unit 134 adjusts the selection signal SEL_1 and the control signal Ctrl according to the indication signal CF generated by the digital correction circuit 120 to control the time-interleaved ADC 100 to operate in a first mode or a second mode. For example, when the indication signal CF indicates that the error amount of at least one of the M corrected digital output codes is less than a threshold, the control circuit 130 controls the time-interleaved ADC 100 to operate in the second mode.

[0037] In some embodiments, when the time-interleaved ADC 100 operates in a first mode, the control circuit 130 controls the digital correction circuit 120 to update the filter coefficients using the control signal DSB; and when the time-interleaved ADC 100 operates in a second mode, the control circuit 130 controls the digital correction circuit 120 to stop updating the filter coefficients using the control signal DSB. Note that although the digital correction circuit 120 stops updating the filter coefficients in the second mode, the current filter coefficients can still be used to correct the M digital output codes (D_1, D_2, ..., D_M).

[0038] The following examples illustrate the timing points or conditions under which the control circuit 130 controls the switching modes of the time-interleaved ADC 100.

[0039] In the first embodiment, the control circuit 130 determines whether the time for which the time-interleaved ADC 100 operates in the first mode is greater than a first threshold. If it is (meaning that the coefficients of the filter in the digital correction circuit 120 do not need to be adjusted or updated), the control circuit 130 controls the time-interleaved ADC 100 to operate in the second mode. The control circuit 130 may use a timer or a counter to time this.

[0040] In the second embodiment, the control circuit 130 determines whether the error amount of the corrected digital output codes D_1', D_2', ..., D_M' is less than a second threshold. If so (meaning that the coefficients of the filter of the digital correction circuit 120 do not need to be adjusted or updated), the control circuit 130 controls the time-interleaved ADC 100 to operate in the second mode.

[0041] In the third embodiment, the control circuit 130 performs a Fast Fourier Transform (FFT) on the digital output signal Dout and determines whether the result of the FFT is greater than a third threshold. If it is (meaning that the digital output signal Dout has become more accurate), the control circuit 130 controls the time-interleaved ADC 100 to operate in the second mode; otherwise, the control circuit 130 controls the time-interleaved ADC 100 to operate in the first mode.

[0042] In the fourth embodiment, the control circuit 130 determines whether the operating voltage and / or ambient temperature of the time-interleaved ADC 100 have changed. If so (meaning that the coefficients of the filter in the digital correction circuit 120 may need to be readjusted or updated), the control circuit 130 controls the time-interleaved ADC 100 to operate in the first mode; otherwise, the control circuit 130 controls the time-interleaved ADC 100 to operate in the second mode.

[0043] Those skilled in the art can design the control unit 134 based on the above disclosure. That is, the control unit 134 can be an application-specific integrated circuit (ASIC) or implemented by circuits or hardware such as a programmable logic device (PLD).

[0044] The time-interleaved ADC of the present invention can operate in either a first mode or a second mode and includes a reference ADC. In the second mode, the reference ADC can be used to implement "pseudo-randomization" to suppress time-skewed tones; in the first mode, the reference ADC can be used to correct other ADCs (e.g., correct gain tone and bias tone) to accelerate the convergence of the time-interleaved ADC (compared to the time-interleaved ADC which only implements the second mode).

[0045] Please note that the shapes, sizes, and proportions of the components in the aforementioned illustrations are merely illustrative and intended to help those skilled in the art understand the invention, and are not intended to limit the invention. Furthermore, in some embodiments, the order of the steps mentioned in the aforementioned flowcharts may be adjusted according to actual operation, and they may even be performed simultaneously or partially simultaneously.

[0046] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application in this specification.

[0047] Symbol Explanation

[0048] 100: Time-Interleaved Analog-to-Digital Converter

[0049] 110_1, 110_2, 110_3, 110_4, 110_M: Analog-to-digital converters

[0050] 115: Reference Analog-to-Digital Converter

[0051] 120: Digital correction circuit

[0052] 130: Control Circuit

[0053] 140: Demultiplexer (DEMUX)

[0054] EN_1, EN_2, EN_3, EN_4, EN_M, EN_R: enable signal

[0055] Vin: Input signal

[0056] D_1, D_2, D_3, D_4, D_M: Digital output codes

[0057] D_R: Reference digital output code

[0058] D_1', D_2', D_3', D_4', D_M': Correction digital output codes

[0059] G_1: First Digital Output Code Group

[0060] G_2: Second digital output code group

[0061] CK: Clock

[0062] CF: Indicator Signal

[0063] SEL_1, SEL_2: Selection signals

[0064] Dout: Digital output signal

[0065] T: Period

[0066] t1~t15: Time points

[0067] 132: Selection Circuit

[0068] 134: Control Unit

[0069] 136: Clock Generation Circuit

[0070] Ctrl, DSB: Control signals

Claims

1. A time-interleaved analog-to-digital converter operating in a first mode or a second mode, comprising: M analog-to-digital converters sampling an input signal according to M enable signals to generate M digital output codes, M being an integer greater than 1; a reference analog-to-digital converter sampling the input signal according to a reference enable signal to generate a reference digital output code; and a digital correction circuit for correcting the M digital output codes to produce M corrected digital output codes; a control circuit generating the M enable signals and the reference enable signal according to a clock; wherein in the first mode, the control circuit outputs the M digital output codes in turn but does not output the reference digital output code; and wherein in the second mode, the control circuit outputs the M digital output codes and the reference digital output code randomly. In the first mode, a period of the M enable signals is M times a period of the clock, and a period of the reference enable signal is M+1 times the period of the clock; in the second mode, periods of the M enable signals and the reference enable signal are not fixed.

2. The time-interleaved analog-to-digital converter of claim 1, wherein, In the second mode, the control circuit randomly selects one of the M analog-to-digital converters and the reference analog-to-digital converter.

3. The time-interleaved analog-to-digital converter of claim 2, wherein, The time-interleaved analog-to-digital converter outputs a digital output signal, and the control circuit comprises:

4. The time-interleaved analog-to-digital converter of claim 2, wherein, a selection circuit receiving the M digital output codes in the first mode and receiving the M digital output codes and the reference digital output code in the second mode; a clock generation circuit generating the M enable signals and the reference enable signal according to the clock; and a control unit coupled to the selection circuit and the clock generation circuit, controlling the selection circuit to determine the digital output signal from the M digital output codes in the first mode and from the M digital output codes and the reference digital output code in the second mode. When a time of operation of the time-interleaved analog-to-digital converter in the first mode exceeds a threshold, the control circuit controls the time-interleaved analog-to-digital converter to operate in the second mode. When the digital correction circuit indicates that an amount of error of at least one of the M digital output codes is less than a threshold, the control circuit controls the time-interleaved analog-to-digital converter to operate in the second mode.

5. The time-interleaved analog-to-digital converter of claim 2, wherein, The time-interleaved analog-to-digital converter outputs a digital output signal, and the control circuit performs a fast Fourier transform on the digital output signal, and when a result of the fast Fourier transform is greater than a threshold, the control circuit controls the time-interleaved analog-to-digital converter to operate in the second mode.

6. The time-interleaved analog-to-digital converter of claim 2, wherein, When the control circuit detects a change in at least one of an operating voltage and an ambient temperature of the time-interleaved analog-to-digital converter, the control circuit controls the time-interleaved analog-to-digital converter to operate in the first mode.

7. The time-interleaved analog-to-digital converter of claim 2, wherein, 9. A time-interleaved analog-to-digital converter operating in a first mode or a second mode to convert an input signal into a digital output signal, comprising:

8. The time-interleaved analog-to-digital converter of claim 2, wherein, a first analog-to-digital converter receiving the input signal and sampling the input signal according to a first enable signal to generate a first digital output code; ​ ​ a second analog-to-digital converter receiving the input signal and sampling the input signal according to a second enable signal to generate a second digital output code; a third analog-to-digital converter receiving the input signal and sampling the input signal according to a third enable signal to generate a third digital output code; a fourth analog-to-digital converter receiving the input signal and sampling the input signal according to a fourth enable signal to generate a fourth digital output code; a reference analog-to-digital converter receiving the input signal and sampling the input signal according to a reference enable signal to generate a reference digital output code; a digital correction circuit for correcting the first digital output code, the second digital output code, the third digital output code and the fourth digital output code to generate a first corrected digital output code, a second corrected digital output code, a third corrected digital output code and a fourth corrected digital output code, respectively; a control circuit for generating the first enable signal, the second enable signal, the third enable signal, the fourth enable signal and the reference enable signal according to a clock; wherein in the first mode, the digital output signal is selected from a first digital output code group comprising the first corrected digital output code, the second corrected digital output code, the third corrected digital output code and the fourth corrected digital output code; and wherein in the second mode, the digital output signal is selected from a second digital output code group comprising the first corrected digital output code, the second corrected digital output code, the third corrected digital output code, the fourth corrected digital output code and the reference digital output code. In the first mode, the periods of the first enable signal, the second enable signal, the third enable signal and the fourth enable signal are four times of the period of the clock, and the period of the reference enable signal is five times of the period of the clock; in the second mode, the periods of the first enable signal, the second enable signal, the third enable signal, the fourth enable signal and the reference enable signal are not fixed.

10. The time-interleaved analog-to-digital converter of claim 9, wherein, ​

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