A radio frequency direct sampling implementation method of a low-level control system with a frequency multiplication relationship

Abstract

The application discloses a radio frequency direct sampling implementation method of a low-level control system with frequency multiplication relation, and belongs to the technical field of a low-level control system of a particle cyclotron. In the application, a source signal with frequency multiplication relation is processed by using a lower frequency reference signal in an FPGA, and then is subjected to up-mixing frequency by a radio frequency digital conversion module to obtain a signal with a radio frequency working frequency; a collection signal of a controlled object is subjected to down-mixing frequency by a radio frequency direct sampling module to obtain a signal with a reference signal frequency, which is processed in the FPGA; wherein, the digital frequency multiplication of the reference signal is realized in the FPGA, and the digital frequency multiplication of the local oscillation signal is realized in the radio frequency direct sampling module, and various source signals with frequency multiplication relation are realized by digital mixing frequency. The product designed according to the application has the advantages of high integration degree, good producibility, wide adaptation to working frequency range and the like.

Description

Technical Field

[0001] This invention relates to the field of low-level control systems for particle cyclotron accelerators, and in particular to a method for implementing direct radio frequency sampling of a low-level control system with a frequency doubling relationship. Background Technology

[0002] In the low-level control systems of current particle cyclotron accelerators, radio frequency (RF) sinusoidal signals with frequency harmonic relationships are frequently used as the driving source signals in the accelerator system. In applications involving proton and heavy ion accelerators, besides those with a fundamental frequency, it is necessary to synthesize specific waveforms (such as sawtooth waves) using RF sinusoidal signals with frequency harmonic relationships. These RF sinusoidal signals with frequency harmonic relationships can be implemented using analog signals or partially digital signals. However, analog implementation of RF sinusoidal signals with frequency harmonic relationships suffers from drawbacks such as equipment complexity, high cost, poor reliability, poor maintainability, and poor manufacturability. For applications such as sawtooth wave synthesis in medical accelerators, purely digital synthesis of RF sinusoidal signals with frequency harmonic relationships can be implemented using high-performance FPGAs. However, the highest frequency at which current FPGAs can operate stably is limited, and excessively high FPGA operating frequencies also lead to problems such as high cost, high power consumption, and difficulty in heat dissipation. Summary of the Invention

[0003] In view of this, the purpose of this invention is to propose a method for implementing radio frequency direct sampling of a low-level control system with a frequency multiplication relationship. This method is based on an FPGA chip and a radio frequency direct sampling chip, and can realize the digitization of a low-level control system with a frequency multiplication relationship.

[0004] Based on the above objectives, the technical solution provided by the present invention is as follows:

[0005] A method for direct RF sampling of a low-level control system with a frequency multiplication relationship, wherein the isothermal crystal oscillator driving clock generation module of the low-level control system generates a low-speed clock signal and a high-speed clock signal with fixed frequency and phase relationship, wherein the frequency of the high-speed clock signal is an integer multiple of the frequency of the low-speed clock signal; including the following steps:

[0006] (1) Inside the FPGA, a low-speed clock signal drives a reference digital control oscillator (NCO) to generate an orthogonal sinusoidal reference signal with a frequency of f0, which serves as the internal reference signal of the low-level control system of each controlled object in the FPGA. The reference signal with a frequency of f0 is digitally multiplied to generate a reference signal with a frequency of n times f0, where n = 1, 2, 3, 4...

[0007] (2) The reference signal with frequency nf0 is subjected to phase and amplitude detection with the sampling signal of the same frequency inside the FPGA. The detected values ​​are compared with the phase preset value and amplitude preset value of this channel, respectively, and then drive the digital PID control of this channel to output the control signal of this channel after amplitude and phase adjustment to the RF direct sampling module. In the RF direct sampling module, the control signal of this channel is upsampled and then upmixed with the local oscillator signal with frequency nf1 generated by the local oscillator NCO in the module to obtain the signal with frequency nf0. out The digital control signal is converted into an analog control signal by the high-speed digital-to-analog converter module and sent to the controlled object;

[0008] (3) The operating frequency is nf out The analog acquisition signal is converted into an RF digital acquisition signal by the analog-to-digital converter module in the RF direct acquisition module. The RF digital acquisition signal is down-mixed with the local oscillator signal with frequency nf1 generated by the local oscillator NCO in the module to obtain the acquisition signal with frequency nf0. The acquisition signal is then downsampled to obtain the sampling signal and sent to the FPGA.

[0009] (4) Design a synchronization module inside the FPGA to generate a soft reset signal and a synchronization pulse signal each time the system starts, resets, or the operating frequency changes, so as to drive all processing modules in the system to maintain a certain initial state and strict synchronization.

[0010] Furthermore, the implementation of the RF direct sampling module and the internal processing of the FPGA is as follows:

[0011] (1) All internal digital signal processing of the FPGA is driven by a soft reset signal, a synchronization signal and a low-speed clock signal with a fixed phase difference;

[0012] (2) The internal digital signal processing of all RF direct sampling modules is driven by a soft reset signal, a synchronization signal and a high-speed clock signal with a fixed phase difference;

[0013] (3) All RF direct acquisition modules require a fixed high-speed clock signal of the same frequency for RF analog-to-digital conversion and RF digital-to-analog conversion, and the converted data must be updated synchronously.

[0014] (4) The downsampling factor and upsampling factor are the same for all branch digital signal processing, and they are kept in phase synchronization;

[0015] (5) After the soft reset of the synchronization module, the registers of all modules are reset to the determined initial state; after the synchronization pulse, all modules in the system start working according to the preset values.

[0016] Furthermore, the specific method of digital frequency multiplication in step (1) is as follows: the output of the phase accumulator of the reference NCO is directly multiplied by the required frequency multiplication number n to obtain the reference signal whose phase changes with time after n times the frequency, and when needed, the phase to amplitude conversion is performed to become an orthogonal sine signal.

[0017] Furthermore, the specific method of digital frequency multiplication in step (1) can also be as follows: if the frequency control word of the reference NCO is F0, then the frequency control word of the n-multiplied NCO is set to nF0. All reference signal NCOs are driven by a low-speed clock with a fixed phase shift relationship. Under the drive of the synchronous pulse signal after soft reset, reference signals with various frequency multiplication relationships are generated simultaneously.

[0018] Furthermore, the specific implementation of the local oscillator NCO inside the RF direct sampling module in steps (2) and (3) is as follows: if the frequency control word of the base frequency local oscillator NCO is F1, then the frequency control word of the n-fold frequency local oscillator NCO is set to nF1. All local oscillator NCOs are driven by a high-speed clock with a fixed phase relationship and simultaneously start generating quadrature sine signals under the drive of the synchronization pulse signal after soft reset.

[0019] Furthermore, the specific control method for the phase preset value in step (2) is as follows: the phase preset value of all control branches with a frequency multiplication relationship has a relationship with the fundamental frequency phase, that is, if the set phase value of the fundamental frequency is θ1, then the set phase value of the nth frequency multiplication branch is θ. n =nθ1+φ n , where φ n It is the independent adjustment phase value of the nth harmonic branch.

[0020] Furthermore, the specific control method for the amplitude preset value in step (2) is as follows: the amplitude preset value of all control branches with a frequency multiplication relationship has a relationship with the fundamental frequency amplitude, that is, if the set amplitude value of the fundamental frequency is a1, then the set amplitude value of the nth frequency multiplication branch is a n =k n a1, where k n It is the independent adjustment amplitude value of the nth harmonic branch.

[0021] As can be seen from the above description, the beneficial effects of the present invention are as follows:

[0022] 1. This invention enables the digitization of a low-level control system with a frequency multiplication relationship.

[0023] 2. This invention utilizes an RF digital conversion chip to implement the interface part of the system with a higher operating frequency, which reduces the speed requirements of subsequent FPGA processing. Devices manufactured based on this principle have advantages such as high integration, good manufacturability, high reliability, easy upgradeability, low power consumption, and wide operating frequency range.

[0024] 3. The present invention adopts associated phase settings and associated amplitude settings, which can adapt to the actual needs of synthesizing specific waveforms from sine waves of multiple reference frequencies.

[0025] 4. For application scenarios where the operating frequency exceeds that of the RF direct sampling chip, this invention can also serve as a basic low-frequency application component. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a block diagram illustrating the digitization principle of a low-level control system with a frequency multiplication relationship in this embodiment of the invention. In the diagram, the gray fill represents the RF digital conversion chip implementation. The diagram shows a simplified implementation of the phase-amplitude control system for the base frequency, second-order multiplication, and nth-order multiplication. Each path illustrates the main functional modules and frequency configuration relationships of the transmit and receive paths. For control paths with the same frequency, the transmit and receive NCOs can be implemented independently or share a single chip, depending on the chip used. In this embodiment, the reference signal is implemented within the FPGA, implementing all frequency multiplications based on the base frequency. When the system has a large number of paths and requires a large number of boards, each board can also use an independent NCO to implement its own reference signal. Implementation

[0028] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0029] A method for direct RF sampling of a low-level control system with a frequency multiplication relationship is provided, assuming that a temperature-controlled crystal oscillator driving a clock generation module generates a low-speed clock signal and a high-speed clock signal with a fixed frequency and phase relationship, wherein the frequency of the high-speed clock is an integer multiple of the frequency of the low-speed clock; the method includes the following steps:

[0030] (1) The low-speed clock signal inside the FPGA drives the reference digital control oscillator (NCO) to generate an orthogonal sine signal with a frequency of f0, which serves as the reference signal inside the FPGA for the low-level control system of each controlled object; the reference signal with a frequency of f0 is digitally multiplied to generate reference signals with frequencies of f0, 2f0, 3f0, ..., which are integer multiples of f0 n, ​​where n takes the natural number 1, 2, 3, 4, ...

[0031] (2) The reference signal with frequency nf0 is subjected to phase and amplitude detection with the sampling signal of the same frequency inside the FPGA. The detected values ​​are compared with the phase preset value and amplitude preset value of this channel, respectively, and then drive the digital PID control of this channel to output the control signal of this channel after amplitude and phase adjustment to the RF digital conversion module (RF direct sampling module). In the RF direct sampling module, the control signal of this channel is upsampled (DUC) and then upmixed with the local oscillator signal with frequency nf1 generated by the local oscillator NCO in the module to obtain the signal with frequency nf0. out The digital control signal is converted into an analog control signal by a high-speed DAC and sent to the controlled object.

[0032] (3) The operating frequency is nf out The analog acquisition signal is converted into an RF digital acquisition signal by the ADC in the RF direct acquisition module. The RF digital acquisition signal and the local oscillator signal with frequency nf1 generated by the local oscillator NCO in the module are down-mixed to obtain an acquisition signal with frequency nf0. The acquisition signal is then processed by downsampling (DDC) to obtain a sampling signal which is sent to the FPGA.

[0033] (4) Design a synchronization module inside the FPGA to generate a soft reset signal and a synchronization pulse signal each time the system starts, resets, or the operating frequency changes, so as to drive all processing modules in the system to maintain a certain initial state and strict synchronization.

[0034] The implementation of the RF direct sampling module and the internal processing of the FPGA is as follows:

[0035] (1) All internal digital signal processing of the FPGA is driven by a soft reset signal, a synchronization signal and a low-speed clock signal with a fixed phase difference;

[0036] (2) The internal digital signal processing of all RF direct sampling modules is driven by a soft reset signal, a synchronization signal and a high-speed clock signal with a fixed phase difference;

[0037] (3) All RF ADCs and RF DACs of the RF direct sampling modules need to be connected to a high-speed clock signal with a fixed phase difference and update the converted data synchronously;

[0038] (4) The downsampling factor of the DDC and the upsampling factor of the DUC are the same for all branches of digital signal processing, and they are kept in phase synchronization;

[0039] (5) After the soft reset of the synchronization module, the registers of all modules are reset to the determined initial state; after the synchronization pulse, all modules in the system start working according to the preset values.

[0040] The specific implementation of digital frequency multiplication in step (1) is as follows: the output of the phase accumulator of the reference NCO is directly multiplied by the required frequency multiplication number n to obtain the reference signal whose phase changes with time after n times the frequency. When needed, the phase to amplitude conversion is performed to transform it into an orthogonal sine signal.

[0041] The specific implementation of digital frequency multiplication in step (1) can also be as follows: if the frequency control word of the reference NCO is F0, then the frequency control word of the n-multiplied NCO is set to nF0. All reference signals NCO are driven by a low-speed clock with a fixed phase shift relationship. Under the drive of the synchronization pulse signal after soft reset, reference signals with various frequency multiplication relationships are generated simultaneously.

[0042] The specific implementation of the local oscillator NCO inside the RF direct sampling module in steps (2) and (3) is as follows: if the frequency control word of the base frequency local oscillator NCO is F1, then the frequency control word of the n-fold frequency local oscillator NCO is set to nF1. All local oscillator NCOs are driven by a high-speed clock with a fixed phase relationship and start generating quadrature sine signals simultaneously under the drive of the synchronization pulse signal after soft reset.

[0043] The specific implementation control method of the phase preset value in step (2) is as follows: the phase preset value of all control branches with a frequency multiplication relationship can have a relationship with the fundamental frequency phase, that is, if the set phase value of the fundamental frequency is θ1, then the set phase value of the nth frequency multiplication branch is θ. n =nθ1+φ n , where φ n It is the independent adjustment phase value of the nth harmonic branch.

[0044] The specific implementation control method for the amplitude preset value in step (2) is as follows: the amplitude preset value of all control branches with a frequency multiplication relationship can have a relationship with the fundamental frequency amplitude, that is, if the set amplitude value of the fundamental frequency is a1, then the set amplitude value of the nth frequency multiplication branch is a n =k n a1, where k n It is the independent adjustment amplitude value of the nth harmonic branch.

[0045] This invention can be implemented using domestically produced RF direct sampling chips, and can operate reliably in the RF frequency range of tens of MHz to 1.2 GHz, meeting the digital requirements of most RF accelerator low-level control systems.

[0046] Here is a more specific example:

[0047] like Figure 1 As shown, a low-level control system with an operating frequency having a harmonic relationship has the following digital signal processing process:

[0048] Assume that the temperature-controlled crystal oscillator drives the clock generation module to generate a low-speed clock signal and a high-speed clock signal with a fixed frequency and phase relationship, wherein the frequency of the high-speed clock is an integer multiple of the frequency of the low-speed clock.

[0049] The low-speed clock signal serves as the system clock for the FPGA, driving multiple phase detection and phase control PID modules and amplitude detection and amplitude control PID modules (referred to as phase-amplitude control PID) with multi-frequency multiplication relationships within the FPGA. The phase-amplitude control PID is connected to the RF digital conversion module, which in turn is connected to external power amplifiers and accelerator cavities, among other controlled objects.

[0050] The reference source and phase control circuits of each controlled object within the FPGA operate under the same low-speed clock signal. This is a necessary condition for maintaining a fixed phase relationship between the signals of each branch. The so-called low-speed clock signal is the system clock with a frequency of tens to hundreds of MHz; the high-speed clock typically has a frequency of hundreds of MHz to several GHz and is used to drive RF direct sampling chips.

[0051] (1) The low-speed clock signal inside the FPGA drives the reference digital control oscillator (NCO) to generate an orthogonal sine signal with a frequency of f0, which serves as the reference signal inside the FPGA for the low-level control system of each controlled object; the reference signal with a frequency of f0 is digitally multiplied to generate reference signals with frequencies of f0, 2f0, 3f0, ..., which are integer multiples of f0 n, ​​where n takes the natural number 1, 2, 3, 4, ...

[0052] (10) Digital frequency multiplication can be achieved as follows: the output of the phase accumulator of the reference NCO is directly multiplied by the required frequency multiplication number n to obtain the reference signal whose phase changes with time after n times the frequency. When needed, the phase to amplitude conversion is performed to transform it into an orthogonal sine signal.

[0053] like Figure 1 In the schematic diagram of the embodiment, the reference signal is generated by direct frequency multiplication to generate a frequency-multiplied reference signal; this method is suitable for situations where all controlled objects are implemented in the FPGA on the same board to realize phase, amplitude, and tuning frequencies.

[0054] (11) Digital frequency multiplication can also be implemented as follows: If the frequency control word of the reference NCO is F0, then the frequency control word of the n-multiplied NCO is set to nF0. All reference signal NCOs are driven by a low-speed clock with a fixed phase shift relationship. Under the drive of the synchronous pulse signal after soft reset, reference signals with various frequency multiplication relationships are generated simultaneously.

[0055] When there are many controlled objects, such as several controlled objects for the base frequency and several controlled objects for the secondary frequency, and the digital signal processing part of the reference frequency of all controlled objects is difficult to implement in the FPGA of the same board, it is troublesome to transmit a lot of reference signals between multiple FPGA boards. This method can be used inside the FPGA of each board.

[0056] Obviously, when the highest operating frequency of the controlled object is low, the reference signal generated by one of the two methods mentioned above can be used as the operating frequency with a frequency multiplication relationship, thus saving the radio frequency digital conversion module.

[0057] (2) The reference signal with frequency nf0 is subjected to phase and amplitude detection with the sampling signal of the same frequency inside the FPGA. The detected values ​​are compared with the phase preset value and amplitude preset value of this channel, respectively, and then drive the digital PID control of this channel to output the control signal of this channel after amplitude and phase adjustment to the RF digital conversion module (RF direct sampling module). In the RF direct sampling module, the control signal of this channel is upsampled (DUC) and then upmixed with the local oscillator signal with frequency nf1 generated by the local oscillator NCO in the module to obtain the signal with frequency nf0. out The digital control signal is converted into an analog control signal by a high-speed DAC and sent to the controlled object.

[0058] exist Figure 1 In the schematic diagram of the embodiment, the three amplitude and phase control branches with a frequency doubling relationship perform their own amplitude and phase control and perform upmixing of their own branches.

[0059] (20) The specific method for achieving control by phase preset value is as follows: the phase preset value of all control branches with frequency multiplication relationship can have a relationship with the fundamental frequency phase, that is, if the set phase value of the fundamental frequency is θ1, then the set phase value of the nth frequency multiplication branch is θ. n =nθ1+φ n , where φ n It is the independent adjustment phase value of the nth harmonic branch.

[0060] As in the example of the sawtooth wave phase control, after setting the phase θ1 of the associated base frequency, adjusting the set phase value of the base frequency will not change the waveform of the entire adjusted sawtooth wave.

[0061] (21) The specific method for implementing amplitude preset value control is as follows: the amplitude preset value of all control branches with frequency multiplication relationships can have a relationship with the fundamental frequency amplitude, that is, if the set amplitude value of the fundamental frequency is a1, then the set amplitude value of the nth frequency multiplication branch is a n =k n a1, where k n It is the independent adjustment amplitude value of the nth harmonic branch.

[0062] As in the example of sawtooth wave amplitude control, after setting the amplitude a1 of the associated base frequency, adjusting the set amplitude value of the base frequency will not change the waveform of the entire adjusted sawtooth wave.

[0063] (3) The operating frequency is nf out The analog acquisition signal is converted into an RF digital acquisition signal by the ADC in the RF direct acquisition module. The RF digital acquisition signal and the local oscillator signal with frequency nf1 generated by the local oscillator NCO in the module are down-mixed to obtain an acquisition signal with frequency nf0. The acquisition signal is then processed by downsampling (DDC) to obtain a sampled signal which is sent to the FPGA.

[0064] (30) The specific implementation of each local oscillator numerically controlled oscillator (NCO) inside the radio frequency digital conversion module is as follows: If the frequency control word of the local oscillator numerically controlled oscillator (NCO) of the base frequency branch is F1, then the frequency control word of the n-fold frequency numerically controlled oscillator (NCO) is set to nF1. All local oscillator NCOs are driven by a high-speed clock with a fixed phase relationship and start generating quadrature sine signals simultaneously under the drive of the synchronization pulse signal.

[0065] exist Figure 1 In this embodiment, the receive local oscillator (NCO) and the transmit local oscillator (NCO) use independent NCOs, which is consistent with the actual situation of most RF digital conversion chips. In fact, it is better to use the same local oscillator NCO for the receive and transmit NCOs of all branches with the same frequency, which can be achieved in some chips.

[0066] (4) Design a synchronization module inside the FPGA to generate a soft reset signal and a synchronization pulse signal each time the system starts, resets, or the operating frequency changes, so as to drive all processing modules in the system to maintain a certain initial state and strict synchronization.

[0067] The implementation methods of the RF-to-digital conversion module and the digital processing inside the FPGA include:

[0068] (1) All internal digital signal processing of the FPGA is driven by a soft reset signal, a synchronization signal and a low-speed clock signal with a fixed phase difference;

[0069] This is the only way to ensure that each branch has a relatively fixed phase relationship.

[0070] (2) The internal digital signal processing of all radio frequency digital conversion modules is driven by a soft reset signal, a synchronization signal and a high-speed clock signal with a fixed phase difference;

[0071] (3) All RF ADCs and RF DACs of the RF direct sampling modules need to be connected to a high-speed clock signal with a fixed phase difference and update the converted data synchronously;

[0072] (4) The downsampling factor of the DDC and the upsampling factor of the DUC are the same for all branches of digital signal processing, and they are kept in phase synchronization;

[0073] (5) After the soft reset of the synchronization module, the registers of all modules are reset to the determined initial state; after the synchronization pulse, all modules in the system start working according to the preset values.

[0074] In this invention, source signals with a frequency multiplication relationship are processed using a lower-frequency reference signal within the FPGA, and then up-mixed by the RF digital conversion module (RF direct acquisition) to obtain the RF operating frequency signal. The acquired signal of the controlled object is down-mixed by the RF direct acquisition module to obtain the reference signal frequency signal, which is then processed within the FPGA. Specifically, digital frequency multiplication of the reference signal is implemented within the FPGA, and digital frequency multiplication of the local oscillator signal is implemented within the RF direct acquisition module. Various source signals with a frequency multiplication relationship are realized through digital mixing. To achieve ease of use, this invention proposes a method for setting the correlation between phase and amplitude control. Products designed according to this invention have advantages such as high integration, good manufacturability, and wide adaptability to operating frequency ranges.

[0075] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples. Any omissions, modifications, equivalent substitutions, improvements, etc., made to the above embodiments within the spirit and principles of this invention should be included within the protection scope of this invention.

Claims

1. A method for implementing direct radio frequency sampling in a low-level control system with a frequency multiplication relationship, wherein the isothermal crystal oscillator driving clock generation module of the low-level control system generates a low-speed clock signal and a high-speed clock signal with fixed frequency and phase relationship, wherein the frequency of the high-speed clock signal is an integer multiple of the frequency of the low-speed clock signal; characterized in that, Includes the following steps: (1) Inside the FPGA, a low-speed clock signal drives a reference digital control oscillator to generate an orthogonal sinusoidal reference signal with a frequency of f0, which serves as the internal reference signal of the low-level control system of each controlled object in the FPGA. The reference signal with a frequency of f0 is digitally multiplied to generate a reference signal with a frequency of n times f0, where n = 1, 2, 3, 4... (2) the reference signal with frequency nf0 is compared with the sampling signal with the same frequency in the FPGA in phase and amplitude, the detection values are compared with the preset phase and amplitude values of the channel, then the digital PID control of the channel is driven, and the channel control signal after amplitude and phase adjustment is output to the RF direct sampling module; in the RF direct sampling module, the channel control signal is up-sampled and mixed with the local oscillator signal with frequency nf1 generated by the local oscillator NCO in the module to obtain the digital control signal with frequency nf out , which is converted into an analog control signal by the high-speed digital-to-analog conversion module and sent to the controlled object; (3) the working frequency is nf out The analog collected signal is converted into a radio frequency digital collected signal by an analog-digital conversion module in the radio frequency direct collection module, the radio frequency digital collected signal is mixed with a local oscillator signal with a frequency of nf1 generated by a local oscillator NCO in the module, a collected signal with a frequency of nf0 is obtained, and the collected signal is processed by down-sampling to obtain a sampling signal and sent to the FPGA. (4) Design a synchronization module inside the FPGA to generate a soft reset signal and a synchronization pulse signal each time the system starts, resets, or the operating frequency changes, so as to drive all processing modules in the system to maintain a certain initial state and strict synchronization.

2. The method for implementing direct radio frequency sampling of a low-level control system with a frequency doubling relationship according to claim 1, characterized in that, The implementation of the RF direct sampling module and the FPGA internal processing is as follows: (1) All internal digital signal processing of the FPGA is driven by a soft reset signal, a synchronization signal and a low-speed clock signal with a fixed phase difference; (2) The internal digital signal processing of all RF direct sampling modules is driven by a soft reset signal, a synchronization signal and a high-speed clock signal with a fixed phase difference; (3) All RF direct acquisition modules require a fixed high-speed clock signal of the same frequency for RF analog-to-digital conversion and RF digital-to-analog conversion, and the converted data must be updated synchronously. (4) The downsampling factor and upsampling factor are the same for all branch digital signal processing, and they are kept in phase synchronization; (5) After the soft reset of the synchronization module, the registers of all modules are reset to a defined initial state; After the synchronization pulse, all modules in the system begin to work according to the preset values.

3. The method for implementing direct radio frequency sampling of a low-level control system with a frequency doubling relationship according to claim 1, characterized in that, The specific method of digital frequency multiplication in step (1) is as follows: the output of the phase accumulator of the reference NCO is directly multiplied by the required frequency multiplication number n to obtain the reference signal whose phase changes with time after n times the frequency. When needed, the phase to amplitude conversion is performed to transform it into an orthogonal sine signal.

4. The method for implementing direct radio frequency sampling of a low-level control system with a frequency doubling relationship according to claim 1, characterized in that, The specific method of digital frequency multiplication in step (1) is as follows: if the frequency control word of the reference NCO is F0, then the frequency control word of the n-multiplied NCO is set to nF0. All reference signal NCOs are driven by a low-speed clock with a fixed phase shift relationship. Under the drive of the synchronous pulse signal after soft reset, reference signals with various frequency multiplication relationships are generated simultaneously.

5. The method for implementing direct radio frequency sampling of a low-level control system with a frequency doubling relationship according to claim 1, characterized in that, The specific implementation of the local oscillator NCO inside the RF direct sampling module in steps (2) and (3) is as follows: if the frequency control word of the base frequency local oscillator NCO is F1, then the frequency control word of the n-fold frequency local oscillator NCO is set to nF1. All local oscillator NCOs are driven by a high-speed clock with a fixed phase relationship and start generating quadrature sine signals simultaneously under the drive of the synchronization pulse signal after soft reset.

6. The method for implementing direct radio frequency sampling of a low-level control system with a frequency doubling relationship according to claim 1, characterized in that, The specific control method for the phase preset value in step (2) is as follows: the phase preset value of all control branches with a frequency multiplication relationship has a relationship with the fundamental frequency phase, that is, if the set phase value of the fundamental frequency is θ1, then the set phase value of the nth frequency multiplication branch is θ. n =nθ1+φ n , where φ n It is the independent adjustment phase value of the nth harmonic branch.

7. The method for implementing direct radio frequency sampling of a low-level control system with a frequency doubling relationship according to claim 1, characterized in that, The specific control method for the amplitude preset value in step (2) is as follows: the amplitude preset value of all control branches with a frequency multiplication relationship has a relationship with the fundamental frequency amplitude, that is, if the set amplitude value of the fundamental frequency is a1, then the set amplitude value of the nth frequency multiplication branch is a n =k n a1, where k n It is the independent adjustment amplitude value of the nth harmonic branch.

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