Semiconductor structure and method of forming the same

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a forming method thereof. The method comprises: providing a substrate, the substrate comprising a substrate, a stacked structure and an initial mask layer, the stacked structure being on the substrate, and the initial mask layer being on a top surface of the stacked structure; forming a capacitor hole, the capacitor hole penetrating through the initial mask layer and the stacked structure; forming an initial conductive layer, the initial conductive layer covering an inner wall of the capacitor hole and covering a top surface of the initial mask layer; etching the initial conductive layer and the initial mask layer to form a first opening, the remaining initial mask layer forming a first mask layer, and the remaining initial conductive layer above the first mask layer forming a first conductive layer; etching the first conductive layer and the first mask layer to form a capacitor structure and a support structure while etching the stacked structure through the first opening.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor manufacturing, and relates to but is not limited to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] A dynamic random access memory (DRAM) cell includes a capacitor for storing electric charge and a transistor. The DRAM stores data in the form of electric charge on the capacitor, so the capacitor needs to be regularly recharged at intervals of a few milliseconds. The greater the capacitance of the capacitor, the longer the data stored in the DRAM can be maintained. However, when a capacitor is formed using a conventional process, the height of the lower electrode is reduced, thereby reducing the capacitance value of the subsequently formed capacitor. SUMMARY

[0003] Embodiments of the present disclosure provide a semiconductor structure and a forming method thereof.

[0004] In a first aspect, embodiments of the present disclosure provide a forming method of a semiconductor structure, the method comprising: providing a substrate, the substrate comprising a substrate, a layer stack, and an initial mask layer, the layer stack being on the substrate, the initial mask layer being on a top surface of the layer stack; forming a capacitor hole, the capacitor hole penetrating through the initial mask layer and the layer stack; forming an initial conductive layer, the initial conductive layer covering an inner wall of the capacitor hole and covering a top surface of the initial mask layer; etching the initial conductive layer and the initial mask layer to form a first opening, a remaining initial mask layer forming a first mask layer, and a remaining initial conductive layer above the first mask layer forming a first conductive layer; etching away the first conductive layer and the first mask layer while etching the layer stack through the first opening to form a capacitor structure and a support structure.

[0005] In some embodiments, the forming of the initial conductive layer comprises: filling the initial conductive layer in the capacitor hole to form a columnar lower electrode; or depositing the initial conductive layer on a bottom and a sidewall of the capacitor hole to form a cylindrical lower electrode.

[0006] In some embodiments, the forming of the capacitor structure and the support structure comprises: etching away the first conductive layer above the first mask layer while etching the layer stack through the first opening, a remaining initial conductive layer forming a lower electrode, and a remaining layer stack forming the support structure; sequentially forming a dielectric layer and an upper electrode on surfaces of the lower electrode and the support structure to form the capacitor structure.

[0007] In some embodiments, the layer stack includes a bottom support layer, a first sacrificial layer, an intermediate support layer, a second sacrificial layer, and a top support layer stacked in sequence; etching the layer stack through the first opening includes: etching away the first conductive layer while forming a second opening through the top support layer by etching through the first opening; and removing the second sacrificial layer through the second opening.

[0008] In some embodiments, etching the layer stack through the first opening further includes: exposing part of the intermediate support layer after removing the second sacrificial layer through the second opening; removing the first mask layer while patterning the intermediate support layer to form a third opening; and removing the first sacrificial layer through the third opening to expose the bottom support layer.

[0009] In some embodiments, the second opening is formed by a dry etching process that removes the first conductive layer simultaneously; and the etching gas in the dry etching process includes: chlorine, oxygen, and argon.

[0010] In some embodiments, the material of the first sacrificial layer includes boron phosphorus silicon glass, and the material of the second sacrificial layer includes oxide; and the second sacrificial layer and the first sacrificial layer are removed by a hydrofluoric acid solution.

[0011] In some embodiments, the third opening is formed by a dry etching process that removes the first mask layer simultaneously; and the etching gas in the dry etching process includes at least one of: C4F8, C4F6, O2, and CH2F2.

[0012] In some embodiments, the first conductive layer and the first mask layer are formed by: sequentially forming an initial composite mask layer and a patterned photoresist layer on the initial conductive layer; etching the initial composite mask layer based on the patterned photoresist layer to form a patterned composite mask layer; and etching the initial conductive layer and the initial mask layer based on the patterned composite mask layer to form the first opening, the first conductive layer, and the first mask layer.

[0013] In some embodiments, the forming of the capacitor hole includes: etching the initial mask layer in a first pattern identical to the capacitor hole pattern to form an initial mask layer having the first pattern; and etching the layer stack through the initial mask layer having the first pattern to form the capacitor hole that exposes the substrate.

[0014] In some embodiments, the initial mask layer includes a polysilicon layer and a silicon oxide layer on the polysilicon layer.

[0015] In a second aspect, the disclosure provides a semiconductor structure, wherein the semiconductor structure comprises: a substrate; the capacitor structure and the support structure formed by the method in any of the above embodiments on the substrate; and wherein a top surface of the capacitor structure is higher than a top surface of the support structure.

[0016] In some embodiments, the capacitor structure comprises a double-sided capacitor structure or a columnar capacitor structure.

[0017] In some embodiments, a height difference between the top surface of the capacitor structure and the top surface of the support structure ranges from 30nm to 45nm.

[0018] In the embodiments of the disclosure, first, a substrate is provided, the substrate comprising a substrate, a laminated structure on the substrate, and an initial mask layer on a top surface of the laminated structure; second, a capacitor hole is formed through the initial mask layer and the laminated structure; third, an initial conductive layer is formed covering an inner wall of the capacitor hole and the top surface of the initial mask layer; fourth, the initial conductive layer and the initial mask layer are etched to form a first opening, the remaining initial mask layer forms a first mask layer, and the remaining initial conductive layer above the first mask layer forms a first conductive layer; and finally, the first conductive layer and the first mask layer are etched and removed while the laminated structure is etched through the first opening to form the capacitor structure and the support structure.

[0019] Since the initial mask layer is not removed after the capacitor hole is formed, no by-products will fall into the capacitor hole, so the capacitor hole is relatively clean, the quality of the lower electrode formed subsequently is good, and the structure of the peripheral area will not be damaged by penetration. At the same time, since there is no etching process of removing the initial mask layer, on the one hand, the top support layer will not be consumed and the capacitor hole will not be enlarged, so that the height of the lower electrode will not be reduced and the adjacent lower electrodes will not be connected to cause short circuit, thereby improving the capacitance value; on the other hand, the support effect of the support structure can be improved.

[0020] Since the first mask layer and the first conductive layer are formed on the laminated structure, when the laminated structure is etched through the first opening, the first mask layer and the first conductive layer will protect the top support layer in the laminated structure, thereby reducing the consumption of the top support layer; at the same time, the lower electrode in the capacitor hole will not be consumed, so that not only the support effect of the support structure can be improved, but also the height of the lower electrode can be improved, thereby improving the capacitance value of the capacitor structure. BRIEF DESCRIPTION OF DRAWINGS

[0021] In the drawings, which are not necessarily drawn to scale, like numerals describe substantially similar components throughout the several views. Like numerals having different letter suffixes can represent different instances of substantially similar components. The drawings illustrate generally, by way of example, various embodiments discussed herein.

[0022] Figure 1 An implementation flowchart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. 1.

[0023] Figures 2 to 14 A schematic diagram of a forming process of a semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. 2. DETAILED DESCRIPTION

[0024] Example embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. Like numerals can be used to describe similar figures in the several embodiments and cross reference can be used to describe common and / or similar features. While example embodiments of the present disclosure are described herein, the present disclosure is not limited to these embodiments, but instead encompasses all alternatives falling within the scope of the present disclosure. Furthermore, the described features, concepts, and principles can be employed separately or in any combination and are not limited to the embodiments described and shown herein.

[0025] In the following description, numerous specific details are given to provide a thorough understanding of the present disclosure. However, it will be apparent that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known structures and components are not described in detail in order to avoid obscuring the present disclosure. In this description, the terminology "example" means an instance of the general class of examples and not an ideal embodiment. The terminology "exemplary" means an instance of the general class of examples and is not an ideal embodiment. Indeed, the specific

[0026] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like numerals refer to like elements throughout.

[0027] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0029] In related technologies, after forming the capacitor holes, a hard mask layer of approximately 100 nanometers (nm) remains on the top support layer (the material of the hard mask layer can be polysilicon). This polysilicon layer needs to be removed through an additional first etching process. Afterwards, nitrogen is used to remove byproducts, followed by ashing treatment. Finally, a cleaning solution is used for cleaning. After subsequently depositing titanium nitride (TiN) material to form the lower electrode, a second etching process is required to remove the TiN located on the top support layer. Afterwards, nitrogen etching is used to remove byproducts, and the surface is cleaned with a cleaning solution to isolate each lower electrode. Furthermore, as can be seen from the above, removing polysilicon and excess titanium nitride requires at least seven processes.

[0030] However, the existence of the first etching process and the second etching process will cause many problems. On the one hand, when the first etching process is used to remove the polysilicon, by-products (such as polymers, etc.) will be generated, which will fall into the high aspect ratio capacitor hole and be difficult to remove, thus affecting the quality of the lower electrode formed subsequently. On the other hand, the two processes will consume more than 20 nm of the top support layer, which will not only reduce the height of the lower electrode, thus reducing the capacitance value of the capacitor formed subsequently; the first etching process will also expand the critical dimension (CD) of the top of the capacitor hole, which will cause short circuit between the two adjacent lower electrodes.

[0031] In addition, due to the existence of by-product particles in the related capacitor hole, there will be a point of by-product particles on the lower electrode when the lower electrode is formed subsequently, thus forming a hole on the lower electrode; when the sacrificial layer in the array region and the peripheral region is opened subsequently, the etching solution may penetrate into the peripheral region through the hole on the lower electrode, thus etching the bottom support layer in the peripheral region, and exposing some structures in the peripheral region in advance, which will damage the structures in the peripheral region.

[0032] Embodiments of the present disclosure provide a method for forming a semiconductor structure, referring to FIG. 1, Figure 1 The method comprises steps S101 to S105, wherein:

[0033] In step S101, a substrate is provided, which comprises a substrate, a laminated structure and an initial mask layer, the laminated structure is located on the substrate, and the initial mask layer is located on the top surface of the laminated structure.

[0034] The substrate can be a single-layer substrate, for example, the substrate can comprise a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a gallium arsenide substrate, a ceramic substrate, a quartz substrate or a glass substrate for display; the substrate can also comprise multiple layers, for example, a silicon on insulator (SOI) substrate, or a germanium on insulator (GOI) substrate, etc. In some embodiments, the substrate can also be a substrate after ion doping, for example, a P-type doped substrate or an N-type doped substrate.

[0035] In implementation, the substrate can include landing pads (LPs) for connecting the drain of the transistor and the subsequently formed capacitor structure (i.e., the capacitor), and isolation structures between adjacent landing pads; the landing pads can be arranged in an array corresponding to the arrangement of the capacitors. In some embodiments, the substrate includes a peripheral region and an array region, the peripheral region being used to form peripheral devices such as field effect transistors, capacitors, inductors, diodes, and the like. The array region is used to form memory structures in subsequent processes, such as structures including word lines, bit lines, and memory transistors, and the like.

[0036] The laminated structure can include a support layer and a sacrificial layer laminated in sequence. The support layer is used to form a support structure for supporting the subsequently formed capacitor structure; the sacrificial layer is consumed in subsequent processes to leave space for depositing the dielectric layer material and the upper electrode material. In implementation, the laminated structure can include a bottom support layer, a first sacrificial layer, a middle support layer, a second sacrificial layer, and a top support layer laminated in sequence. The material of the support layer can include at least one of silicon oxide, silicon nitride, silicon carbon nitride, silicon oxynitride, and silicon boron nitride. The material of the sacrificial layer can include silicon oxide, phosphorus silicon glass (PSG), boro phosphor silicate glass (BPSG), or fluoro silicate glass (FSG), and the like.

[0037] The initial mask layer not only serves as a mask layer, but also protects the top support layer when etching the laminated structure subsequently, thereby reducing the reduction amount of the top support layer and the lower electrode, and further improving the capacitance value of the capacitor structure and the support effect of the support structure. The initial mask layer can be a single-layer structure or a double-layer structure; the material of each layer can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polysilicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, tantalum nitride, titanium, and the like. In implementation, the initial mask layer can be a double-layer structure including a polysilicon layer and a silicon oxynitride layer (or a silicon oxide layer) on the polysilicon layer.

[0038] The support layer, the sacrificial layer and the initial mask layer can be formed by any suitable deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a spin-coating process, a coating process or a thin film process, etc.

[0039] In step S102, a capacitor hole is formed, the capacitor hole penetrating through the initial mask layer and the stacked structure.

[0040] Here, the capacitor hole can expose the substrate, and a dry method (such as a plasma etching process, a reactive ion etching process or an ion milling process) can be used to pattern the initial mask layer and the stacked structure to form the capacitor hole. The gas used in the dry etching can be one or a combination of trifluoromethane (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), hydrobromic acid (HBr), chlorine (Cl2), sulfur hexafluoride (SF6), octafluorocyclobutane (C4F8), hexafluoro-2-butyne (C4F6), oxygen (O2) and argon (Ar). In some embodiments, a wet etching process can also be used to form the capacitor hole.

[0041] In step S103, an initial conductive layer is formed, the initial conductive layer covering the inner wall of the capacitor hole and covering the top surface of the initial mask layer.

[0042] Here, the initial conductive layer can include two parts, one part is the initial conductive layer covering the inner wall of the capacitor hole (the initial conductive layer can fill the capacitor hole, or the initial conductive layer can not fill the capacitor hole, but only form at the bottom and the sidewall of the capacitor hole), and the other part is the initial conductive layer covering the initial mask layer.

[0043] In implementation, any suitable deposition process can be used to form the initial conductive layer, such as a low pressure chemical vapor deposition (LPCVD) process, etc.

[0044] In some embodiments, the implementation of step S103 can include step S1031 or step S1032, wherein: step S1031 fills the initial conductive layer in the capacitor hole to form a columnar lower electrode, and a columnar capacitor can be formed subsequently, the area of the columnar capacitor is smaller than that of a double-sided capacitor, so that the integration level can be improved and miniaturization can be achieved; step S1032 deposits the initial conductive layer at the bottom and sidewall of the capacitor hole. That is, the initial conductive layer in the capacitor hole is consistent with the topography of the capacitor hole, so as to form a cylindrical lower electrode, and a cylindrical capacitor can be formed subsequently, thereby improving the capacitance value.

[0045] Step S104: etching the initial conductive layer and the initial mask layer to form a first opening, the remaining initial mask layer forms a first mask layer, and the remaining initial conductive layer above the first mask layer forms a first conductive layer.

[0046] Here, the difference between step S104 and the related art at least includes that the initial conductive layer and the initial mask layer are removed in the related art, while step S104 only etches the initial conductive layer and the initial mask layer to form a first opening. Dry etching or wet etching process can be used to etch the initial conductive layer and the initial mask layer to form a first opening. It should be noted that, in order to reduce the damage to the lower electrode when forming the first opening, the projection of the first opening along the thickness direction of the stacked structure should be located between adjacent columnar lower electrodes or cylindrical lower electrodes.

[0047] Step S105: etching the first conductive layer and the first mask layer to form a capacitor structure and a support structure while etching the stacked structure through the first opening.

[0048] Here, etching the stacked structure through the first opening can include multiple etching processes, the number of etching times is related to the number of layers in the stacked structure, for example, the stacked structure includes a bottom support layer, a sacrificial layer and a top support layer, and the number of etching times can be twice. Once is to open the top support layer through the first opening, and the other is to remove the sacrificial layer through the opening on the top support layer. The removal time of the first conductive layer and the first mask layer is related to the etching gas or etching solution in the etching process. In implementation, the first mask layer should be removed as much as possible in the step before removing the lowermost sacrificial layer in the stacked structure, so as to simplify the process flow and reduce the consumption of the top support layer.

[0049] In this embodiment of the disclosure, firstly, a substrate is provided, the substrate including a substrate, a stacked structure, and an initial mask layer, the stacked structure being located on the substrate, and the initial mask layer being located on the top surface of the stacked structure; secondly, a capacitor aperture penetrating the initial mask layer and the stacked structure is formed; then, an initial conductive layer is formed covering the inner wall of the capacitor aperture and the top surface of the initial mask layer; next, the initial conductive layer and the initial mask layer are etched to form a first opening, the remaining initial mask layer forms a first mask layer, and the remaining initial conductive layer above the first mask layer forms a first conductive layer; finally, while etching the stacked structure through the first opening, the first conductive layer and the first mask layer are etched away to form a capacitor structure and a support structure.

[0050] Since the initial mask layer is not removed after the capacitor aperture is formed, no byproducts are generated and fall into the capacitor aperture, resulting in a relatively clean capacitor aperture. This leads to a better quality lower electrode formed subsequently and prevents penetration damage to the surrounding structure. At the same time, the absence of the initial mask layer during the etching process avoids consuming the top support layer and enlarging the capacitor aperture, thus preventing a decrease in the height of the lower electrode and short-circuiting of adjacent lower electrodes, thereby increasing the capacitance value. Furthermore, it enhances the support effect of the support structure.

[0051] Since a first mask layer and a first conductive layer are formed on the stacked structure, when the stacked structure is etched through the first opening, the first mask layer and the first conductive layer will protect the top support layer in the stacked structure, thereby reducing the consumption of the top support layer; at the same time, it will not consume the lower electrode located in the capacitor hole. This not only improves the support effect of the support structure, but also increases the height of the lower electrode, thereby increasing the capacitance value of the capacitor structure.

[0052] The following will refer to Figures 2 to 14 The process of forming a semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0053] refer to Figure 2 In step S101, a substrate 100 is provided. The substrate 100 includes a substrate 10, a stacked structure 20, and an initial mask layer 30. The stacked structure 20 is located on the substrate 10, and the initial mask layer 30 is located on the top surface of the stacked structure 20.

[0054] Here, the stacked structure 20 may include a bottom support layer 201, a first sacrificial layer 202, an intermediate support layer 203, a second sacrificial layer 204, and a top support layer 205. The bottom support layer 201, the intermediate support layer 203, and the top support layer 205 are made of silicon nitride or silicon carbide nitride. The first sacrificial layer 202 is made of borosilicate glass, and the second sacrificial layer 204 is made of an oxide, such as silicon oxide. The initial mask layer 30 includes a polysilicon layer 301 and a silicon oxide layer 302 located on the polysilicon layer 301.

[0055] Reference will now be made to the following drawings Figure 2 and Figure 3 Step S102 is performed to form the capacitor hole 40 which penetrates the initial mask layer 30 and the stacked structure 20. It should be noted that part of the initial mask layer 30 will be consumed when the capacitor hole 40 is formed, and thus the initial mask layer 30 on the stacked structure 20 will be thinned after the capacitor hole 40 is formed. In order to leave the initial mask layer on the stacked structure after the capacitor hole is formed, the etching rate of the etching substance on the stacked structure needs to be greater than the etching rate on the initial mask layer.

[0056] In implementation, the initial mask layer can be etched in the same first pattern as the capacitor hole pattern to form the initial mask layer with the first pattern, and the stacked structure can be etched with the initial mask layer with the first pattern to form the capacitor hole which penetrates the stacked structure while exposing the substrate. The capacitor hole pattern includes a plurality of capacitor holes arranged in an array, and the plurality of capacitor holes correspond to the plurality of landing pads one by one, and each capacitor hole is in communication with the corresponding landing pad. In some embodiments, the self-aligned double patterning (SADP) technique can also be used to form the capacitor hole to realize spatial frequency multiplication of the lithography pattern, so that a capacitor hole with smaller size and higher density can be formed.

[0057] Reference will now be made to the following drawings Figures 3 to 5 Step S103 is performed to form the initial conductive layer 50 which covers the inner wall of the capacitor hole 40 and covers the top surface of the initial mask layer 30. Figure 4 FIG. 4 is a schematic view of filling the initial conductive layer 50 in the capacitor hole to form a columnar lower electrode. In some embodiments, as shown in FIG. 5, the initial conductive layer 50 is deposited at the bottom and sidewall of the capacitor hole to form a cylindrical lower electrode. In the embodiments of the present disclosure, the columnar lower electrode is mainly taken as an example for illustration. Figure 5

[0058] Reference will now be made to the following drawings Figures 6 to 8 Step S104 is performed to etch the initial conductive layer 50 and the initial mask layer 30 to form the first opening 605, and the remaining initial mask layer 30 forms the first mask layer 31, and the remaining initial conductive layer 50 above the first mask layer 31 forms the first conductive layer 51.

[0059] In some embodiments, forming the first conductive layer and the first mask layer can include steps S1041 to S1043, in which:

[0060] Step S1041, sequentially forming an initial composite mask layer and a patterned photoresist layer on the initial conductive layer;

[0061] ​Here, the initial composite mask layer can include at least two mask layers, and each mask layer can be made of any one of silicon dioxide, silicon nitride, amorphous carbon (ACL), silicon oxynitride, and polysilicon. For example, the initial composite mask layer can include a silicon nitride layer and an amorphous carbon layer on the silicon nitride layer. In implementation, a bottom anti-reflection coating (BARC) layer can be formed on the initial composite mask layer, and then a patterned photoresist layer can be formed on the BARC layer. In this way, the BARC layer can absorb reflected light during photolithography, thereby improving the accuracy of pattern transfer. The BARC layer can be made of silicon oxynitride (SiON) or the like.

[0062] Reference is made to Figure 6 In step S1041, an initial composite mask layer 60a, a BARC layer 603, and a patterned photoresist layer 604 are sequentially formed on the initial conductive layer 50. The initial composite mask layer 60a includes an initial silicon nitride layer 601a and an amorphous carbon layer 602a on the initial silicon nitride layer 601a. Figure 6 As shown in FIG. 6B, the patterned photoresist layer 604 has a plurality of openings corresponding to the positions of the first openings to be formed subsequently.

[0063] In step S1042, the initial composite mask layer is etched based on the patterned photoresist layer to form a patterned composite mask layer.

[0064] Step S1042 is a process of transferring the pattern in the photoresist layer to the initial composite mask layer to form the patterned composite mask layer.

[0065] Reference is made to Figure 6 and Figure 7 In step S1042, the BARC layer 603 and the initial composite mask layer are etched based on the patterned photoresist layer 604 to form a patterned composite mask layer 60. The patterned composite mask layer 60 includes a silicon nitride layer 601 and an amorphous carbon layer 602 on the silicon nitride layer 601.

[0066] In implementation, the pattern in the patterned photoresist layer can be transferred to the BARC layer and the initial composite mask layer by using a dry etching process, and then the patterned photoresist layer and the patterned BARC layer can be removed by using a dry etching process or a wet etching process (the etching solution can be a strong acid such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid). When the patterned BARC layer is removed, part of the patterned composite mask layer is also removed, thereby forming the patterned composite mask layer 60 as shown in FIG. 6C. Figure 7 To reduce the etching of the patterned composite mask layer, the etching selectivity ratio between the patterned composite mask layer and the patterned BARC layer can be improved.

[0067] In some embodiments, the patterned photoresist layer and the patterned bottom anti-reflective layer can also not be removed, and the patterned photoresist layer, the patterned bottom anti-reflective layer and the patterned composite mask layer are used as a mask to etch the initial conductive layer and the initial mask layer.

[0068] At step S1043, the initial conductive layer and the initial mask layer are etched based on the patterned composite mask layer to form the first opening, the first conductive layer and the first mask layer.

[0069] Here, the dry etching process or the wet etching process can be used to form the patterned composite mask layer, the first opening, the first conductive layer and the first mask layer.

[0070] Meanwhile referring to Figure 7 and Figure 8 At step S1043, the initial conductive layer 50 and the initial mask layer 30 are etched based on the patterned composite mask layer 60 to form the first opening 605 exposing the top support layer 205, the remaining initial mask layer 30 forms the first mask layer 31, and the remaining initial conductive layer 50 located above the first mask layer 31 forms the first conductive layer 51. In implementation, after the initial conductive layer 50 and the initial mask layer 30 are etched, the method of forming the semiconductor structure further includes: removing the patterned composite mask layer 60 located on the first conductive layer 51.

[0071] Next, referring to Figures 9 to 14 At step S105, the first conductive layer 51 and the first mask layer 31 are etched and removed while etching the layer stack structure 20 through the first opening 605 to form the capacitor structure 55 and the support structure 21.

[0072] In some embodiments, step S105 can be implemented by step S1051 and step S1052, in which:

[0073] At step S1051, the first conductive layer located above the first mask layer is etched and removed while etching the layer stack structure through the first opening, the remaining initial conductive layer forms the lower electrode, and the remaining layer stack structure forms the support structure.

[0074] Here, since the first conductive layer located above the first mask layer is removed, the lower electrode formed is relatively high, and thus the capacitor structure formed subsequently is also relatively high. Compared with the capacitor structure in the related art, the height of the capacitor structure can be increased in the embodiments of the present disclosure, so that the capacitance value can be increased. For example, when the height of the capacitor structure is increased by 30 nm, the capacitance value of the capacitor structure can be increased by at least 0.3 fF (femtofarad).

[0075] It should be noted that the step S1051 at least includes a process of removing the sacrificial layer in the laminated structure (the removal of the sacrificial layer needs to form an opening on the support layer except the bottom support layer) and a process of removing the first conductive layer above the first mask layer to form the lower electrode; wherein the laminated structure includes the laminated sacrificial layer and support layer, and the remaining laminated structure refers to the support layer remaining after the removal of the sacrificial layer.

[0076] In some embodiments, with reference to Figure 8 The laminated structure 20 includes a bottom support layer 201, a first sacrificial layer 202, an intermediate support layer 203, a second sacrificial layer 204 and a top support layer 205 laminated in sequence. Correspondingly, the etching of the laminated structure through the first opening in step S1051 can include steps S151 and S152, wherein:

[0077] In step S151, the first conductive layer is etched and removed while the top support layer is etched to form a second opening through the first opening.

[0078] Here, when the top support layer is etched to form the second opening through the first opening, the etching rate of the etching material selected for the top support layer and the first conductive layer should be substantially the same, so that the first conductive layer can be removed at the same time as the top support layer is opened. In other words, a special process is not needed to remove the excess first conductive layer, thereby simplifying the process flow.

[0079] In practice, the second opening in the top support layer for removing the second sacrificial layer can be formed by a dry etching process, and the etching gas in the dry etching process includes chlorine (Cl2), O2 and Ar, wherein the volume flow rate of chlorine is in the range of 100-200 standard cubic centimeters per minute (sccm), the volume flow rate of oxygen is in the range of 10-40 sccm, and the volume flow rate of argon is in the range of 50-80 sccm. In actual processes, the proportions of the above-mentioned etching gases can be adjusted according to the actual etching conditions to ensure that the first conductive layer is removed at the same time as the second opening is formed. For example, the volume flow rate of chlorine is 150 sccm, the volume flow rate of oxygen is 25 sccm, and the volume flow rate of argon is 65 sccm.

[0080] In step S152, the second sacrificial layer is removed through the second opening.

[0081] The material of the second sacrificial layer can include an oxide, and the second sacrificial layer can be removed by using a hydrofluoric acid solution, wherein the volume ratio of hydrogen fluoride to deionized water in the hydrofluoric acid solution is 1:150 to 1:250, for example, the volume ratio of hydrogen fluoride to deionized water in the hydrofluoric acid solution is 1:200.

[0082] After removing the second sacrificial layer, part of the intermediate support layer will be exposed. An opening can then be formed in the intermediate support layer to remove the first sacrificial layer, thereby forming a support structure.

[0083] In some embodiments, step S1051, which involves etching the stacked structure through the first opening, further includes steps S153 and S154, wherein:

[0084] Step S153: After removing the second sacrificial layer through the second opening, a portion of the intermediate support layer is exposed;

[0085] In step S154, while the third opening is formed in the patterned intermediate support layer, the first mask layer is removed; and the first sacrificial layer is removed through the third opening to expose the bottom support layer.

[0086] Here, the material of the first sacrificial layer may include borosilicate glass, and the first sacrificial layer may be removed using a hydrofluoric acid solution, wherein the volume ratio of hydrogen fluoride to deionized water in the hydrofluoric acid solution is 1:150 to 1:250, for example, the volume ratio of hydrogen fluoride to deionized water in the hydrofluoric acid solution is 1:200; the third opening is located in the intermediate support layer and is used to remove the first sacrificial layer.

[0087] When forming the third opening, the etching material should have approximately the same etching rate on both the intermediate support layer and the first mask layer. This allows the first mask layer to be removed while the intermediate support layer is being opened. This approach protects the top support layer, reducing its loss and improving its support function. Furthermore, it eliminates the need for a separate process to remove the first mask layer, further simplifying the process flow.

[0088] In implementation, a dry etching process can be used to form the third opening while simultaneously removing the first mask layer. The etching gas in the dry etching process can include at least one of the following: C4F8, C4F6, O2, and CH2F2. The volumetric flow rate of C4F8 is 5-30 sccm, C4F6 is 5-35 sccm, O2 is 40-80 sccm, and CH2F2 is 20-50 sccm. In actual practice, the proportions of the etching gases are adjusted according to the specific etching conditions to ensure that the first mask layer is removed simultaneously with the formation of the third opening. For example, the volumetric flow rate of C4F8 might be 15 sccm, C4F6 20 sccm, O2 60 sccm, and CH2F2 35 sccm.

[0089] The following will refer to Figures 9 to 13 Perform steps S151 to S154.

[0090] First, refer to Figure 9 Step S151 is performed, and the first conductive layer 51 above the first mask layer 31 is etched to expose the first mask layer 31 while forming the second opening 606 by etching the top support layer 205 through the first opening 605 (refer to Figure 8 ). Figure 10 In implementation, over-etching may occur when the top support layer 205 is etched to form the second opening 606, and a first recess A as shown in

[0091] Second, refer to Figure 11 Steps S152 and S153 are performed, and the second sacrificial layer 204 is removed through the second opening 606 (refer to Figure 9 or Figure 10 ). After the second sacrificial layer is removed, the middle support layer 203 is exposed.

[0092] Finally, refer to Figure 12 and Figure 13 Step S154 is performed, and the first mask layer is removed to expose the top support layer 205 while etching the middle support layer 203 along the second opening, i.e., patterning the middle support layer 203, to form a third opening 607 as shown in Figure 12 . Refer to Figure 13 , the first sacrificial layer 202 is removed through the third opening 607 to expose the bottom support layer 201, so that the bottom support layer 201, the remaining middle support layer 203, and the remaining top support layer 205 can constitute the support structure 21.

[0093] As can be seen from Figure 12 , there is a height difference H between the top surface of the lower electrode 52 and the top surface of the top support layer 205, so that the lower electrode 52 in the embodiment of the disclosure is higher than the lower electrode in the related art by H, so that the height-depth ratio of the subsequently formed capacitor structure is large, thereby improving the capacitance value of the capacitor structure, and further maintaining the data stored in the DRAM for a longer time.

[0094] It should be noted that the first mask layer can be removed at the same time as the third opening is formed in the middle support layer by adjusting the etching solution; in addition, over-etching may occur when the third opening is etched, and a second recess B as shown in Figure 12 may be formed in the first sacrificial layer 202. In addition, part of the top support layer 205 may be consumed when the first sacrificial layer 202 is removed, so that the thickness of the top support layer 205 is thinned.

[0095] Step S1052 is performed, and a dielectric layer and an upper electrode are formed on the surface of the lower electrode and the support structure in sequence to form a capacitor structure.

[0096] Here, the material of the dielectric layer can be selected from high-K dielectric materials to increase the capacitance of the capacitor structure per unit area. For example, the material of the dielectric layer can include one of zirconium oxide (ZrO x ), hafnium oxide (HfO x ), zirconium titanium oxide (ZrTiO x ), ruthenium oxide (RuO x ), antimony oxide (SbO x ), aluminum oxide (AlO x ), barium titanate (BaTiO3), or a stack of two or more of the above materials.

[0097] The material of the upper electrode can include one of tantalum (Ta), ruthenium (Ru), cobalt (Co), gold (Au), tungsten (W), titanium (Ti), nickel (Ni), aluminum (Al), platinum (Pt), titanium nitride, tantalum nitride (TaN), N-type polysilicon, P-type polysilicon, or a stack of two or more of the above materials. The material of the upper electrode can be the same as the material of the lower electrode, for example, both the upper electrode and the lower electrode include titanium nitride. Alternatively, the material of the upper electrode can be different from the material of the lower electrode, for example, the material of the upper electrode is tantalum and the material of the lower electrode is titanium nitride. In implementation, the dielectric layer and the upper electrode can be formed by any suitable deposition process, such as chemical vapor deposition, atomic layer deposition, etc.

[0098] Referring to Figure 13 , the dielectric layer material and the upper electrode material are sequentially deposited on the support structure 21 and the lower electrode 52 to form the dielectric layer 53 and the upper electrode 54 as shown in Figure 14 , thereby forming the capacitor structure 55.

[0099] The disclosure also provides a semiconductor structure, referring to Figure 14 , the semiconductor structure includes: a substrate 10; a capacitor structure 55 and a support structure 21 formed on the substrate 10 by the method of any of the above embodiments; and wherein the top surface of the capacitor structure 55 is higher than the top surface of the support structure 21. In implementation, the height difference between the top surface of the capacitor structure 55 and the top surface of the support structure 21 ranges from 30 nm to 45 nm, for example, can be 35 nm, 38 nm, 40 nm, 42 nm.

[0100] In some embodiments, the capacitor structure includes a cylindrical capacitor structure or a columnar capacitor structure.

[0101] In the embodiments of the disclosure, since the capacitor structure and the support structure are formed by the method for forming a semiconductor structure provided by the embodiments of the disclosure, the lower electrode in the capacitor structure has good quality, the capacitor structure has a large capacitance, and the support structure has a better support effect, thereby improving the stability of the capacitor structure.

[0102] In several embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-targeted manner. The structural embodiments described above are only illustrative, for example, the division of the units is only a logical functional division, and actual implementation can have another division manner, for example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling between the components shown or discussed.

[0103] The units described above as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place or distributed on multiple network units; part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0104] The features disclosed in several method or structure embodiments provided in the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments or structure embodiments.

[0105] The above is only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided, the substrate including a substrate, a stacked structure and an initial mask layer, the stacked structure being located on the substrate and the initial mask layer being located on the top surface of the stacked structure; A capacitor hole is formed, which penetrates the initial mask layer and the stacked structure; An initial conductive layer is formed, which covers the inner wall of the capacitor hole and the top surface of the initial mask layer; The initial conductive layer and the initial mask layer are etched to form a first opening, the remaining initial mask layer forms a first mask layer, and the remaining initial conductive layer above the first mask layer forms a first conductive layer. While etching the stacked structure through the first opening, the first conductive layer and the first mask layer are etched away to form a capacitor structure and a support structure.

2. The method according to claim 1, characterized in that, Forming an initial conductive layer includes: The initial conductive layer is filled into the capacitor hole to form a columnar lower electrode; Alternatively, the initial conductive layer may be deposited on the bottom and sidewalls of the capacitor hole to form a cylindrical lower electrode.

3. The method according to claim 1, characterized in that, The formation of the capacitor structure and the support structure includes: While etching the stacked structure through the first opening, the first conductive layer located above the first mask layer is etched away, the remaining initial conductive layer forms the lower electrode, and the remaining stacked structure forms the support structure. A dielectric layer and an upper electrode are sequentially formed on the surfaces of the lower electrode and the support structure to form the capacitor structure.

4. The method according to claim 3, characterized in that, The stacked structure includes a bottom support layer, a first sacrificial layer, an intermediate support layer, a second sacrificial layer, and a top support layer stacked sequentially. Etching the stacked structure through the first opening includes: simultaneously etching away the first conductive layer while etching the top support layer through the first opening to form a second opening; The second sacrificial layer is removed through the second opening.

5. The method according to claim 4, characterized in that, Etching the stacked structure through the first opening further includes: removing the second sacrificial layer through the second opening to expose a portion of the intermediate support layer; removing the first mask layer while patterning the intermediate support layer to form a third opening; and removing the first sacrificial layer through the third opening to expose the bottom support layer.

6. The method according to claim 4, characterized in that, The second opening is formed by etching using a dry etching process, while the first conductive layer is removed. The etching gases used in the dry etching process include chlorine, oxygen, and argon.

7. The method according to claim 5, characterized in that, The first sacrificial layer is made of borosilicate glass, and the second sacrificial layer is made of oxide. The second sacrificial layer and the first sacrificial layer are removed using a hydrofluoric acid solution.

8. The method according to claim 7, characterized in that, The third opening is formed by etching using a dry etching process, while the first mask layer is removed. The etching gas in the dry etching process includes at least one of the following: C4F8, C4F6, O2, CH2F2.

9. The method according to any one of claims 1 to 8, characterized in that, Forming the first conductive layer and the first mask layer includes: An initial composite mask layer and a patterned photoresist layer are sequentially formed on the initial conductive layer; The initial composite mask layer is etched based on the patterned photoresist layer to form a patterned composite mask layer; Based on the patterned composite mask layer, the initial conductive layer and the initial mask layer are etched to form the first opening, the first conductive layer, and the first mask layer.

10. The method according to any one of claims 1 to 8, characterized in that, The formation of the capacitor hole includes: The initial mask layer is etched with a first pattern identical to the capacitor hole pattern to form an initial mask layer with the first pattern; The stacked structure is etched through the initial mask layer having the first pattern to form the capacitor holes that expose the substrate.

11. The method according to claim 10, characterized in that, The initial mask layer includes a polysilicon layer and a silicon oxide layer located on the polysilicon layer.

12. A semiconductor structure, characterized in that, in, The semiconductor structure includes: Substrate; The capacitor structure and the support structure are located on the substrate and formed using the method according to any one of claims 1 to 11; The top surface of the capacitor structure is higher than the top surface of the support structure.

13. The structure according to claim 12, characterized in that, The capacitor structure includes a double-sided capacitor structure or a columnar capacitor structure.

14. The structure according to claim 12, characterized in that, The height difference between the top surface of the capacitor structure and the top surface of the support structure ranges from 30 nm to 45 nm.

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