Adaptive synchronized defibrillator and defibrillation control method for different abnormal heart rhythms

Abstract

This invention belongs to the field of defibrillation technology and provides an adaptive synchronized defibrillator and defibrillation method for different abnormal heart rhythms, solving the current problem of not being able to achieve adaptive synchronized defibrillation for different abnormal heart rhythms. The system includes a control module, a charging circuit, an energy storage capacitor, a high-voltage detection circuit, a discharge circuit, and a wave detection circuit. The control module controls whether to activate the R-wave detection module, drive circuit, charging circuit, high-voltage detection circuit, and discharge circuit based on different ECG classification results. By comprehensively utilizing the advantages of software and hardware defibrillation, adaptive synchronized defibrillation can be achieved for various abnormal heart rhythms, exhibiting high efficiency, low latency, and high-quality defibrillation performance.

Description

Technical Field

[0001] This invention belongs to the field of defibrillation technology, and particularly relates to electrocardiogram detection and adaptive synchronous defibrillators and defibrillation control methods for different abnormal heart rhythms. Background Technology

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] Defibrillation methods include synchronized and asynchronous defibrillation. For patients with severe arrhythmias such as ventricular fibrillation, ventricular flutter, and pulseless ventricular tachycardia, who are completely unconscious, defibrillation can be performed directly without considering their own rhythm, simply by charging and discharging. However, for atrial fibrillation, atrial flutter, and supraventricular tachycardia, where the patient still has their own rhythm despite the arrhythmia, synchronized defibrillation should be used. This means the discharge pulse must be synchronized with the patient's heartbeat, ensuring the pulse falls within the heart's absolute refractory period, typically at the falling edge of the R wave. This is because, within the absolute refractory period, no amount of stimulation will induce new excitation, preventing the pulse from falling into the vulnerable period of the ventricles near the peak of the T wave and causing more severe ventricular fibrillation. Since different arrhythmias have different waveforms and reflect different physiological states, the required defibrillation energy also varies.

[0004] However, current defibrillators operate in manual or fixed energy output modes for different abnormal heart rhythms, failing to achieve adaptive synchronous defibrillation for various abnormal rhythms. Furthermore, current defibrillators process ECG data using either software or hardware methods. Software-based ECG processing offers high accuracy but suffers from a significant delay between rhythm analysis and defibrillation execution; hardware-based ECG processing is highly efficient, with a very low delay from the R wave to defibrillation, but it can analyze a limited range of heart rhythms, thus restricting its application. Summary of the Invention

[0005] To address at least one of the technical problems mentioned above, this invention provides an adaptive synchronized defibrillator and defibrillation control method for different abnormal heart rhythms. It combines the advantages of hardware and software, and can achieve high-efficiency, low-latency, and high-quality synchronized defibrillation while handling multiple abnormal heart rhythms, thereby greatly reducing the incidence of sudden cardiac death.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] The first aspect of the present invention provides an adaptive synchronized defibrillator for different abnormal heart rhythms, including a control module, a charging circuit, an energy storage capacitor, a high voltage detection circuit, a discharge circuit, and an R wave detection circuit.

[0008] The control module classifies the input electrocardiogram signal to obtain the abnormal heart rhythm classification result, and determines whether defibrillation is needed. If defibrillation is needed, the first control signal is output to control the charging circuit to charge the energy storage capacitor. At the same time, the high voltage detection circuit detects the current voltage value across the energy storage capacitor. If the voltage reaches the charging voltage threshold, charging stops; otherwise, charging continues.

[0009] After the energy storage capacitor is fully charged, it is determined whether the ECG signal is one that requires simultaneous defibrillation. If so, a second control signal is output to call the R-wave detection circuit to discharge at the falling edge of the ECG R-wave to achieve simultaneous defibrillation. Otherwise, the discharge circuit is directly driven to discharge to complete the defibrillation.

[0010] In one implementation, the R-wave detection circuit includes an R-wave bandpass filter, a peak detection circuit, a proportional circuit, and a comparison trigger circuit;

[0011] The R-wave bandpass filter extracts the R-wave signal from the ECG signal and outputs it to the peak detection circuit. The peak detection circuit detects the peak value of the input signal and inputs the detected ECG peak value to the proportional circuit. The proportional circuit multiplies the peak value by a coefficient k less than 1. The comparison trigger circuit compares the output signals of the R-wave bandpass filter and the proportional circuit. When the output of the R-wave bandpass filter is greater than the output of the proportional circuit, a high level is output, indicating the arrival of the R-wave.

[0012] In one embodiment, the adaptive synchronous defibrillator further includes ECG electrodes, an ECG acquisition module, and a filtering circuit module. The ECG electrodes are connected to the input terminal of the ECG acquisition module, the output terminal of the ECG acquisition module is connected to the input terminal of the filtering circuit module, and the output terminal of the filtering circuit module is connected to the control module.

[0013] As one implementation, the control module classifies the input ECG signals using a lightweight ECG classification method based on SNN.

[0014] A second aspect of the present invention provides an adaptive synchronized defibrillation control method for different abnormal heart rhythms, comprising the following steps:

[0015] Acquire the patient's electrocardiogram (ECG) signal;

[0016] The electrocardiogram (ECG) signal is classified to obtain abnormal heart rhythm classification results. Based on the classification results, it is determined whether defibrillation is needed. If so, a defibrillation energy threshold is set for each type of ECG signal to be defibrillated, and the charging circuit is controlled to charge the energy storage capacitor. At the same time, the high voltage detection circuit detects the current voltage value across the energy storage capacitor. If the charging voltage threshold is reached, charging stops; otherwise, charging continues.

[0017] After the energy storage capacitor is fully charged, it is determined whether the ECG signal is one that requires simultaneous defibrillation. If so, the R-wave detection circuit is invoked to discharge at the falling edge of the ECG R-wave to achieve simultaneous defibrillation. Otherwise, the discharge circuit is directly driven to discharge and complete the defibrillation.

[0018] As one implementation method, the classification of electrocardiogram (ECG) signals employs a lightweight ECG classification method based on Sub-Neural Networks (SNN).

[0019] As one implementation method, the method for determining the arrival of the R wave in the electrocardiogram (ECG) is as follows: the R wave signal in the ECG signal is filtered out by an R-wave bandpass filter circuit. The filtered ECG signal is then passed through a peak detection circuit to detect the peak value. The peak value is multiplied by a coefficient k less than 1 by a proportional circuit. The filtered ECG signal is compared with the output of the proportional circuit. When the filtered ECG signal is greater than the output, a high level is output. The arrival of the R wave can be determined by detecting the high level of the output.

[0020] As one implementation method, the ECG signal preprocessing is included before classification. Based on the frequency distribution of ECG signal and noise at different scales, wavelet transform is performed on the ECG signal to obtain wavelet coefficients of each layer. Threshold processing is performed on the wavelet coefficients of each layer. The three-dimensional amplitude of each wavelet coefficient is compared with the threshold and the ECG signal is reconstructed to obtain the noise-reduced ECG signal.

[0021] A third aspect of the present invention provides a computer-readable storage medium.

[0022] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the adaptive synchronized defibrillation control method for different abnormal heart rhythms as described above.

[0023] A fourth aspect of the present invention provides a computer device.

[0024] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the steps of the adaptive synchronized defibrillation control method for different abnormal heart rhythms as described above.

[0025] The beneficial effects of this invention are:

[0026] 1. The adaptive synchronous defibrillator of the present invention combines the advantages of software defibrillation and hardware defibrillation. It can detect, analyze and synchronously defibrillate a variety of abnormal heart rhythms while ensuring the accuracy of ECG classification. It has the advantages of high efficiency, low latency and high quality, and is of great significance for reducing the clinical symptoms caused by a variety of abnormal heart rhythms.

[0027] 2. This invention processes classification tasks with low power consumption and captures the time, morphology, and characteristics of electrocardiogram (ECG) signals. Once a patient's ECG is input into the system, it can be quickly classified to determine the current disease type, and the disease type is used to determine whether defibrillation and synchronized defibrillation are needed. This system can achieve efficient, accurate, and low-power automatic diagnosis of ECG arrhythmias.

[0028] 3. This invention performs R-wave detection in ECG using hardware. Hardware methods offer excellent real-time performance. The R-wave detection circuit consists of an R-wave bandpass filter, a peak detection circuit, a proportional circuit, and a comparison trigger circuit. It can accurately locate the R-wave position when it arrives and output a +5V high level. The arrival of the R-wave can be detected by detecting the high level, and the discharge can be controlled to achieve synchronous defibrillation. Attached Figure Description

[0029] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0030] Figure 1 This is a schematic diagram of the overall structure of the adaptive synchronous defibrillator for different abnormal heart rhythms according to Embodiment 1 of the present invention;

[0031] Figure 2 This is a schematic diagram of the ECG acquisition circuit and filtering circuit according to Embodiment 1 of the present invention;

[0032] Figure 3 This is a schematic diagram of the R-wave detection circuit according to Embodiment 1 of the present invention;

[0033] Figure 4 This is a schematic diagram of the charging and discharging circuit of the defibrillator device according to Embodiment 1 of the present invention;

[0034] Figure 5 This is a flowchart of the defibrillation device according to Embodiment 2 of the present invention;

[0035] Figure 6 This is a flowchart of the electrocardiogram classification procedure according to Embodiment 2 of the present invention.

[0036] In the diagram, 1-ECG electrode, 2-ECG signal acquisition module, 21-ECG electrode interface, 22-transient suppression tube, 23-instrument amplifier, 24-right leg drive circuit, 3-filter circuit module, 31-high-pass filter circuit, 32-low-pass filter circuit, 33-50Hz notch filter circuit, 4-control module, 5-R-wave detection circuit, 51-ECG R-wave bandpass circuit, 52-peak detection circuit, 53-proportional circuit, 54-comparison trigger circuit, 6-drive circuit, 61-first drive circuit, 62-second drive circuit, 7-charging circuit, 8-high voltage detection circuit, 9-discharge circuit, 10-energy storage capacitor, 11-power supply, 12-MOSFET switch, 13-high voltage rectifier diode, 14-IGBT discharge tube. Detailed Implementation

[0037] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0038] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0039] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0040] As described in the background section, current defibrillators operate in manual or fixed energy output modes for different abnormal heart rhythms, failing to achieve adaptive synchronous defibrillation for various abnormal heart rhythms. To address these issues, this invention proposes an adaptive synchronous defibrillator and defibrillation method for different abnormal heart rhythms.

[0041] Example 1

[0042] like Figure 1 As shown, this embodiment provides an adaptive synchronous defibrillator for different abnormal heart rhythms, including ECG electrodes 1, ECG signal acquisition module 2, filtering circuit module 3, control module 4, R-wave detection circuit 5, driving circuit 6, charging circuit 7, high voltage detection circuit 8, discharge circuit 9, and energy storage capacitor 10.

[0043] The ECG electrode 1 serves as a shared electrode for ECG detection and discharge, used to detect ECG signals and conduct discharge signals;

[0044] The ECG acquisition module 2 transmits the real-time acquired ECG signal to the filtering circuit module 3. The filtering circuit module 3 filters out interference signals in the ECG signal and obtains a pure ECG signal, which is then transmitted to the control module 4 to ensure the determination of whether the ECG is abnormal.

[0045] It should be noted that in this embodiment, the control module 4 can be a microcontroller. The specific model of the microcontroller can be set by those skilled in the art according to the specific working conditions, and will not be described in detail here.

[0046] The control module 4 classifies the pure electrocardiogram (ECG) signal and controls whether to activate the R-wave detection circuit 5, drive circuit 6, charging circuit 7, high-voltage detection circuit 8, and discharge circuit 9 based on the ECG classification results.

[0047] The control module 4 classifies the input electrocardiogram signal to obtain the abnormal heart rhythm classification result and determines whether defibrillation is needed. If defibrillation is needed, the first control signal is output to control the charging circuit 7 to charge the energy storage capacitor. At the same time, the high voltage detection circuit 8 detects the current voltage value across the energy storage capacitor. If the voltage reaches the charging voltage threshold, charging stops; otherwise, charging continues.

[0048] After the energy storage capacitor is fully charged, it is determined whether the ECG signal is one that requires synchronous defibrillation. If so, a second control signal is output to call the R-wave detection circuit 5 to discharge at the falling edge of the ECG R-wave for synchronous defibrillation. If the ECG classification result is an ECG signal that requires asynchronous defibrillation, the drive circuit 6, charging circuit 7, and discharging circuit 9 are directly called for defibrillation.

[0049] Figure 2 The ECG acquisition module 2 includes an ECG electrode interface 21, a transient suppression transistor 22, an instrument amplifier 23, and a right leg drive circuit 24. The filter circuit module 3 includes a high-pass filter circuit 31, a low-pass filter circuit 32, and a 50Hz notch filter circuit 33. One end of the ECG electrode interface 21 is connected to the ECG patch, and the other end is connected to the input terminals of the transient suppression transistor 22 and the instrument amplifier 23, respectively. The two ends of the right leg drive circuit 24 are connected to the two input terminals of the instrument amplifier 23, respectively. The output terminal OUT1 of the instrument amplifier 23 is connected to the input terminal of the high-pass filter circuit 31, the output terminal OUT2 of the high-pass filter circuit 31 is connected to the input terminal of the low-pass filter circuit 32, the output terminal OUT3 of the low-pass filter circuit 32 is connected to the input terminal of the 50Hz notch filter circuit 33, and a clean ECG signal is output through the output terminal OUT4 of the 50Hz notch filter circuit 33.

[0050] The high-pass filter circuit 31 uses a fourth-order Butterworth high-pass filter to filter out low-frequency interference such as baseline drift; the low-pass filter circuit 32 uses a fourth-order Butterworth low-pass filter to filter out high-frequency interference such as electromyography (EMG) signals; and the 50Hz notch filter circuit 33 uses a dual-T type 50Hz notch filter to eliminate power frequency interference signals. The filter circuit module 3 filters the acquired ECG signals to obtain a relatively pure ECG signal.

[0051] The control module 4 plays a coordinating and controlling role in the entire system; the drive circuit 6 acts as the driver for the charging circuit 7 and the discharging circuit 9, driving the charging circuit and the discharging circuit to charge and discharge when defibrillation is required.

[0052] The charging circuit employs a flyback charging circuit for rapid charging, achieving high-quality, rapid charging of the energy storage capacitor while maintaining a relatively simple structure. The ECG classification module utilizes a lightweight ECG classification method based on Spike Neural Network (SNN), enabling continuous monitoring of patient arrhythmias on defibrillator devices.

[0053] Its advantages lie in the fact that once a patient's electrocardiogram (ECG) is input into the system, it can be quickly classified to determine the current disease type, and the disease type can be used to determine whether defibrillation and synchronized defibrillation are needed. This system can achieve efficient, accurate, and low-power automatic diagnosis of ECG arrhythmias.

[0054] Figure 3 The ECG R-wave detection circuit 5 includes an ECG R-wave bandpass circuit 51, a peak detection circuit 52, a proportional circuit 53, and a comparison trigger circuit 54.

[0055] The R-wave bandpass filter 51 filters out the R-wave signal from the ECG signal and outputs it to the peak detection circuit 52. The peak detection circuit 52 inputs the detected ECG peak value to the proportional circuit 53. The proportional circuit 53 multiplies the peak value by a coefficient k less than 1. The comparison trigger circuit 54 is used to compare the output signals of the R-wave bandpass filter circuit 51 and the proportional circuit 53. When the output of the R-wave bandpass filter is greater than the output of the proportional circuit, a high level output indicates the arrival of the R-wave.

[0056] Its advantage lies in the fact that, since the ECG signal ranges from 0.05Hz to 100Hz, spectral analysis shows that the R-wave frequency is mainly between 10Hz and 25Hz, with a peak value around 17Hz. Therefore, using an ECG R-wave bandpass circuit can quickly filter out the R-wave signal from the ECG signal. Afterwards, a peak detection circuit detects the peak value of the bandpassed ECG signal. Then, a proportional circuit multiplies the peak value by a coefficient k slightly less than 1; in this embodiment, the value ranges from 0.5 to 0.9, which can be adjusted according to actual conditions. The bandpassed ECG signal is compared with the output of the proportional circuit. When the bandpassed ECG signal is greater than the output, a high-level output is generated. The microcontroller can determine the arrival of the R-wave by detecting the high level, thus achieving synchronized defibrillation.

[0057] like Figure 4 The diagram shows the charging and discharging circuit of the defibrillator. The charging circuit 7 adopts a flyback topology transformer structure, which can quickly raise the voltage across the energy storage capacitor 10 to the specified voltage. The driving circuit 6 includes a first driving circuit 61 and a second driving circuit 62.

[0058] When charging is required, under the power supply 11, the control module 4 drives the MOSFET switch 12 to quickly turn on via the first drive circuit 61, allowing the secondary side of the flyback transformer to store energy, which is then charged to the energy storage capacitor 10 via the high-voltage rectifier diode 13. The high-voltage feedback circuit 8 feeds back the voltage across the energy storage capacitor 10 to the control module 4 in real time. When the voltage across the energy storage capacitor 10 reaches a set value, the control module 4 drives the IGBT discharge tubes 14 to turn on sequentially at appropriate times via the second drive circuit 62, completing the discharge defibrillation.

[0059] The high-voltage feedback circuit 8 feeds back the voltage across the energy storage capacitor to the control module 4 in real time to control the charging energy and achieve different discharge energies for different abnormal heart rhythms; the charging circuit 7 adopts a transformer structure with a flyback topology, which can quickly raise the voltage across the energy storage capacitor to the specified voltage; the ECG R-wave detection circuit 5 plays a role when synchronous defibrillation is required; and the discharge circuit drives the IGBT switch of the H-bridge through the drive circuit to achieve discharge when discharge is required.

[0060] The advantage of the above scheme lies in its ability to design a synchronized defibrillation system for abnormal heart rhythms requiring simultaneous defibrillation. This ensures defibrillation occurs at the falling edge of the R-wave on the electrocardiogram (ECG). The area near the T-wave in the ECG signal is a vulnerable period for the heart; if the defibrillation pulse falls near the T-wave, it will not only fail to terminate the abnormal rhythm but may also trigger more severe ventricular fibrillation. Hardware-based R-wave detection offers excellent real-time performance. The R-wave detection circuit consists of an R-wave bandpass filter, a peak detection circuit, a proportional circuit, and a comparison trigger circuit. It can accurately locate the R-wave upon its arrival and output a +5V high-level signal. The microcontroller detects the arrival of the R-wave by detecting this high-level signal and controls the discharge to achieve synchronized defibrillation.

[0061] Example 2

[0062] like Figure 5 As shown, this embodiment provides an adaptive synchronized defibrillation control method for different abnormal heart rhythms, including the following steps:

[0063] S1: Acquire the patient's electrocardiogram (ECG) signal;

[0064] S2: Preprocess the electrocardiogram signal;

[0065] S3: Classify the preprocessed ECG signals to obtain abnormal heart rhythm classification results;

[0066] S4: Determine whether defibrillation is needed based on the classification results. If so, set the defibrillation energy threshold corresponding to each type of cardiac signal to be defibrillated, control the charging circuit to charge the energy storage capacitor, and at the same time, the high voltage detection circuit detects the current voltage value across the energy storage capacitor. If the charging voltage threshold is reached, charging stops; otherwise, charging continues.

[0067] After the energy storage capacitor is fully charged, it is determined whether the ECG signal to be defibrillated requires synchronous defibrillation. If so, the R-wave detection circuit is invoked to discharge at the falling edge of the ECG R-wave to achieve synchronous defibrillation. If synchronous defibrillation is not required, the discharge circuit is directly driven to discharge to complete the defibrillation.

[0068] In step S2, the preprocessing of the electrocardiogram signal includes the following steps: The signal preprocessing includes the following steps:

[0069] S21: Based on the frequency distribution of ECG signals and noise at different scales, wavelet transform is performed on the signals to obtain wavelet coefficients for each layer;

[0070] S22: Then, threshold processing is performed on the wavelet coefficients of each layer;

[0071] S23: Noise reduction is achieved through signal reconstruction to obtain the denoised ECG signal.

[0072] In S22, the threshold formula is set as follows:

[0073]

[0074] In the formula, λ is the threshold, MAD is the median amplitude of the first layer wavelet coefficients, 0.6745 is the standard deviation adjustment coefficient of Gaussian noise, and N is the signal length.

[0075] By using a soft thresholding method, the reconstructed signal is relatively smooth. The amplitude of each wavelet coefficient |x| is compared with a set threshold λ, as shown in the following formula:

[0076]

[0077] The return value sgn(x) reflects the sign of the parameter x, according to the following formula:

[0078]

[0079] After inverse wavelet transform, the electrocardiogram (ECG) is reconstructed using the processed wavelet coefficients to obtain a denoised ECG signal.

[0080] In S3, a lightweight ECG classification method based on SNN is used to classify ECG signals.

[0081] like Figure 6 As shown, the electrocardiogram signal is segmented and morphological features are extracted. First, the position of the R wave is identified as a points forward and b points backward as the heartbeat, and different types of heartbeats are segmented.

[0082] In this case, a can be 100 and b can be 200.

[0083] Specifically, for biologically preserved neural model (LIF) neurons, a synapse is the connection between a presynaptic neuron and a postsynaptic neuron. Within the time constant τ, the membrane potential U... j (t) accumulates leakage current and input peaks generated by different presynaptic neurons i, potential U j (t) can store time information, and the calculation formula is as follows:

[0084]

[0085] Where τ represents the time constant of the leakage current, and R and I(t) represent the input resistance and driving current in the circuit composed of LIF neurons, respectively.

[0086] Since the digital instrumentation tests continuous current and voltage, the differential equation (4) is transformed into a difference equation for calculation. From the perspective of the difference equation, the membrane voltage is expressed as:

[0087] U j(t)=λU j (t - 1)+∑ i w ij U i (t) (5)

[0088] Among them, U j (t) represents the membrane voltage of postsynaptic neuron j at time t, w ij For synaptic weights, the synaptic weights are the weights of the inputs to the presynaptic neuron i.

[0089] SNN layers with LIF neurons encode the input numerical signal into binary peaks, U j (t) and w ij Multiplication is transformed into addition.

[0090] When the membrane voltage U j (t) exceeds the voltage threshold v th At time t, the action potential is activated, and neuron j produces a spike. The formula for calculating the peak output at time t is:

[0091]

[0092] Next, the membrane potential U j (t) When the voltage drops to the reset voltage vr, the neuron enters the refractory period and sets the reset voltage vr to 0. During the refractory period, the membrane potential of the postsynaptic neuron j remains unchanged until the next cycle when it responds to a new stimulus.

[0093] In SNN layers, the membrane potential of LIF neurons approximates the original activation function in convolution, and also supports other network layers in convolutional neural networks (CNNs), such as convolutional layers and fully connected layers.

[0094] After the first SNN layer, the input ECG data is reshaped into local features:

[0095] F = f 1 ,f 2 ,f 3 ,……,f c ]∈R 1×W×C (7)

[0096] The size is 1×W, where C is the channel number, fs represents the feature vector of channel s, and the value of F is the product of all channels.

[0097] To address the limitations of shallow networks, the following steps are taken: First, the vector F is fed into the global layer, matching its output dimension with its own channel number to refine the global information, resulting in the vector Fp = [fp1, fp2, ..., fpc](Fp) ∈ R1 × C. The GMP operation then compresses the feature vector F into a one-dimensional feature Fp representing the importance of each channel from a global perspective, as shown in the following equation:

[0098]

[0099] Let f represent the j-th element in the i-th channel of feature f, and N be the number of elements in f.

[0100] The feature vector Fp is then fed into a bottleneck structure, which consists of two convolutional layers with a kernel size of 1. There is a hidden layer between the convolutional layers. The output convolutional layer uses the same number of convolutional neurons as the input layer to obtain new features. After the last convolutional layer, a sigmoid activation layer is used to make Fc contain non-mutually exclusive multi-channel information and normalize it between 0 and 1.

[0101] The calculation formula is as follows:

[0102] Fc = σ(g(Fp, W)) = σ(W2δ(W1Fp)) (9)

[0103] Where δ is the ReLU function and σ is the sigmoid function.

[0104] Ultimately, the feature vector It is obtained by multiplying the feature Fc with the previous feature vector f by the channel. Adaptive calibration is achieved using the learned channel information, using the following formula:

[0105]

[0106] The CAM is integrated between two SNN layers, providing an optimal solution for tuning hyperparameters and configurations in both the SNN-based module and the CAM to achieve ECG classification.

[0107] In S4, the method for determining the arrival of the ECG R wave is as follows: The R wave signal in the ECG signal is filtered out from the ECG signal through the R wave bandpass circuit. The filtered ECG signal is then passed through the peak detection circuit to detect the peak value of the ECG signal. The peak value is then multiplied by a coefficient k less than 1 by the proportional circuit. The filtered ECG signal is compared with the output of the proportional circuit. When the filtered ECG signal is greater than the output, a high level is output. The arrival of the R wave can be determined by detecting the high level.

[0108] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) containing computer-usable program code.

[0109] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0110] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0111] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps of the functions specified in one or more boxes. Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0112] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An adaptive synchronized defibrillator for different abnormal heart rhythms, characterized in that, It includes a control module, a charging circuit, an energy storage capacitor, a high-voltage detection circuit, a discharge circuit, and an R-wave detection circuit; The control module classifies the input ECG signal to obtain abnormal heart rhythm classification results and determines whether defibrillation is needed. If so, it outputs a first control signal to control the charging circuit to charge the energy storage capacitor. The charging circuit adopts a flyback topology transformer structure to quickly raise the voltage across the energy storage capacitor to a specified voltage. At the same time, the high voltage detection circuit detects the current voltage value across the energy storage capacitor. If it reaches the charging voltage threshold, charging stops; otherwise, charging continues. After the energy storage capacitor is fully charged, it is determined whether the ECG signal is a signal that requires simultaneous defibrillation. If so, a second control signal is output to call the R-wave detection circuit to discharge at the falling edge of the ECG R-wave to achieve simultaneous defibrillation. Otherwise, the discharge circuit is directly driven to discharge to complete the defibrillation. The R-wave detection circuit includes an R-wave bandpass filter, a peak detection circuit, a proportional circuit, and a comparison trigger circuit; The R-wave bandpass filter filters out the R-wave signal from the ECG signal and outputs it to the peak detection circuit. The peak detection circuit inputs the detected ECG peak value to the proportional circuit, which multiplies the peak value by a coefficient k less than 1. The comparison trigger circuit compares the output signals of the R-wave bandpass filter and the proportional circuit. When the output of the R-wave bandpass filter is greater than the output of the proportional circuit, a high level output indicates the arrival of the R-wave.

2. The adaptive synchronized defibrillator for different abnormal heart rhythms according to claim 1, characterized in that, The adaptive synchronous defibrillator also includes ECG electrodes, an ECG acquisition module, and a filtering circuit module. The ECG electrodes are connected to the input terminal of the ECG acquisition module, the output terminal of the ECG acquisition module is connected to the input terminal of the filtering circuit module, and the output terminal of the filtering circuit module is connected to the control module.

3. The adaptive synchronized defibrillator for different abnormal heart rhythms according to claim 1, characterized in that, The control module classifies the input ECG signals using a lightweight ECG classification method based on SNN.

4. An adaptive synchronized defibrillation control method for different abnormal heart rhythms, characterized in that, Includes the following steps: Acquire the patient's electrocardiogram (ECG) signal; The electrocardiogram signal is classified to obtain the abnormal heart rhythm classification result. Based on the classification result, it is determined whether defibrillation is needed. If so, the charging circuit is controlled to charge the energy storage capacitor. The charging circuit adopts a flyback topology transformer structure to quickly raise the voltage across the energy storage capacitor to the specified voltage. At the same time, the high voltage detection circuit detects the current voltage value across the energy storage capacitor. If it reaches the charging voltage threshold, charging stops; otherwise, charging continues. After the energy storage capacitor is fully charged, it is determined whether the ECG signal is a signal that requires simultaneous defibrillation. If so, the R-wave detection circuit is invoked to discharge at the falling edge of the ECG R-wave to achieve simultaneous defibrillation; otherwise, the discharge circuit is directly driven to discharge to complete defibrillation. The R-wave detection circuit includes an R-wave bandpass filter, a peak detection circuit, a proportional circuit, and a comparison trigger circuit; The R-wave bandpass filter filters out the R-wave signal from the ECG signal and outputs it to the peak detection circuit. The peak detection circuit inputs the detected ECG peak value to the proportional circuit, which multiplies the peak value by a coefficient k less than 1. The comparison trigger circuit compares the output signals of the R-wave bandpass filter and the proportional circuit. When the output of the R-wave bandpass filter is greater than the output of the proportional circuit, a high level output indicates the arrival of the R-wave.

5. The adaptive synchronized defibrillation control method for different abnormal heart rhythms according to claim 4, characterized in that, In the classification of electrocardiogram (ECG) signals, a lightweight ECG classification method based on SNN is adopted.

6. The adaptive synchronized defibrillation control method for different abnormal heart rhythms according to claim 4, characterized in that, Before classifying the ECG signal, preprocessing of the ECG signal is also included. Based on the frequency distribution of the ECG signal and noise at different scales, wavelet transform is performed on the ECG signal to obtain wavelet coefficients of each layer. Thresholding is performed on the wavelet coefficients of each layer. After comparing the three-dimensional amplitude of each wavelet coefficient with the threshold, the ECG signal is reconstructed to obtain the noise-reduced ECG signal.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps in the adaptive synchronous defibrillation control method for different abnormal heart rhythms as described in any one of claims 4-6.

8. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps in the adaptive synchronous defibrillation control method for different abnormal heart rhythms as described in any one of claims 4-6.

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