Semiconductor structure

Abstract

A semiconductor structure includes a substrate, a first and a second transistor, a first and a second fuse, a contact structure and a dielectric layer. The substrate has a first and a second component area, and a fuse area. The first transistor and the second transistor are respectively located on the first component area and the second component area. The first fuse is electrically connected to the first transistor and includes a first fuse active area having a first portion and a second portion. The second fuse is electrically connected to the second transistor and includes a second fuse active area having a third portion and a fourth portion. The contact structure interconnects the second portion and the third portion, wherein the first portion and the fourth portion are located on opposite sides of the contact structure. The dielectric layer is located between the contact structure and the fuse area of ​​the substrate. By this, the semiconductor structure disclosed herein can reduce the characteristic size of the semiconductor structure, thereby increasing the integrated density.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure. Background Art

[0002] With the rapid development of the electronics industry, the development of integrated circuits (ICs) has achieved high performance and miniaturization. Technological advances in the materials and design of integrated circuits have produced generations of integrated circuits, each with smaller and more complex circuits than the previous generation.

[0003] As the number of electronic components on a single chip increases rapidly, three-dimensional (3D) integrated circuit layouts or stacked chip designs have been used for certain semiconductor devices to overcome the feature size and density limitations associated with two-dimensional (2D) layouts. However, the feature size and density of semiconductor structures still need to be improved. Summary of the invention

[0004] A technical aspect of the present disclosure is a semiconductor structure.

[0005] According to some embodiments of the present disclosure, a semiconductor structure includes a substrate, a first transistor, a second transistor, a first fuse, a second fuse, a contact structure, and a dielectric layer. The substrate has a first component region, a second component region, and a fuse region. The first transistor is located on the first component region of the substrate. The second transistor is located on the second component region of the substrate. The first fuse is electrically connected to the first transistor and is located in the fuse region, the first fuse includes a first fuse active region, and the first fuse active region has a first portion and a second portion. The second fuse is electrically connected to the second transistor and is located in the fuse region, the second fuse includes a second fuse active region, and the second fuse active region has a third portion and a fourth portion. The contact structure interconnects the second portion of the first fuse active region and the third portion of the second fuse active region, wherein the first portion of the first fuse active region and the fourth portion of the second fuse active region are located on opposite sides of the contact structure. The dielectric layer is located between the contact structure and the fuse region of the substrate.

[0006] In some embodiments, the first portion of the first fuse active region and the third portion of the second fuse active region are located on a same side of the contact structure.

[0007] In some embodiments, the first fuse partially overlaps the second fuse.

[0008] In some embodiments, a distance between the first fuse and the second fuse is in a range from about 0.5 microns to about 0.6 microns.

[0009] In some embodiments, the semiconductor structure further includes a first contact and a second contact, wherein the first contact is located on the first portion of the first fuse active region, and the second contact is located on the fourth portion of the second fuse active region.

[0010] In some embodiments, the first contact is not aligned with the second contact.

[0011] In some embodiments, the first contact is not aligned with the third portion of the second fuse active region.

[0012] In some embodiments, a distance between the first transistor and the first fuse is in a range from about 2 microns to about 3 microns.

[0013] In some embodiments, the dielectric layer is directly on the second portion of the first fuse active region and the third portion of the second fuse active region.

[0014] In some embodiments, the semiconductor structure further includes a conductive structure, and the conductive structure is located on the first transistor and the first fuse, so that the first fuse is electrically connected to the first transistor.

[0015] In some embodiments, the semiconductor structure further includes an isolation structure located in the substrate.

[0016] In some embodiments, the first transistor further includes source / drain regions and a gate structure located between the source / drain regions.

[0017] In some embodiments, the semiconductor structure further includes a gate transistor. The gate transistor is located between the gate structure and the first device region of the substrate.

[0018] In some embodiments, a top surface of the contact structure is higher than a top surface of the gate structure of the first transistor.

[0019] In some embodiments, the semiconductor structure further includes a contact, wherein the contact is located on the first device region of the substrate and adjacent to the gate structure.

[0020] According to the above embodiments of the present disclosure, since the contact structure interconnects the second portion of the first fuse active region and the third portion of the second fuse active region, the feature size of the semiconductor structure can be reduced, thereby increasing the integration density. In this way, the performance of the semiconductor structure can be improved.

[0021] It is to be understood that both the foregoing general description and the following detailed description are merely exemplary, and are intended to provide further explanation of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The aspects of the present disclosure can be understood from the following detailed description of the embodiments and the accompanying drawings.

[0023] Figure 1 A top view of a layout of a semiconductor structure according to some embodiments of the present disclosure is shown.

[0024] Figure 2 Draw Figure 1 A partial enlarged view of .

[0025] Figure 3 Draw along Figure 1 A cross-sectional view of the semiconductor structure along line 3-3.

[0026] Figure 4 Draw along Figure 1 A cross-sectional view of the semiconductor structure along line 4-4.

[0027] Figure 5 Draw along Figure 1 A cross-sectional view of the semiconductor structure along line 5-5. DETAILED DESCRIPTION

[0028] The following will disclose multiple embodiments of the present disclosure with drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. That is, in some embodiments of the present disclosure, these practical details are not necessary and therefore should not be used to limit the present disclosure. In addition, in order to simplify the drawings, some conventional structures and components will be illustrated in the drawings in a simple schematic manner. In addition, for the convenience of readers, the sizes of the components in the drawings are not drawn according to the actual scale.

[0029] As used in this disclosure, "around", "about", "approximately" or "substantially" generally means within 20%, or within 10%, or within 5% of a given value or range. The numerical values ​​given in this disclosure are approximate, meaning that if not explicitly stated, the term "around", "about", "approximately" or "substantially" can be inferred.

[0030] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "below," "above," "above," and the like may be used in some embodiments of the present disclosure to describe the relationship of one element or feature to another element(s) or feature(s) as described in the figures. Such spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the drawings. The element may be otherwise positioned (rotated 90 degrees or in other orientations) and such spatially relative descriptors used in some embodiments of the present disclosure interpreted accordingly.

[0031] Figure 1 A top view of the layout of the semiconductor structure 10 according to some embodiments of the present disclosure is shown, and Figure 2 Draw Figure 1 See also Figure 1 and Figure 2 The semiconductor structure 10 includes a substrate 100, a first transistor T1, a second transistor T2, a first fuse F1, a second fuse F2, a contact structure 150 and a dielectric layer 220 (hereinafter referred to as Figure 4 and Figure 5 Discussion). The substrate 100 has a first device region 102, a second device region 104, and a fuse region 106 between the first device region 102 and the second device region 104. The first transistor T1 is disposed on the first device region 102 of the substrate 100, and the second transistor T2 is disposed on the second device region 104 of the substrate 100. The first fuse F1 and the second fuse F2 are disposed in the fuse region 106 of the substrate 100. Each first fuse F1 is electrically connected to each first transistor T1, respectively. Each first fuse F1 includes a first fuse active region 110a in the fuse region 106. The first fuse active region 110a has a first portion 112 and a second portion 114. Each second fuse F2 is electrically connected to each second transistor T2, respectively. Each second fuse F2 includes a second fuse active region 110b in the fuse region 106. The second fuse active region 110b includes a third portion 118 and a fourth portion 120. The contact structure 150 interconnects the second portion 114 of the first fuse active region 110a of each first fuse F1 and the third portion 118 of the second fuse active region 110b of each second fuse F2. The first portion 112 of the first fuse active region 110a and the fourth portion 120 of the second fuse active region 110b are disposed on opposite sides of the contact structure 150. The dielectric layer 220 (see Figure 4 and Figure 5 ) is located between the contact structure 150 and the fuse region 106 of the substrate 100. Since the first fuse F1 and the second fuse F2 share the same contact structure 150 thereon, the area of ​​the fuse region 106 can be reduced and thus the feature size of the semiconductor structure 10 can be reduced, thereby increasing the integration density. In this way, the performance of the semiconductor structure 10 can be improved.

[0032] In some embodiments, the semiconductor structure 10 includes a first conductive structure 270a and a second conductive structure 270b. The first conductive structure 270a is located on the first transistor T1 and the first fuse F1, and the second conductive structure 270b is located on the second transistor T2 and the second fuse F2. The first fuse F1 is electrically connected to the first transistor T1 through the first conductive structure 270a extending from above the first device region 102 of the substrate 100 to above the fuse region 106 of the substrate 100, and the second fuse F2 is electrically connected to the second transistor T2 through the second conductive structure 270b extending from above the second device region 104 of the substrate 100 to above the fuse region 106 of the substrate 100. The first transistor T1 and the second transistor T2 are configured to read and write the first fuse F1 and the second fuse F2. It should be noted that when the first conductive structure 270a and the second conductive structure 270b are formed on the transistors (the first transistor T1 and the second transistor T2) and the fuses (the first fuse F1 and the second fuse F2), Figure 2 Draw Figure 1 The dotted line area R in FIG. 1 is a partial enlarged view, and for the sake of clarity, Figure 1 The first conductive structure 270a and the second conductive structure 270b are omitted.

[0033] In some embodiments, in the top view, the first fuses F1 and the second fuses F2 are alternately arranged along the Y-axis direction. The contact structure 150 is arranged along the Y-axis direction. The first portion 112 of the first fuse active region 110a of each first fuse F1 and the fourth portion 120 of the second fuse active region 110b of each second fuse F2 are located on opposite sides of the contact structure 150, while the first portion 112 of the first fuse active region 110a of each first fuse F1 and the third portion 118 of the second fuse active region 110b of each second fuse F2 are located on the same side of the contact structure 150 (e.g., on the negative direction side of the X-axis). Similarly, the first portion 112 of the first fuse active region 110a and the fourth portion 120 of the second fuse active region 110b are located on opposite sides of the contact structure 150, while the second portion 114 of the first fuse active region 110a and the fourth portion 120 of the second fuse active region 110b are located on the same side of the contact structure 150 (e.g., on the positive direction side of the X-axis). In some embodiments, each first fuse F1 partially overlaps with each second fuse F2. Specifically, in the Y-axis direction, a portion of the second portion 114 of the first fuse active region 110a of each first fuse F1 overlaps (or aligns) with a portion of the third portion 118 of the second fuse active region 110b of each second fuse F2, wherein the aforementioned portion of the second portion 114 and the aforementioned portion of the third portion 118 are covered by the contact structure 150.

[0034] In some embodiments, in the Y-axis direction, the distance D1 between each first fuse F1 and each second fuse F2 is in the range of about 0.5 micrometers (μm) to about 0.6 micrometers. If the distance D1 is less than about 0.5 micrometers, the space between the first fuse F1 and the second fuse F2 will not be sufficient to accommodate the contact; if the distance D1 is greater than about 0.6 micrometers, the area of ​​the fuse region 106 will increase. In some embodiments, the distance D2 between the first portion 112 of the first fuse active region 110a of each first fuse F1 and the third portion 118 of the second fuse active region 110b of each second fuse F2 in the X-axis direction is in the range of about 0.2 micrometers to about 0.3 micrometers. If the distance D2 is less than about 0.2 microns, the space above the first fuse F1 will not be sufficient to accommodate contacts (e.g., the first contact 160 and the second contact 170) thereon; if the distance D2 is greater than about 0.3 microns, the length of the first portion 112 of the first fuse active region 110a of each first fuse F1 will be too large, thereby increasing the resistance of the first fuse F1 and the area of ​​the fuse region 106.

[0035] In some embodiments, the first portion 112 of the first fuse active region 110a of each first fuse F1 is closer to the first transistor T1 than the third portion 118 of the second fuse active region 110b of each second fuse F2, and the fourth portion 120 of the second fuse active region 110b of each second fuse F2 is closer to the second transistor T2 than the second portion 114 of the first fuse active region 110a of each first fuse F1.

[0036] In some embodiments, the semiconductor structure 10 further includes a first contact 160 and a second contact 170. The first contact 160 is located on the first portion 112 of the first fuse active region 110a of each first fuse F1, and the second contact 170 is located on the fourth portion 120 of the second fuse active region 110b of each second fuse F2. The first contact 160 is not aligned with the second contact 170. In other words, the first contact 160 and the second contact 170 are located on opposite sides corresponding to the contact structure 150. The first contact 160 is not aligned with the third portion 118 of the second fuse active region 110b, and the second contact 170 is not aligned with the second portion 114 of the first fuse active region 110a. In other words, the first contact 160 does not overlap with the third portion 118 of the second fuse active region 110b, and the second contact 170 does not overlap with the second portion 114 of the first fuse active region 110a.

[0037] In some embodiments, the semiconductor structure 10 further includes a first dummy gate 180 and a second dummy gate 190. The first dummy gate 180 is located on the first device region 102 of the substrate 100, and the second dummy gate 190 is located on the second device region 104 of the substrate 100. In some embodiments, in the top view, each second transistor T2 is higher than each first transistor T1 by a distance D3, wherein the distance D3 is in a range of about 0.2 microns to about 0.3 microns (e.g., 0.25 microns). In some embodiments, the semiconductor structure 10 further includes a conductive structure 260, which is configured to program the first fuse F1 and the second fuse F2 by applying a voltage.

[0038] In some embodiments, in the X-axis direction, the semiconductor structure 10 has a first length in the range of about 5 microns to about 6 microns (e.g., 5.45 microns); in the Y-axis direction, the semiconductor structure 10 has a second length in the range of about 9 microns to about 10 microns (e.g., 9.64 microns).

[0039] Figure 3 Draw along Figure 1 A cross-sectional view of the semiconductor structure 10 taken along line 3-3 (the Y axis is the horizontal axis and the Z axis is the vertical axis), Figure 4 Draw along Figure 1 A cross-sectional view of the semiconductor structure 10 taken along line 4-4 (the Y axis is the horizontal axis and the Z axis is the vertical axis), and Figure 5 Draw along Figure 1 A cross-sectional view of the semiconductor structure 10 taken along line 5-5 (the X axis is the horizontal axis and the Z axis is the vertical axis). Figures 1 to 5 , the first device region 102, the second device region 104 and the fuse region 106 are adjacent to each other. In some embodiments, the substrate 100 includes silicon. In some other embodiments, the substrate 100 includes another element semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof.

[0040] In some embodiments, Figure 3As shown, source / drain regions 122, source / drain regions 124, and source / drain regions 126 are formed in substrate 100. The source / drain regions 122, source / drain regions 124, and source / drain regions 126 may be formed by doping a top portion of substrate 100 with an N-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), a combination thereof, or the like. Alternatively, the source / drain regions 122, source / drain regions 124, and source / drain regions 126 may be formed by doping a top portion of substrate 100 with a P-type dopant, such as boron (B), BF2, BF3, a combination thereof, or the like. In some embodiments, source / drain regions 122 and source / drain regions 124 are considered to be source / drain regions of one of the first transistors T1. For example, the source / drain region 122 is the source region of one of the first transistors T1 , the source / drain region 124 is the drain region of one of the first transistors T1 , and the source / drain region 126 is the source region of another of the first transistors T1 .

[0041] In some embodiments, Figure 1 , Figure 4 and Figure 5 As shown, the semiconductor structure 10 further includes an isolation structure 140 located in the substrate 100. The isolation structure 140 is formed to surround the first device region 102, the second device region 104, and the fuse region 106 for proper electrical isolation. In some embodiments, the isolation structure 140 is a shallow trench isolation (STI). The formation of the isolation structure 140 may include etching a trench in the substrate 100 and filling the trench with an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride). The filled trench may have a multi-layer structure, such as a thermal oxide liner layer and having silicon nitride filling the trench. In some embodiments, the isolation structure 140 is created using a process sequence such as growing a liner oxide, forming a low pressure chemical vapor deposition (LPCVD) nitride layer, patterning an STI opening using a photoresist and mask, etching a trench in the substrate 100, optionally growing a thermal oxide trench liner to improve the trench interface, filling the trench with a chemical vapor deposition (CVD) oxide, and using chemical mechanical planarization (CMP) to remove excess dielectric layer.

[0042] In some embodiments, the gate structure 200 is disposed on the first device region 102 and the second device region 104 of the substrate 100, and the contact structure 150 is disposed on the fuse region 106 of the substrate 100. Figure 1 and Figure 3As shown, the first transistor T1 includes a source / drain region 122, a source / drain region 124, and a gate structure 200 located between the source / drain region 122 and the source / drain region 124. In some embodiments, a width W1 of each gate structure 200 is greater than a width W2 of the contact structure 150.

[0043] In some embodiments, the gate structure 200 and the contact structure 150 are formed simultaneously in the same processing process. In some embodiments, the gate structure 200 and the contact structure 150 include the same material, such as metal, semiconductor material (such as polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe)), or other suitable materials. In some embodiments, the gate structure 200 and the contact structure 150 respectively include a work function metal layer, a capping layer, a filling layer and / or other suitable layers desired in the metal gate stack. In some embodiments, the filling layer in the gate structure 200 and / or the contact structure 150 may include tungsten (W). The filling layer can be deposited by ALD, PVD, CVD, or other suitable processes.

[0044] In some embodiments, the semiconductor structure 10 further includes a gate dielectric layer 210 located between each gate structure 200 and the first device region 102 of the substrate 100. The gate dielectric layer 210 has a portion located in the first device region 102 of the substrate 100 and a remaining portion located above the first device region 102 of the substrate 100. In some embodiments, the dielectric layer 220 has a portion located in the fuse region 106 of the substrate 100 and a remaining portion located above the fuse region 106 of the substrate 100. Specifically, as Figure 1 and Figure 4 As shown, the dielectric layer 220 is disposed between the contact structure 150 and the third portion 118 of the second fuse active region 110b of the second fuse F2, and between the contact structure 150 and the second portion 114 of the first fuse active region 110a of the first fuse F1. The dielectric layer 220 is directly located on the second portion 114 of the first fuse active region 110a and the third portion 118 of the second fuse active region 110b. Figure 1 and Figure 5 As shown, the dielectric layer 220 is disposed between the contact structure 150 and the second portion 114 of the first fuse active region 110 a of the first fuse F1 .

[0045] In some embodiments, the gate dielectric layer 210 and the dielectric layer 220 are formed simultaneously in the same process. In some embodiments, the gate dielectric layer 210 and the dielectric layer 220 include the same material, such as silicon dioxide, silicon nitride, a high-k dielectric material, or other suitable materials. In various examples, the gate dielectric layer 210 and the dielectric layer 220 are deposited by a thermal oxidation process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a sub-atmospheric pressure chemical vapor deposition (SACVD) process, a flowable chemical vapor deposition process (flowable CVD), a physical vapor deposition (PVD) process, or other suitable processes.

[0046] like Figure 1 and Figure 3 As shown, the contact 230, the contact 240 and the contact 250 are disposed on the first device region 102 of the substrate 100 and adjacent to the gate structure 200. Specifically, the contact 230 is disposed on the source / drain region 122, the contact 240 is disposed on the source / drain region 124, and the contact 250 is disposed on the source / drain region 126. The contact 240 is electrically connected to the first conductive structure 270a. Figure 1 and Figure 5 As shown, the first contact 160 is disposed on the fuse region 106 of the substrate 100 and is adjacent to the contact structure 150. Specifically, the first contact 160 is located on the first portion 112 of the first fuse active region 110a, and the contact structure 150 is located on the second portion 114 of the first fuse active region 110a. In some embodiments, a top surface 161 of the first contact 160 is higher than a top surface 151 of the contact structure 150.

[0047] In some embodiments, Figure 1 and Figure 5 As shown, the contact structure 150 has a higher potential than the first contact 160, so that current flows from the contact structure 150 to the first contact 160. In other words, current flows from the second portion 114 of the first fuse active region 110a to the first portion 112 of the first fuse active region 110a.

[0048] In some embodiments, Figure 1 and Figure 5 As shown, the contacts 230 to 250 and the first contact 160 are formed simultaneously in the same process. The contacts 230 to 250 and the first contact 160 may include the same material, such as copper (Cu), iron (Fe), aluminum (Al), or other suitable conductive materials. The contacts 230 to 250 and the first contact 160 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0049] In some embodiments, the first conductive structure 270a is disposed on the contact 240 and the first contact 160. The first conductive structure 270a is electrically connected to the contact 240 located above the first device region 102 of the substrate 100 and the first contact 160 located above the fuse region 106 of the substrate 100, so that the first fuse F1 is electrically connected to the first transistor T1 through the first contact 160, the first conductive structure 270a and the contact 240. The first conductive structure 270a can be made of polysilicon, metal, or other suitable conductive materials.

[0050] In some embodiments, Figure 1 , Figure 2 and Figure 5 As shown, a large amount of current may cause the dielectric layer 220 of the first fuse F1 to be blown, for example, by electromigration of the conductive material caused by the large current flowing through the first fuse F1. The first fuse active region 110a can be considered as a first electrode of the first fuse F1, and the contact structure 150 on the first fuse active region 110a can be considered as a second electrode of the first fuse F1. In some embodiments, a breakdown may occur on the dielectric layer 220 between the first electrode (the first fuse active region 110a) and the second electrode (the contact structure 150 on the second portion 114 of the first fuse active region 110a) and form a short circuit.

[0051] In some embodiments, the semiconductor structure 10 further includes an interlayer dielectric (ILD) layer 280 located on the substrate 100. The interlayer dielectric layer 280 can be formed above the substrate 100 to a horizontal position above the top surface 201 of each gate structure 200 and the top surface 151 of the contact structure 150, so that the gate structure 200 and the contact structure 150 are embedded in the interlayer dielectric layer 280. The interlayer dielectric layer 280 can be formed by chemical vapor deposition (CVD), high-density plasma chemical vapor deposition, spin coating, sputtering, or other suitable methods. In some embodiments, the interlayer dielectric layer 280 includes silicon oxide, phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), fluorinated silicate glass (FSG), or other suitable materials. In some other embodiments, the interlayer dielectric layer 280 may include silicon oxynitride, silicon nitride, a compound including Si, O, C and / or H (e.g., silicon oxide, SiCOH and SiOC), a low-k dielectric material (a dielectric material having a dielectric constant less than about 3.9, which is the dielectric constant of thermal silicon oxide), or an organic material (e.g., a polymer). In some embodiments, a planarization process is performed to remove a portion of the interlayer dielectric layer 280 so that the top surface of the interlayer dielectric layer 280 is coplanar with the top surfaces of the first conductive structure 270a and the second conductive structure 270b. The planarization process may be a chemical mechanical planarization (CMP) process.

[0052] Although the present disclosure has disclosed the embodiments in detail above, other embodiments are also possible and are not intended to limit the present disclosure. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments of the present disclosure.

[0053] Those skilled in the art may make various changes or substitutions without departing from the spirit and scope of the present disclosure, and all such changes or substitutions should be included in the protection scope of the claims attached to the present disclosure.

[0054]

Explanation of symbols

[0055] 10: Semiconductor structure

[0056] 100:Substrate

[0057] 102: First component area

[0058] 104: Second component area

[0059] 106: Fuse area

[0060] 110a: first fuse active region

[0061] 110b: second fuse active region

[0062] 112: Part 1

[0063] 114: Part 2

[0064] 118: Part 3

[0065] 120: Part 4

[0066] 122: Source / drain region

[0067] 124: Source / drain region

[0068] 126: Source / drain region

[0069] 140: Isolation Structure

[0070] 150: Contact structure

[0071] 151: Top

[0072] 160: First Contact

[0073] 161: Top

[0074] 170: Second Contact

[0075] 180: first dummy gate

[0076] 190: second dummy gate

[0077] 200: Gate structure

[0078] 201: Top

[0079] 210: Gate dielectric layer

[0080] 220: Dielectric layer

[0081] 230: Contact

[0082] 240: Contact

[0083] 250: Contact

[0084] 260: Conductive structure

[0085] 270a: first conductive structure

[0086] 270b: second conductive structure

[0087] 280: Interlayer dielectric layer

[0088] D1: Distance

[0089] D2: Distance

[0090] D3: Distance

[0091] F1: First fuse

[0092] F2: Second fuse

[0093] R: Dashed area

[0094] T1: First transistor

[0095] T2: Second transistor

[0096] W1: Width

[0097] W2: Width

[0098] X: Axis

[0099] Y: Axis

[0100] Z: Axis

[0101] 3-3: Line

[0102] 4-4: Line

[0103] 5-5: line.

Claims

1. A semiconductor structure, characterized in that: Include: A substrate having a first element region, a second element region and a fuse region; A first transistor is located on the first device region of the substrate; A second transistor is located on the second device region of the substrate; A first fuse electrically connected to the first transistor and located in the fuse region, the first fuse comprising a first fuse active region having a first portion and a second portion; A second fuse electrically connected to the second transistor and located in the fuse region, the second fuse comprising a second fuse active region having a third portion and a fourth portion; a contact structure interconnecting the second portion of the first fuse active region and the third portion of the second fuse active region, wherein the first portion of the first fuse active region and the fourth portion of the second fuse active region are located on opposite sides of the contact structure; as well as A dielectric layer is located between the contact structure and the fuse region of the substrate. 2 . The semiconductor structure of claim 1 , wherein the first portion of the first fuse active region and the third portion of the second fuse active region are located on a same side of the contact structure. The semiconductor structure according to claim 1 , wherein the first fuse partially overlaps the second fuse. 4 . The semiconductor structure of claim 1 , wherein a distance between the first fuse and the second fuse is in a range of about 0.5 micrometers to about 0.6 micrometers.

5. The semiconductor structure according to claim 1, further comprising: a first contact located on the first portion of the first fuse active region; and The second contact is located on the fourth portion of the second fuse active region. The semiconductor structure of claim 5 , wherein the first contact is not aligned with the second contact. 7 . The semiconductor structure of claim 5 , wherein the first contact is not aligned with the third portion of the second fuse active region. 8 . The semiconductor structure of claim 1 , wherein a distance between the first transistor and the first fuse is in a range from about 2 microns to about 3 microns. 9 . The semiconductor structure of claim 1 , wherein the dielectric layer is directly located on the second portion of the first fuse active region and the third portion of the second fuse active region.

10. The semiconductor structure according to claim 1, further comprising: The conductive structure is located on the first transistor and the first fuse, so that the first fuse is electrically connected to the first transistor.

11. The semiconductor structure according to claim 1, further comprising: The isolation structure is located in the substrate.

12. The semiconductor structure according to claim 1, wherein the first transistor further comprises: source / drain regions; and A gate structure is located between the source / drain regions.

13. The semiconductor structure according to claim 12, further comprising: The gate transistor is located between the gate structure and the first device region of the substrate. 14 . The semiconductor structure according to claim 12 , wherein a top surface of the contact structure is higher than a top surface of the gate structure of the first transistor.

15. The semiconductor structure of claim 12, further comprising: A contact is located on the first device region of the substrate and adjacent to the gate structure.

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