A low radio frequency dissipation N-face HEMT device and its preparation method

Abstract

The present invention discloses an N-face HEMT device with low radio frequency dissipation, comprising: an epitaxial substrate, which comprises a substrate, a GaN buffer layer, an Al x Ga 1‑x N graded barrier layer, AlN insertion layer, AlGaN barrier layer and GaN channel layer; passivation layer, arranged above the GaN channel layer; source electrode and drain electrode, respectively arranged above the AlGaN barrier layer at both ends of the epitaxial substrate; gate electrode, arranged on the passivation layer; wherein, Al x Ga 1‑x The interface between the N-graded barrier layer and the GaN buffer layer is δ-doped. The present invention performs δ-doping in the graded barrier layer near the NPI, increasing the number of positively charged Si ions after ionization at the NPI and further compensating for the polarized negative charge. Furthermore, an AlN insertion layer is introduced between the graded barrier layer and the barrier layer, which not only moves the valence band away from the Fermi level but also weakens the polarization electric field in the barrier layer and the graded barrier layer, thereby reducing the speed at which the valence band approaches the Fermi level, achieving a distance between the valence band and improving radio frequency dissipation at the NPI.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronics technology, and in particular relates to an N-face HEMT device with low radio frequency dissipation and a preparation method thereof. Background Art

[0002] The high breakdown voltage and high-density two-dimensional electron gas of gallium nitride (GaN) combined with the high electron mobility and high transconductance of HEMT devices make GaN HEMTs highly competitive in the high-frequency, high-power segment. However, with the continuous advancement of technology, the available spectrum resources are becoming increasingly limited, placing higher demands on the application environment of RF electronic devices.

[0003] In traditional Ga-face GaN HEMT high-frequency devices, reducing gate length is one of the primary means of achieving higher frequency performance. However, as gate length is further reduced, the reduced aspect ratio of the device means that the short channel effect can no longer be ignored, seriously deteriorating the device's performance. In Ga-face HEMT devices, the device's longitudinal dimension is primarily approximate to the thickness of the barrier layer, while in N-face HEMT devices, the longitudinal dimension is primarily the channel layer thickness. Theoretically, the 2DEG in HEMT devices is primarily distributed within a few nanometers, resulting in smaller longitudinal dimensions for N-face devices. This facilitates the fabrication of devices with smaller gate lengths, resulting in better frequency performance.

[0004] In addition, N-face HEMT devices have advantages such as a natural back-barrier structure, greater activity, and lower ohmic contact resistance. The back-barrier structure can enhance the confinement of the two-dimensional electron gas, improving the short-channel effect of the device. It can also enhance the device's gate control capability and reduce buffer layer leakage, resulting in better turn-off and breakdown characteristics. The higher activity of the N-face gives it a greater advantage over Ga-face devices in sensor applications. It also facilitates the secondary epitaxy of some materials, facilitating the production of lower ohmic contact resistance. For example, the N-face exhibits stronger indium adsorption capacity and facilitates the growth of InN. Through the epitaxial composition gradient of the InGaN structure, a gapless contact can be formed with GaN, resulting in an ohmic contact of up to 0.027Ω·mm.

[0005] However, N-face HEMT devices also have some problems that do not exist in Ga-face devices. Among them, the main problem affecting the high-frequency performance of the device is the donor-like trap at the NPI (negatively polarized interface), whose trap energy level is recorded as E T For Al 0.3 Ga 0.7 For N / GaN, E T The distance from the valence band top (E V) is about 60meV, such as Figure 2 As shown in Figure 2, donor-like traps at the NPI (Non-Pin Electron Pipe) in N-face HEMTs are a major source of 2D electron gas, slightly different from the source of 2D electron gas in Ga-face HEMTs. When the device is subjected to different voltage biases, the charging and discharging of these traps causes changes in the 2D electron concentration. Consequently, N-face HEMTs typically exhibit more severe current collapse in RF environments. Therefore, improvements at the NPI are crucial for RF N-face HEMTs.

[0006] Currently, the mainstream solution to address the severe RF dissipation problem of the NPI in N-face HEMT devices is to dope Si in the barrier layer near the buffer layer. The positively charged Si ions after ionization increase the potential at the barrier / buffer layer interface, shifting the valence band at the NPI away from the Fermi level. This reduces the difference in electron concentration caused by the charging and discharging of donor-like traps under different voltage stresses. A further solution to this problem is to use a graded barrier in the barrier layer design to improve the ionization efficiency of the doped silicon, ensuring that there are sufficient positively charged ions near the NPI to compensate for the polarized negative charge.

[0007] However, the use of graded barrier layers means that the band gap gradually decreases, and there will be a band step difference in the valence band, such as Figure 3 This means that the valence band will gradually approach the Fermi level, which to some extent worsens the RF dissipation problem of N-face HEMT. Summary of the Invention

[0008] To address the problem of severe RF dissipation caused by the donor-like energy level near the NPI in existing N-face HEMT devices being close to the Fermi level, the present invention provides an N-face HEMT device with low RF dissipation and a method for preparing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0009] In a first aspect, the present invention provides an N-face HEMT device with low radio frequency dissipation, comprising:

[0010] Epitaxial substrate, which includes substrate, GaN buffer layer, Al x Ga 1-x N graded barrier layer, AlN insertion layer, AlGaN barrier layer and GaN channel layer;

[0011] a passivation layer, disposed above the GaN channel layer;

[0012] A source electrode and a drain electrode are respectively arranged above the AlGaN barrier layers at both ends of the epitaxial substrate;

[0013] a gate electrode, disposed on the passivation layer;

[0014] Wherein, the Al x Ga 1-x The interface between the N graded barrier layer and the GaN buffer layer is delta-doped.

[0015] In one embodiment of the present invention, the Al x Ga 1-x The Al composition X in the N graded barrier layer changes gradually from 0% to 30% from bottom to top.

[0016] In one embodiment of the present invention, the δ-doping is Si doping with a doping concentration of 1.2×10 13 ~2.5×10 13 cm -2 .

[0017] In one embodiment of the present invention, the thickness of the AlN insertion layer is 1-5 nm.

[0018] In one embodiment of the present invention, the thickness of the substrate is 400 μm to 500 μm; the thickness of the GaN buffer layer is 1.3 μm to 2 μm; the Al x Ga 1-x The thickness of the N graded barrier layer is 20-30 nm; the thickness of the AlGaN barrier layer is 10-30 nm; and the thickness of the GaN channel layer is 10-20 nm.

[0019] In one embodiment of the present invention, the substrate is made of sapphire, Si or SiC.

[0020] In a second aspect, the present invention provides a method for preparing an N-face HEMT device with low radio frequency dissipation, comprising:

[0021] Obtain an epitaxial substrate; wherein the epitaxial substrate comprises a substrate, a GaN buffer layer, an Al x Ga 1-x N graded barrier layer, AlN insertion layer, AlGaN barrier layer and GaN channel layer, and the Al x Ga 1-x The interface between the N graded barrier layer and the GaN buffer layer is δ-doped;

[0022] Fabricating a source electrode and a drain electrode on the GaN channel layer;

[0023] growing a passivation layer on the GaN channel layer;

[0024] Photolithography a gate electrode region on the passivation layer and fabricating a gate electrode;

[0025] A metal interconnection layer is prepared to lead the source electrode, the drain electrode and the gate electrode to the surface of the device to complete the device fabrication.

[0026] In one embodiment of the present invention, obtaining the epitaxial substrate includes:

[0027] From bottom to top, the substrate, GaN buffer layer, Al x Ga 1-x N graded barrier layer, AlN insertion layer, AlGaN barrier layer and GaN channel layer integrated epitaxial substrate; or sequentially grow GaN buffer layer, AlN x Ga 1- x N graded barrier layer, AlN insertion layer, AlGaN barrier layer and GaN channel layer are formed to prepare the epitaxial substrate.

[0028] Beneficial effects of the present invention:

[0029] 1. The low RF dissipation N-face HEMT device provided by the present invention is on the one hand x Ga 1-x δ-doping is performed at the interface between the N-graded barrier layer and the GaN buffer layer, which increases the number of positively charged Si ions after ionization at the NPI, further compensating for the polarized negative charge. On the other hand, an AlN insertion layer is introduced between the graded barrier layer and the barrier layer. This not only makes the valence band move away from the Fermi level due to the band gap caused by its wider bandgap, but also weakens the polarization electric field in the barrier layer and the graded barrier layer, thereby reducing the speed at which the valence band approaches the Fermi level, achieving the valence band's distance, and thus improving the RF dissipation at the NPI.

[0030] 2. The low RF dissipation N-face HEMT device provided by the present invention helps to reduce the serious lattice mismatch problem caused by the different lattice constants of the AlN material and the GaN buffer layer by introducing a barrier layer structure with a graded composition. By placing the insertion layer between the graded barrier layer and the barrier layer, the serious lattice mismatch problem between the AlN insertion layer and the GaN channel layer is also avoided.

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a schematic diagram of the energy band of an existing N-side HEMT device;

[0033] Figure 2 yes Figure 1 A local magnified view of the NPI interface;

[0034] Figure 3 This is a schematic diagram of the effect of the graded barrier layer on the energy band in the prior art;

[0035] Figure 4 1 is a schematic structural diagram of an N-face HEMT device with low radio frequency dissipation provided by an embodiment of the present invention;

[0036] Figure 5 Schematic diagram of the effect of the AlN insertion layer structure on polarization provided by an embodiment of the present invention;

[0037] Figure 6 Schematic diagram of the effect of the AlN insertion layer structure on the energy band provided by an embodiment of the present invention;

[0038] Figure 7 It is a flow chart of a method for preparing an N-face HEMT device with low RF dissipation provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0040] Example 1

[0041] See Figure 4 , Figure 4 1 is a schematic structural diagram of an N-face HEMT device with low radio frequency dissipation provided by an embodiment of the present invention, which includes:

[0042] The epitaxial substrate includes, from bottom to top, a substrate 1, a GaN buffer layer 2, an Al x Ga 1-x N graded barrier layer 3, AlN insertion layer 4, AlGaN barrier layer 5 and GaN channel layer 6;

[0043] a passivation layer 7, disposed above the GaN channel layer 6;

[0044] The source electrode 8 and the drain electrode 9 are respectively arranged above the AlGaN barrier layer 5 at both ends of the epitaxial substrate;

[0045] A gate electrode 10 is provided on the passivation layer 7;

[0046] Among them, in Al x Ga 1-x The interface between the N graded barrier layer 3 and the GaN buffer layer 2 is delta-doped.

[0047] Optionally, as an implementation method, Al x Ga 1-x The Al composition X in the N graded barrier layer 3 changes gradually from 0% to 30% from bottom to top.

[0048] In this embodiment, δ-doping adopts Si doping, and its doping concentration is 1.2×10 13~2.5×10 13 cm -2 .

[0049] It is understandable that δ-doping is an ideal distribution with a peak concentration at only one interface and no vertical dimension. However, in practice, due to process limitations, it is actually a bulk doping and a bulk distribution.

[0050] Specifically, the doping can be achieved by using a molecular beam epitaxy (MBE) device to grow to a distance from Al x Ga 1-x When the interface distance between the N graded barrier layer 3 and the GaN buffer layer 2 is 4-5 nm, the Si source furnace baffle is opened and 3×10 19 ~5×10 19 cm -3 The concentration is doped, and then the volume distribution is multiplied by the longitudinal size to eliminate the longitudinal size, thereby converting the volume distribution into surface density.

[0051] The device provided in this embodiment, through its graded barrier layer structure, not only improves the ionization efficiency of Si δ-doping but also ensures that the ionized electrons are widely distributed throughout the barrier layer. Furthermore, δ-doping concentrates the ionized Si ions at the NPI, further compensating for the polarized negative charge and moving the valence band away from the Fermi level.

[0052] Furthermore, the thickness of the AlN insertion layer 4 is 1 to 5 nm.

[0053] This embodiment uses AlN as the insertion layer material. On the one hand, thanks to the wider band gap of the AlN insertion layer, there is a band gap at the barrier layer / AlN interface, which can pull the valence band away from the Fermi level and reduce the charge and discharge effect of the donor-like trap. On the other hand, please refer to Figure 5 , Figure 5 Schematic diagram of the effect of the AlN insertion layer structure on polarization provided by the embodiment of the present invention. Figure 5 As shown in region 2, the introduction of AlN material will cause the barrier layer material to have a piezoelectric polarization opposite to the spontaneous polarization, which weakens the polarization strength in the barrier layer. This is also an effect that the AlN insertion layer usually does not have between the barrier layer and the channel layer in the traditional device structure. In addition, at the interface between region 3 and region 4, the polarization charge caused by the strong polarization effect of the AlN material will compensate for the polarization charge in region 4, thereby weakening the polarization electric field in region 4. The joint weakening of the polarization electric field in region 2 and region 4 causes the valence band of the barrier layer to slowly approach the Fermi level, improving the RF dissipation at the NPI, as shown in Figure 2. Figure 6 shown.

[0054] In addition, the introduction of a graded component structure helps to reduce the serious lattice mismatch problem caused by the different lattice constants of the AlN material and the GaN buffer layer, and placing the insertion layer between the graded barrier layer and the barrier layer improves the serious lattice mismatch problem between the AlN insertion layer and the GaN channel layer.

[0055] Furthermore, in this embodiment, the thickness of the substrate 1 is 400 μm to 500 μm; the thickness of the GaN buffer layer 2 is 1.3 μm to 2 μm; and the thickness of the Al x Ga 1-x The thickness of the N graded barrier layer 3 is 20-30 nm; the thickness of the AlGaN barrier layer 5 is 10-30 nm; and the thickness of the GaN channel layer 6 is 10-20 nm.

[0056] Optionally, as an implementation method, the material of the substrate 1 is sapphire, Si, or SiC, and the AlGaN barrier layer 5 is Al 0.3 Ga 0.7 N preparation.

[0057] In this embodiment, the source electrode and the drain electrode may adopt a metal stack structure consisting of four metal layers of Ti, Al, Ni and Au in order from bottom to top.

[0058] The gate electrode adopts a T-shaped gate structure, and the gate metal can adopt a metal stack structure composed of two layers of Ni and Au metal in sequence from bottom to top.

[0059] The low RF dissipation N-face HEMT device provided by the present invention is based on Al x Ga 1-x δ-doping is performed at the interface between the N graded barrier layer and the GaN buffer layer, which increases the number of positively charged Si ions after ionization at the NPI and further compensates for the polarized negative charge. On the other hand, an AlN insertion layer is introduced between the graded barrier layer and the barrier layer, which not only makes the valence band move away from the Fermi level by virtue of the band gap difference caused by its wider bandgap, but also weakens the polarization electric field in the barrier layer and the graded barrier layer, thereby reducing the speed at which the valence band approaches the Fermi level and realizing the distance of the valence band, thereby improving the serious problem of RF dissipation at the NPI.

[0060] Example 2

[0061] Based on the above embodiment 1 and the same inventive concept, this embodiment provides a method for preparing an N-face HEMT device with low RF dissipation. Figure 7 , Figure 7 This is a flow chart of a method for preparing an N-face HEMT device with low RF dissipation provided by an embodiment of the present invention, which specifically includes:

[0062] S1: Obtain an epitaxial substrate; wherein the epitaxial substrate includes a substrate, a GaN buffer layer, an Al x Ga 1-x N graded barrier layer, AlN insertion layer, AlGaN barrier layer and GaN channel layer; and in the Al x Ga 1-x The interface between the N graded barrier layer and the GaN buffer layer is δ-doped;

[0063] Optionally, as an implementation method, the epitaxial substrate in step 1 can be directly obtained from bottom to top and includes substrate, GaN buffer layer, Al x Ga 1-x An integrated epitaxial substrate of an N graded barrier layer, an AlN insertion layer, an AlGaN barrier layer and a GaN channel layer.

[0064] Alternatively, as another implementation method, the epitaxial substrate in step 1 can also be prepared by yourself. First, a substrate of a certain material is selected, such as sapphire, Si or SiC material, and then a GaN buffer layer, an Al2O3 layer and a GaN layer are grown on the selected substrate in sequence using the MBE process. x Ga 1-x N graded barrier layer, AlN insertion layer, AlGaN barrier layer and GaN channel layer are formed to prepare an epitaxial substrate.

[0065] In this embodiment, δ-doping can be achieved by Si doping. Specifically, the Si doping can be achieved by using MBE equipment to grow to a distance from Al. x Ga 1-x This is achieved by opening the Si source furnace baffle when the interface between the N graded composition barrier layer and the GaN buffer layer is a few nanometers, and performing high-concentration doping.

[0066] S2: Fabricate source and drain electrodes on the GaN channel layer.

[0067] Specifically, an ohmic contact region is photoetched on a GaN channel layer of an epitaxial substrate, and then a source electrode and a drain electrode are fabricated.

[0068] S3: growing a passivation layer on the GaN channel layer.

[0069] First, an isolation region of the active region is photoetched on the GaN channel layer of the epitaxial substrate, and Cl-based etching is performed using an inductively coupled plasma (ICP) device to form a mesa isolation.

[0070] Then, a SiN passivation layer is formed by plasma enhanced chemical vapor deposition (PECVD).

[0071] S4: Photolithography is performed on the passivation layer to form a gate electrode region and to fabricate a gate electrode.

[0072] First, a gate groove grss region is photolithographically formed on the passivation layer.

[0073] Then, an ICP device is used to perform F-based etching on the SiN passivation layer to form a gate groove.

[0074] Next, a gate electrode region is photoetched on the passivation layer, and the gate electrode is manufactured using an electron beam evaporation process. After this step is completed, the gate electrode has a T-type gate structure.

[0075] Finally, the source and drain opening regions are photoetched on the passivation layer, and F-based etching is performed using an ICP device to remove the passivation layer 7 above the source and drain electrodes.

[0076] S5: Prepare a metal interconnect layer to lead the source electrode, drain electrode and gate electrode to the device surface to complete the device fabrication.

[0077] Specifically, metal interconnection areas are photolithographically formed on the passivation layer and the gate electrode, and an electron beam evaporation process is used to form a metal interconnection layer. The metal interconnection layer is a metal stack structure consisting of two layers of Ti and Au from bottom to top to lead out the electrode.

[0078] At this point, the preparation of N-side HEMT devices with low RF dissipation has been completed.

[0079] The low RF dissipation N-face HEMT device prepared in this embodiment has the advantages of x Ga 1-x δ-doping is performed at the interface between the N graded barrier layer and the GaN buffer layer, which increases the number of positively charged Si ions after ionization at the NPI and further compensates for the polarized negative charge. On the other hand, an AlN insertion layer is introduced between the graded barrier layer and the barrier layer, which not only makes the valence band move away from the Fermi level by virtue of the band gap difference caused by its wider bandgap, but also weakens the polarization electric field in the barrier layer and the graded barrier layer, thereby reducing the speed at which the valence band approaches the Fermi level, realizing the distance of the valence band, and thus improving the RF dissipation at the NPI.

[0080] Example 3

[0081] The following is a sapphire substrate with a channel layer thickness of 20nm. 0.3 Ga 0.7 The thickness of the N barrier layer is 10nm, the thickness of the AlN insertion layer is 2nm, and the thickness of the Al x Ga 1-x Taking an N-face HEMT device with an N-graded barrier layer having a thickness of 20 nm and a composition gradually changing from 0% to 30% as an example, the preparation process of the present invention is described in detail.

[0082] Step 1: Obtain an epitaxial substrate.

[0083] The epitaxial substrate includes, from bottom to top, a sapphire substrate 1, a GaN buffer layer 2, an Al x Ga 1-x N (x: 0% to 30%) graded barrier layer 3, AlN insertion layer 4, Al 0.3 Ga 0.7 N barrier layer 5 and GaN channel layer 6. x Ga 1-x The interface between the N graded barrier layer and the GaN buffer layer was doped with Siδ-, with a doping concentration of 2×10 13 cm -2 .

[0084] Step 2: Form a source electrode 8 and a drain electrode 9 on the GaN channel layer 6 .

[0085] 21) Photolithography of source and drain electrode regions on the GaN channel layer 6:

[0086] 21a) Place the epitaxial substrate on a hot plate at 200° C. and bake for 5 minutes;

[0087] 21b) applying and spinning a stripping adhesive on the GaN channel layer 6 to a thickness of 0.35 μm, and baking the sample on a hot plate at 200° C. for 5 minutes;

[0088] 21c) coating and spinning photoresist on the stripping adhesive to a thickness of 0.77 μm, and baking the sample on a hot plate at 90° C. for 1 minute;

[0089] 21d) The sample after the coating and stripping is placed in a photolithography machine to expose the coated surface, and the exposed sample is placed in a developer to remove the photoresist and stripping glue, and then rinsed with ultrapure water and blown with nitrogen to form the source electrode region and the drain electrode region.

[0090] 22) Evaporating the source electrode 8 and the drain electrode 9 on the GaN channel layer 6 in the source electrode region and the drain electrode region and the photoresist outside the source electrode region and the drain electrode region:

[0091] 22a) placing the sample with the active electrode and drain electrode photolithography patterns into a plasma stripper for base film treatment for 5 minutes;

[0092] 22b) Place the sample in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 - 6After Torr, ohmic metal is evaporated on the GaN channel layer 6 in the source electrode region and the drain electrode region and on the photoresist outside the source electrode region and the drain electrode region to form the source electrode 8 and the drain electrode 9. The ohmic metal is a metal stack structure composed of four metal layers of Ti, Al, Ni and Au from bottom to top;

[0093] 22c) The sample after ohmic metal evaporation is stripped to remove the ohmic metal, photoresist and stripping glue outside the source electrode 8 and the drain electrode 9, and then the sample is rinsed with ultrapure water and blown dry with nitrogen.

[0094] 23) The sample after ohmic metal evaporation and stripping is placed in a rapid thermal annealing furnace for annealing treatment, so that the ohmic metal of the source electrode 8 and the drain electrode 9 sinks into the AlGaN barrier layer 5, thereby forming an ohmic contact between the ohmic metal and the heterojunction channel. The annealing process conditions are: annealing atmosphere is N2, annealing temperature is 860°C, and annealing time is 30s.

[0095] Step 3: Use ICP equipment to perform Cl-based etching on the active area to form mesa isolation.

[0096] 31) Photolithography of mesa isolation regions on the GaN channel layer 6:

[0097] 31a) Bake the sample on a hot plate at 200°C for 5 minutes;

[0098] 31b) applying and spinning photoresist at a spinning speed of 3500 rpm, and baking the sample on a hot plate at 90° C. for 1 minute;

[0099] 31c) Place the sample in a photolithography machine to expose the photoresist in the passive area, then place the exposed sample in a developer to remove the photoresist in the passive area, and rinse with ultrapure water and blow dry with nitrogen.

[0100] 32) Etching is performed on the GaN channel layer 6 to form mesa isolation:

[0101] 32a) Using an ICP device, the barrier layer 5 in the passive region is etched away until part of the buffer layer is formed to form a mesa isolation in the active region, wherein the etching depth is 50 nm to 120 nm;

[0102] 32b) The sample is sequentially placed in an acetone solution, a stripping solution, an acetone solution, and an isopropanol solution for cleaning to remove the photoresist outside the electrically isolated area. Finally, the sample is rinsed with ultrapure water and blown dry with nitrogen gas.

[0103] Step 4: growing a SiN passivation layer 7 on the GaN channel layer 6 by plasma enhanced chemical vapor deposition (PECVD).

[0104] Specifically, the sample was placed in a PECVD device to grow SiN with a thickness of 60 nm. The growth process conditions were: NH3 and SiH4 were used as reaction gases, the substrate temperature was 250°C, the reaction chamber pressure was 600mTorr, and the RF power was 22W.

[0105] Step 5: Use ICP equipment to perform gate groove grss etching.

[0106] 51) Photolithography of the gate groove region on the SiN passivation layer 7:

[0107] 51a) Bake the sample on a hot plate at 200°C for 5 minutes;

[0108] 51b) applying and spinning photoresist at a spinning speed of 3500 rpm, and baking the sample on a hot plate at 90° C. for 1 minute;

[0109] 51c) Place the sample in a photolithography machine to expose the gate groove area, then place the exposed sample in a developer to remove the photoresist in the gate groove area, and rinse with ultrapure water and blow dry with nitrogen.

[0110] 52) Perform gate trench etching on the SiN passivation layer 7:

[0111] 52a) using an ICP device to etch away the passivation layer 7 in the gate groove region;

[0112] 52b) The sample is sequentially placed in an acetone solution, a stripping solution, an acetone solution, and an isopropyl alcohol solution for cleaning to remove the photoresist outside the gate groove area. Finally, the sample is rinsed with ultrapure water and blown dry with nitrogen gas.

[0113] Step 6: Photolithography a gate electrode region on the SiN passivation layer 7 and fabricate the gate electrode 10 using an electron beam evaporation process.

[0114] 61) Photolithography of the gate electrode region on the SiN passivation layer 7:

[0115] 61a) Place the gate trench etched sample on a hot plate at 200° C. and bake for 5 minutes;

[0116] 61b) applying and spinning a stripping adhesive to the SiN passivation layer 7 to a thickness of 0.5 μm, and baking the sample on a hot plate at 200° C. for 5 minutes;

[0117] 61c) coating and spinning photoresist on the stripping adhesive to a thickness of 0.77 μm, and baking the sample on a hot plate at 90° C. for 1 minute;

[0118] 61d) placing the sample after the coating and spin-coating process into a photolithography machine to expose the photoresist in the gate electrode region;

[0119] 61e) The exposed sample is placed in a developer to remove the photoresist and stripping adhesive in the gate electrode region, and then rinsed with ultrapure water and dried with nitrogen.

[0120] 62) Evaporating a gate electrode 10 on the GaN channel layer 6 in the gate electrode region:

[0121] 62a) placing the sample with the photolithographic pattern in the gate electrode region into a plasma stripper for base film treatment for 5 minutes;

[0122] 62b) Place the sample in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 - 6 After the Torr, a gate metal is evaporated on the GaN channel layer 6 in the gate electrode area and the photoresist outside the gate electrode 10 area. The gate metal is a metal stack structure composed of two layers of Ni and Au from bottom to top;

[0123] 62c) The sample after gate metal evaporation is stripped to remove the gate metal, photoresist and stripping glue outside the gate electrode area, and the sample is rinsed with ultrapure water and blown dry with nitrogen to form a gate electrode 10.

[0124] Step 7: Photolithography is performed on the passivation layer 7 to remove the passivation layer above the source electrode 8 and the drain electrode 9 .

[0125] 71) Photolithography opening area on the passivation layer 7:

[0126] 71a) Bake the sample on a hot plate at 200°C for 5 minutes;

[0127] 71b) applying and spinning photoresist at a spinning speed of 3500 rpm, and baking the sample on a hot plate at 90° C. for 1 minute;

[0128] 71c) placing the sample in a photolithography machine to expose the source and drain regions, then placing the exposed sample in a developer to remove the photoresist in the source and drain regions, and then rinsing the sample with ultrapure water and drying with nitrogen;

[0129] 72) Opening holes in the source and drain regions on the SiN passivation layer 7:

[0130] 72a) Using an ICP F-based etching process to remove the passivation layer 7 in the source and drain opening regions, the etching conditions are as follows: CF4 and O2 as the reaction gases, a reaction chamber pressure of 10 mTorr, RF powers of 100 W and 10 W for the upper and lower electrodes, respectively, and an etching depth of 60 nm to 80 nm, down to the surfaces of the source and drain electrodes 8 and 9;

[0131] 72b) The sample is sequentially cleaned in acetone solution, stripping solution, acetone solution, and isopropanol solution to remove the photoresist outside the source and drain opening areas. Finally, the sample is rinsed with ultrapure water and blown dry with nitrogen gas.

[0132] Step 8: Photolithography a metal interconnection region on the passivation layer 7 and the gate electrode 10, and use an electron beam evaporation process to form a metal interconnection layer.

[0133] 81) Photolithography of metal interconnection area on the passivation layer 7 and the gate electrode 10:

[0134] 81a) Bake the sample on a hot plate at 200°C for 5 minutes;

[0135] 81b) applying and spinning a stripping adhesive on the passivation layer 7 and the gate electrode 10 to a thickness of 0.35 μm, and baking the sample on a hot plate at 200° C. for 5 minutes;

[0136] 81c) coating and spinning a photoresist on the stripping adhesive to a thickness of 0.77 μm, and baking the sample on a hot plate at 90° C. for 1 minute;

[0137] 81d) placing the sample after the coating and spin coating process in a photolithography machine to expose the photoresist in the metal interconnection area, then placing the exposed sample in a developer to remove the photoresist and stripping adhesive in the metal interconnection area, and then rinsing the sample with ultrapure water and drying with nitrogen;

[0138] 82) Evaporating a metal interconnect layer on the electrodes in the metal interconnect area and on the photoresist outside the metal interconnect area:

[0139] 82a) placing the sample with the metal interconnection area into a plasma stripper for base film treatment for 5 minutes;

[0140] 82b) Place the sample in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 - 6 After Torr, interconnect metal is evaporated on the electrodes in the metal interconnect area and the photoresist outside the metal interconnect area to form a metal interconnect layer. The metal interconnect layer is a metal stack structure composed of two layers of Ti and Au from bottom to top to lead out the electrode;

[0141] 82c) Stripping the sample after interconnect metal evaporation to remove the metal, photoresist and stripping glue outside the metal interconnect area layer, and then rinse the sample with ultrapure water and blow dry with nitrogen to complete the device fabrication.

[0142] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. An N-face HEMT device with low radio frequency dissipation, characterized in that: include: The epitaxial substrate comprises, from bottom to top, a substrate (1), a GaN buffer layer (2), an Al x Ga 1-x N graded barrier layer (3), AlN insertion layer (4), AlGaN barrier layer (5) and GaN channel layer (6); wherein the Al x Ga 1-x The Al composition X in the N graded barrier layer (3) changes from 0% to 30% from bottom to top; A passivation layer (7) is provided above the GaN channel layer (6); A source electrode (8) and a drain electrode (9) are respectively arranged above the AlGaN barrier layer (5) at both ends of the epitaxial substrate; A gate electrode (10) is disposed on the passivation layer (7); Wherein, the Al x Ga 1-x The interface between the N graded barrier layer (3) and the GaN buffer layer (2) is delta-doped.

2. The N-face HEMT device with low RF dissipation according to claim 1, characterized in that: The δ-doping adopts Si doping with a doping concentration of 1.2×10 13 ~ 2.5×10 13 cm -2 .

3. The N-face HEMT device with low RF dissipation according to claim 1, characterized in that: The thickness of the AlN insertion layer (4) is 1-5 nm.

4. The N-face HEMT device with low RF dissipation according to claim 1, characterized in that: The thickness of the substrate (1) is 400 μm to 500 μm; the thickness of the GaN buffer layer (2) is 1.3 μm to 2 μm; the Al x Ga 1-x The thickness of the N graded barrier layer (3) is 20-30 nm; the thickness of the AlGaN barrier layer (5) is 10-30 nm; and the thickness of the GaN channel layer (6) is 10-20 nm.

5. The N-face HEMT device with low RF dissipation according to claim 1, characterized in that: The material of the substrate (1) is sapphire, Si or SiC.

6. A method for preparing an N-face HEMT device with low radio frequency dissipation, characterized in that: include: Obtain an epitaxial substrate; wherein the epitaxial substrate comprises a substrate, a GaN buffer layer, an Al x Ga 1-x N graded barrier layer, AlN insertion layer, AlGaN barrier layer and GaN channel layer, and the Al x Ga 1-x The interface between the N graded barrier layer and the GaN buffer layer is δ-doped; wherein the Al x Ga 1-x The Al composition X in the N graded barrier layer (3) changes from 0% to 30% from bottom to top; Fabricating a source electrode and a drain electrode on the GaN channel layer; growing a passivation layer on the GaN channel layer; Photolithography a gate electrode region on the passivation layer and fabricating a gate electrode; A metal interconnection layer is prepared to lead the source electrode, the drain electrode and the gate electrode to the surface of the device to complete the device fabrication.

7. The method for preparing an N-face HEMT device with low RF dissipation according to claim 6, characterized in that: The obtaining of the epitaxial substrate comprises: From bottom to top, the substrate, GaN buffer layer, Al x Ga 1-x N graded barrier layer, AlN insertion layer, AlGaN barrier layer and GaN channel layer integrated epitaxial substrate; or sequentially grow GaN buffer layer, AlN x Ga 1-x N graded barrier layer, AlN insertion layer, AlGaN barrier layer and GaN channel layer are formed to prepare the epitaxial substrate.

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