A pump circuit

Abstract

This invention provides a pump circuit, including a voltage divider circuit, a comparator, a clock control circuit, a charge pump, and a power supply circuit. The charge pump outputs a first positive voltage VPOS, and a second positive voltage VPOSW is output from the middle tap of the charge pump. The voltage divider circuit is connected between the first positive voltage VPOS and ground and outputs a divided voltage DIV. The comparator compares the divided voltage DIV with a reference voltage VREF and outputs a clock control signal. The clock control signal is input to the control terminal of the clock control circuit, and the clock signal PCLK is input to the input terminal of the charge pump through the clock control circuit. The power supply voltage for the clock control circuit and the charge pump is VDDI, which is generated by the power supply circuit. This invention adds an NMOS transistor N2 to the power supply module and adds a second positive voltage VPOSM to the pump module, connecting VPOSM to the drain of the NMOS transistor N2. This achieves the goal of fully conducting the NMOS transistor N1 during low-voltage pump startup, making VDDI infinitely close to the external total power supply of the power supply circuit, and also increases the output positive voltage VPOS of the pump circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and more specifically to a pump circuit. Background Technology

[0002] Flash products require high voltage to perform erase and program operations. In order to meet the requirements of Flash products to operate normally over a wide range of power supply voltages, low power consumption, and strong driving capability, a pump circuit is required.

[0003] Figure 1 The diagram shows a circuit diagram of a PUMP BLOCK generating a positive voltage VPOS, as described in the prior art. Figure 1 As shown, the system includes a voltage divider circuit, a comparator (COMP), a clock control circuit (PCLK BLOCK), a charge pump / boost stage module (BoostStage), and a power supply module (VDDigen). The voltage divider circuit is connected between the positive voltage VPOS and ground vgnd, outputting a voltage divider DIV formed by VPOS and ground vgnd. The voltage divider circuit consists of multiple resistors connected in series. The comparator compares the voltage divider DIV with a reference voltage VREF and outputs a clock control signal. The non-inverting input of the comparator is connected to the voltage divider DIV, and the inverting input is connected to the reference voltage VREF. The clock signal PCLK is input to the input of the charge pump through the clock control circuit. The clock control signal adjusts the magnitude of the positive voltage VPOS by regulating the amplitude of the clock signal PCLK. A filter capacitor is connected between the output of the positive voltage VPOS and ground vgnd. The power supply for the PCLK & Boost Stage module is VDDI, which is generated by the VDDigen module. The VDDigen module is powered by an external main power supply VDDA50.

[0004] Figure 1 The circuit shown experiences a sudden increase in power consumption during low-voltage pump startup. VDDI will decrease by a certain amount compared to VDDA50 due to the transistor N1, and the recovery is slower due to the limitations of N1. As a result, the pump circuit will take a longer time to start up to the predetermined target under this VDDI. Summary of the Invention

[0005] In view of this, the present invention provides a pump circuit to solve the problem of poor driving capability of positive voltage VPOS during low-voltage startup of existing pump circuits.

[0006] This invention provides a pump circuit, comprising: a voltage divider circuit, a comparator, a clock control circuit, a charge pump, and a power supply circuit;

[0007] The charge pump outputs a first positive voltage VPOS, and a second positive voltage VPOSM is output from the middle tap of the charge pump; the voltage divider circuit is connected between the first positive voltage VPOS and ground and outputs a divided voltage DIV; the comparator compares the divided voltage DIV with the reference voltage VREF and outputs a clock control signal.

[0008] The clock control signal is input to the control terminal of the clock control circuit, and the clock signal PCLK is input to the input terminal of the charge pump through the clock control circuit. The clock control signal adjusts the amplitude of the clock signal PCLK input to the charge pump, and the magnitudes of the first positive voltage VPOS and the second positive voltage VPOSM are adjusted by adjusting the amplitude of the clock signal PCLK.

[0009] The power supply circuit includes a first current path, a second current path, and an NMOS transistor N2. Both the first and second current paths are connected between the external main power supply and ground. The first current path includes a first current source, a MOS transistor, and a transistor. The second current path includes an NMOS transistor N1 and a second current source. One end of the first current source is connected to the external main power supply, and the other end is connected to the gate of the NMOS transistor N1, the drain of the NMOS transistor N2, the drain and gate of the NMOS transistor N3. The gate of the NMOS transistor N2 is connected to the external main power supply. The second positive voltage VPOSM is output to the source of the NMOS transistor N2. The drain of the NMOS transistor N1 is connected to the external main power supply, and the source outputs the power supply voltage VDDI of the clock control circuit and the charge pump.

[0010] The source of the NMOS transistor N3 is connected to the emitter of the PNP transistor, and the base and collector of the PNP transistor are grounded.

[0011] One end of the second current source is connected to the source of the NMOS transistor N1, and the other end is grounded.

[0012] Preferably, the voltage divider circuit is composed of multiple resistors connected in series.

[0013] Preferably, the non-inverting input of the comparator is connected to the voltage divider DIV, and the inverting input is connected to the reference voltage VREF.

[0014] The voltage value of the second positive voltage VPOSM is approximately half that of the first positive voltage VPOS.

[0015] Preferably, the power supply voltage VDDI of the clock control circuit and the charge pump is infinitely close to the external total power supply.

[0016] Preferably, the external main power supply is a VDDA50.

[0017] Preferably, the circuit further includes a filter capacitor.

[0018] Preferably, the filter capacitor is connected between the output terminal of the charge pump and ground.

[0019] The pump circuit of this invention adds an NMOS transistor N2 to the power supply module and adds a second positive output voltage VPOSM to the pump module. VPOSM is connected to the drain terminal of the NMOS transistor N2. This enables the NMOS transistor N2 to conduct when the low-voltage pump starts, raising the gate terminal potential of the NMOS transistor N1 to VPOSM, so that the NMOS transistor N1 is fully turned on. VDDI is infinitely close to the external total power supply VDDA50 of the power supply circuit, improving the driving capability of the positive voltage VPOS. Moreover, compared with the existing circuit, the output positive voltage VPOS of the pump circuit of this invention is improved. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0021] Figure 1 The diagram shows a schematic of the circuit structure of an existing pump circuit.

[0022] Figure 2 The diagram shown is a schematic diagram of the pump circuit according to an embodiment of the present invention.

[0023] Figure 3 Displayed as Figure 1 The circuit shown is Figure 2 The circuit shown has a potential diagram of the output positive voltage VPOS. Detailed Implementation

[0024] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0025] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0026] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0027] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0028] Figure 2 The diagram shown is a schematic representation of the pump circuit according to an embodiment of the present invention. Figure 2 As shown, the pump circuit of this embodiment includes a pump module and a power supply module. The pump module includes a voltage divider circuit, a comparator (COMP), a clock control circuit (PCLK BLOCK), a charge pump (i.e., a boost stage), and a power supply module (vddigen).

[0029] The charge pump outputs a first positive voltage VPOS, and a second positive voltage VPOSM is output from the center tap of the charge pump. A voltage divider circuit is connected between the first positive voltage VPOS and ground and outputs a divided voltage DIV. The non-inverting input of a comparator is connected to the divided voltage DIV, and the inverting input is connected to the reference voltage VREF. The comparator compares the divided voltage DIV and the reference voltage VREF and outputs a clock control signal. The clock control signal is input to the control terminal of the clock control circuit (PCLK BLOCK). The clock signal PCLK is input to the input terminal of the charge pump (Boost Stage) through the clock control circuit (PCLK BLOCK). The clock control signal adjusts the amplitude of the clock signal PCLK input to the charge pump (Boost Stage), thereby adjusting the magnitudes of the first positive voltage VPOS and the second positive voltage VPOSM.

[0030] In this embodiment of the invention, the voltage source for the clock control circuit and the charge pump is VDDI, which is generated by the power supply module. The power supply circuit of the power supply module (vddigen) includes a first current path, a second current path, and an NMOS transistor N2. Both the first and second current paths are connected between the external main power supply and ground. The first current path includes a first current source, an NMOS transistor N3, and a PNP transistor. The second current path includes an NMOS transistor N1 and a second current source. One end of the first current source is connected to the external main power supply, and the other end is connected to the gate of the NMOS transistor N1, the drain of the NMOS transistor N2, the drain and gate of the NMOS transistor N3. The gate of the NMOS transistor N2 is connected to the external main power supply. The second positive voltage VPOSM is output to the source of the NMOS transistor N2. The drain of the NMOS transistor N1 is connected to the external main power supply, and the source outputs the power supply voltage VDDI for the clock control circuit and the charge pump.

[0031] The source of the NMOS transistor N3 is connected to the emitter of the PNP transistor, and the base and collector of the PNP transistor are grounded.

[0032] One end of the second current source is connected to the source of the NMOS transistor N1, and the other end is grounded.

[0033] In this embodiment of the invention, the voltage divider circuit is composed of multiple resistors connected in series. In other embodiments, the voltage divider circuit can also be formed by multiple MOS transistors connected in series, with the drain and gate of each MOS transistor connected together.

[0034] In this embodiment of the invention, the external main power supply is VDDA50.

[0035] In this embodiment of the invention, the power supply voltage VDDI of the clock control circuit and the charge pump is infinitely close to the external total power supply VDDA50. In this embodiment, when the pump starts at a low potential (VDDA50), NMOS transistor N2 is turned on, raising the gate potential of NMOS transistor N1 to VPOSM, where VPOSM is approximately 0.5*VPOS, thus fully turning on NMOS transistor N1. Therefore, VDDI is infinitely close to VDDA50. Figure 1 In the existing pump circuit, IB_VDDI is clamped by current, and its voltage is much lower than VPOSM. The potential of VDDI is VDDA50-Vt. VDDI serves as the base potential of the clock control circuit (PCLK BLOCK) and the charge pump, i.e. the boost stage, and directly determines the final voltage value of VPOS.

[0036] The pump circuit in this embodiment of the invention also includes a filter capacitor, which is connected between the output terminal of the charge pump (first positive voltage VPOS) and ground.

[0037] Figure 3 Displayed as Figure 1 The circuit shown is compared with the circuit shown in the embodiment of the present invention, which has an output positive voltage VPOS potential diagram. Figure 3 As shown, curve 12 is Figure 1 The diagram shows the output positive voltage VPOS potential of the existing pump circuit; curve 11 shows the output positive voltage VPOS potential of the pump circuit according to the embodiment of the present invention. As can be seen from the diagram, adding an NMOS transistor N2 to the power supply module and adding a second positive output voltage VPOSM to the pump module, and connecting VPOSM to the drain terminal of the NMOS transistor N2, can effectively increase the output positive voltage VPOS of the pump circuit. In this embodiment of the present invention, the VPOS potential is increased from 8.65V to 8.85V.

[0038] In summary, the pump circuit of this embodiment adds an NMOS transistor N2 to the power module, adds a second positive output voltage VPOSM to the pump module, and connects VPOSM to the drain terminal of the NMOS transistor N2. This enables the NMOS transistor N2 to conduct during low-voltage pump startup, raising the gate potential of the NMOS transistor N1 to VPOSM, thus fully turning on the NMOS transistor N1. VDDI is then infinitely close to the external total power supply VDDA50 of the power circuit, improving the driving capability of the positive voltage VPOS. Moreover, compared with existing circuits, the output positive voltage VPOS of the pump circuit of this invention is improved.

[0039] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A pump circuit, characterized by, The circuit comprises a voltage dividing circuit, a comparator, a clock control circuit, a charge pump and a power supply circuit. The output of the charge pump outputs a first positive voltage VPOS, and a second positive voltage VPOSM is output from the intermediate tap of the charge pump; the voltage dividing circuit is connected between the first positive voltage VPOS and ground and outputs a voltage division DIV; the comparator compares the voltage division DIV and a reference voltage VREF and outputs a clock control signal; The clock control signal is input to the control end of the clock control circuit, a clock signal PCLK is input to the input end of the charge pump through the clock control circuit, and the clock control signal adjusts the amplitude of the clock signal PCLK input to the charge pump, and the size of the first positive voltage VPOS and the second positive voltage VPOSM is adjusted by adjusting the amplitude of the clock signal PCLK; The power supply circuit comprises a first current path, a second current path and an NMOS tube N2, the first current path and the second current path are both connected between an external total power supply and ground, the first current path comprises a first current source, an NMOS tube N3 and a PNP transistor, and the second current path comprises an NMOS tube N1 and a second current source; One end of the first current source is connected to the external total power supply, and the other end is connected to the gate of the NMOS tube N1, the drain of the NMOS tube N2, the drain and gate of the NMOS tube N3, the gate of the NMOS tube N2 is connected to the external total power supply, the second positive voltage VPOSM is output to the source of the NMOS tube N2, the drain of the NMOS tube N1 is connected to the external total power supply, and the source outputs the power supply voltage VDDI of the clock control circuit and the charge pump; The source of the NMOS tube N3 is connected to the emitter of the PNP transistor, and the base and collector of the PNP transistor are grounded; One end of the second current source is connected to the source of the NMOS tube N1, and the other end is connected to ground.

2. The pump circuit of claim 1, wherein, The voltage dividing circuit is composed of a plurality of resistors connected in series.

3. The pump circuit of claim 1, wherein, The non-inverting input of the comparator is connected to the voltage division DIV, and the inverting input is connected to the reference voltage VREF.

4. The pump circuit of claim 1, wherein, The voltage value of the second positive voltage VPOSM is about half of the first positive voltage VPOS.

5. The pump circuit of claim 1, wherein, The power supply voltage VDDI of the clock control circuit and the charge pump is infinitely close to the external total power supply.

6. The pump circuit of claim 1, wherein, The external total power supply is VDDA50.

7. The pump circuit of claim 1, wherein, The circuit further comprises a filter capacitor.

8. The pump circuit of claim 7, wherein, The filter capacitor is connected between the output of the charge pump and ground.

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