Voltage providing unit, voltage providing method, display driving module, and display device

Abstract

The present disclosure provides a voltage supply unit, a voltage supply method, a display driving module, and a display device. The voltage supply unit is applied to a display panel and is configured to provide a control voltage signal for a driving circuit. The voltage supply unit includes a buck circuit and a first level conversion circuit. The buck circuit is configured to receive a first voltage signal and perform a buck operation on the first voltage signal to obtain a second voltage signal. The first level conversion circuit is connected to the buck circuit and is configured to receive an input control voltage, a third voltage signal, and the second voltage signal, and generate a control voltage signal according to the input control voltage, the third voltage signal, and the second voltage signal, so that the voltage value of the control voltage signal is less than a predetermined voltage value. Embodiments of the present disclosure can achieve level control of the control voltage signal, can reduce the influence of too high a level of the control voltage signal on the performance of the display panel, and help improve the reliability of the display panel.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of display technologies, and in particular, to a voltage providing unit, a voltage providing method, a display driving module, and a display device. Background Art

[0002] Large-sized display panels are popular due to their larger display areas. At the same time, oxide thin-film transistors (Oxide TFTs) are gradually applied to various display panels due to their technical advantages such as high mobility. Summary of the Invention

[0003] In a first aspect, embodiments of the present disclosure provide a voltage providing unit, which is applied to a display panel and is configured to provide a control voltage signal for a driving circuit. The voltage providing unit includes a buck circuit and a first level conversion circuit;

[0004] The buck circuit is configured to receive a first voltage signal and perform a buck operation on the first voltage signal to obtain a second voltage signal;

[0005] The first level conversion circuit is connected to the buck circuit and is configured to receive an input control voltage, a third voltage signal, and the second voltage signal, and generate a control voltage signal based on the input control voltage, the third voltage signal, and the second voltage signal, so that the voltage value of the control voltage signal is less than a predetermined voltage value.

[0006] In some embodiments, the buck circuit includes a switching unit, a storage unit, and a freewheeling unit;

[0007] A first end of the switching unit is connected to an input node of the buck circuit, a second end of the switching unit is connected to a first node, and the switching unit is configured to transmit a signal input to the buck circuit to the storage unit when it is turned on;

[0008] The storage unit is respectively connected to the first node, a second node, and an output node of the buck circuit. The storage unit is configured to store and transmit a signal from the switching unit to the output node when the switching unit is turned on, and transmit the stored signal from the switching unit to the output node when the switching unit is turned off;

[0009] The freewheeling unit is connected to the first node and the second node, and is configured to convert the signal stored in the storage unit into a current when the switching unit is turned off.

[0010] In some embodiments, the switching unit includes:

[0011] A control switch tube, the control switch tube having a control terminal, a first terminal, and a second terminal, the control terminal of the control switch tube being connected to a control signal terminal to obtain a control signal, the first terminal of the control switch being connected to the input node, and the second terminal of the control switch being connected to the first node;

[0012] The storage unit includes:

[0013] A first inductor, one end of the first inductor being connected to the first node and the other end being connected to the output node;

[0014] A first capacitor, one end of the first capacitor being connected to the second node and the other end being connected to the output node;

[0015] The freewheeling unit includes:

[0016] A first diode, the positive electrode of the first diode being connected to the second node and the negative electrode of the first diode being connected to the first node;

[0017] The second node is grounded.

[0018] In some embodiments, the predetermined voltage value is less than or equal to 27 volts.

[0019] In some embodiments, the range of the predetermined voltage value is 15 to 26 volts.

[0020] In a second aspect, an embodiment of the present disclosure provides a voltage providing method, which is applied to the voltage providing unit described in any one of the first aspects. The voltage providing method includes:

[0021] The buck circuit receives a first voltage signal and performs a buck operation on the first voltage signal to obtain a second voltage signal;

[0022] The first level conversion circuit receives an input control voltage, a third voltage signal, and the second voltage signal, and generates a control voltage signal according to the input control voltage, the third voltage signal, and the second voltage signal, so that the voltage value of the control voltage signal is less than a predetermined voltage value.

[0023] In some embodiments, the control voltage signal is a square wave voltage signal;

[0024] The high voltage value of the control voltage signal is the voltage value of the second voltage signal, and the low voltage value of the control voltage signal is the voltage value of the third voltage signal;

[0025] The high voltage value of the control voltage signal is less than the predetermined voltage value.

[0026] In a third aspect, embodiments of the present disclosure provide a display driving module, including a driving circuit, a timing controller, a power management integrated circuit, and the voltage providing unit according to any one of the first aspect;

[0027] The timing controller is configured to provide the input control voltage;

[0028] The power management integrated circuit is configured to provide the first voltage signal;

[0029] The voltage providing unit is configured to provide a control voltage signal to the driving circuit.

[0030] In some embodiments, the display driving module further includes a second level conversion circuit, which is connected to the timing controller, the power management integrated circuit, and the driving circuit. The second level conversion circuit is configured to receive a first timing control signal, a first driving control signal, the first voltage signal, and the third voltage signal, and then generate a second timing signal, a common signal, and a second driving control signal, and transmit them to the driving circuit.

[0031] In some embodiments, the driving circuit includes:

[0032] An input sub-circuit, connected to an input signal terminal and a pull-up node, configured to transmit an input signal provided by the input signal terminal to the pull-up node under the control of the input signal terminal;

[0033] A pull-down node control sub-circuit, connected to the input signal terminal, a first power supply voltage signal terminal, the pull-up node, and a first pull-down node, configured to transmit a power supply voltage signal provided by the first power supply voltage signal terminal to the first pull-down node under the control of the first power supply voltage signal terminal and the pull-up node;

[0034] An output sub-circuit, connected to the pull-up node, a clock signal terminal, the first pull-down node, a third voltage signal terminal, and a first output signal terminal, configured to transmit a clock signal provided by the clock signal terminal to the first output signal terminal under the control of the pull-up node, and transmit a third voltage signal provided by the third voltage signal terminal to the first output signal terminal under the control of the first pull-down node;

[0035] A noise reduction sub-circuit, connected to the pull-up node, the third voltage signal terminal, and the first pull-down node, configured to transmit a third voltage signal provided by the third voltage signal terminal to the pull-up node under the control of the first pull-down node;

[0036] The first reset sub - circuit is connected to the pull - up node, the first reset signal terminal, and the third voltage signal terminal. The first reset sub - circuit is configured to transmit the third voltage signal provided by the third voltage signal terminal to the first pull - down node under the control of the reset signal provided by the first reset signal terminal.

[0037] In a fourth aspect, an embodiment of the present disclosure provides a display device, including the display driving module according to any one of the third aspects.

[0038] The voltage providing unit of the embodiment of the present disclosure is applied to a display panel and is configured to provide a control voltage signal for a driving circuit. The voltage providing unit includes a buck circuit and a first level conversion circuit. The buck circuit is configured to receive a first voltage signal and perform a buck operation on the first voltage signal to obtain a second voltage signal. The first level conversion circuit is connected to the buck circuit and is configured to receive an input control voltage, a third voltage signal, and the second voltage signal, and generate a control voltage signal according to the input control voltage, the third voltage signal, and the second voltage signal, so that the voltage value of the control voltage signal is less than a predetermined voltage value. By providing the buck circuit and the first level conversion circuit, the embodiment of the present disclosure can achieve level control of the control voltage signal, reduce the influence of the too - high level of the control voltage signal on the performance of the display panel, and contribute to improving the reliability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments of the present disclosure. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0040] Figure 1A is the circuit diagram of the driving circuit in an embodiment of the present disclosure;

[0041] Figure 1B is another circuit diagram of the driving circuit in an embodiment of the present disclosure;

[0042] Figure 2 is Figure 1B the driving timing diagram of the shown driving circuit;

[0043] Figure 3 is the simulation schematic diagram of the transistor in an embodiment of the present disclosure;

[0044] Figure 4 is the relationship curve between the initial state and the failure state of the transistor in an embodiment of the present disclosure;

[0045] Figure 5 It is a schematic diagram of the hot carrier injection failure mechanism in an embodiment of the present disclosure;

[0046] Figure 6 It is a circuit diagram of a test circuit in an embodiment of the present disclosure;

[0047] Figure 7 It is a schematic structural diagram of a display driving module provided in an embodiment of the present disclosure;

[0048] Figure 8 It is a circuit diagram of a buck circuit in an embodiment of the present disclosure. Detailed implementation manners

[0049] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some, rather than all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0050] Due to the advantage of high mobility, the liquid crystal display panel (LCD) technology using oxide thin film transistors (Oxide TFT) is gradually replacing the LCD using a-Si TFT (amorphous silicon thin film transistor). However, compared with the existing a-Si TFT, the Oxide TFT has a certain gap in stability and yield.

[0051] The inventors of the present disclosure found in the process of implementing the technical solutions of the present application that large-size, high-resolution, and high-refresh-rate display panels have relatively high requirements for driving voltage. Many large-size display panels adopt the driving method of Gate driver On Array (GOA, array substrate driving circuit, which is also called array substrate row driving when it is located in the row direction of the display panel) to achieve narrow bezel display and also help to reduce costs. In the embodiments of the present disclosure, the driving circuit is taken as GOA for exemplary illustration.

[0052] To reduce the signal attenuation and delay caused by large size and high resolution, in the related art, it is usually achieved by increasing the driving voltage. For example, the high level of the GOA of a certain display panel is above 30V and the low level is below -10V.

[0053] When the requirements of the display panel are relatively high, such as large size, high refresh rate or high resolution, its driving voltage will be further increased. For example, taking an Oxide TFT display panel of 110 inches, 8K, 120Hz (8000 resolution, 120Hz refresh rate) as an example, to reduce the RC Delay (capacitance-resistance delay), the GOA driving voltage is usually a high voltage VGH of about 32V and a low voltage LVGL of about -15V.

[0054] In at least one embodiment of the present disclosure, the driving circuit in the display device may include multiple-stage driving sub-circuits. The driving circuit may be configured to provide driving signals for pixel circuits located within the effective display area. The driving signals may be, for example, gate driving signals or light emission control signals, but are not limited thereto.

[0055] In at least one embodiment of the present disclosure, a driving circuit is provided.

[0056] As Figure 1A shown, the driving circuit includes: an input sub-circuit 101, a pull-down node control sub-circuit 102, an output sub-circuit 103, a noise reduction sub-circuit 104, and a first reset sub-circuit 105.

[0057] Furthermore, as Figure 1A and Figure 1B shown, in some embodiments, the input sub-circuit 101 includes a first transistor M1. The input sub-circuit is connected to an input signal terminal I and a pull-up node PU. Specifically, the control electrode and the first electrode of the first transistor M1 are connected to the input signal terminal I, and the second electrode is connected to the pull-up node PU. The input sub-circuit 101 is configured to transmit the input signal provided by the input signal terminal I to the pull-up node PU under the control of the input signal terminal I.

[0058] The pull-down node control sub-circuit 102 includes a fifth transistor M5. The pull-down node control sub-circuit 102 is connected to a first power supply voltage signal terminal V1, a pull-up node PU, and a first pull-down node PD1.

[0059] The control electrode and the first electrode of the fifth transistor M5 are connected to the first power supply voltage signal terminal V1, and the second electrode of the fifth transistor M5 is connected to the first pull-down node PD1.

[0060] The pull-down node control circuit 102 is configured to transmit the power supply voltage signal provided by the first power supply voltage signal terminal V1 to the first pull-down node PD1 under the control of the first power supply voltage signal terminal V1 and the pull-up node PU.

[0061] In some embodiments, the pull-down node control sub-circuit 102 further includes a first access unit. The first access unit specifically includes a sixth transistor M6. In some embodiments, the first access unit further includes an eighth transistor M6'.

[0062] The control electrode of the sixth transistor M6 is connected to the input signal terminal I, the first electrode is connected to the first pull-down node PD1, and the second electrode is connected to a third voltage signal terminal V3.

[0063] The control electrode of the eighth transistor M6' is connected to the pull-up node PU, the first electrode is connected to the first pull-down node PD1, and the second electrode is connected to the third voltage signal terminal V3.

[0064] The first access unit can transmit the third voltage signal provided by the third voltage signal terminal V3 to the first pull-down node PD1 under the control of the input signal terminal I. In this way, when the input signal provided by the input signal terminal I is at a high level, the electrical potential of the first pull-down node PD1 can be set to a low level, which helps to more accurately ensure that the noise reduction sub-circuit 104, the output sub-circuit 103, and the transistors in the cascade sub-circuit connected to the third voltage signal terminal V3 are not turned on, thereby ensuring the normal operation of the circuit and improving the accuracy of the output signal.

[0065] In some embodiments, the pull-down node control sub-circuit 102 further includes a fourth transistor M5'. The control electrode and the first electrode of the fourth transistor M5' are connected to the second power supply voltage signal terminal V2, and the second electrode of the fourth transistor M5' is connected to the second pull-down node PD2.

[0066] In some embodiments, the pull-down node control sub-circuit 102 further includes a second access unit. The second access unit specifically includes a sixteenth transistor M16. In some embodiments, the second access unit further includes a seventeenth transistor M16'.

[0067] The control electrode of the sixteenth transistor M16 is connected to the pull-up node PU, the first electrode is connected to the second pull-down node PD2, and the second electrode is connected to the third voltage signal terminal V3.

[0068] The control electrode of the seventeenth transistor M16' is connected to the input signal terminal I, the first electrode is connected to the second pull-down node PD2, and the second electrode is connected to the third voltage signal terminal V3.

[0069] As Figure 2 shown, when the first power supply voltage signal terminal V1 provides a high level, the second power supply voltage signal terminal V2 provides a low level. When the first power supply voltage signal terminal V1 provides a low level, the second power supply voltage signal terminal V2 provides a high level. At regular intervals, the first power supply voltage signal terminal V1 and the second power supply voltage signal terminal V2 perform a level conversion, thereby realizing the level control of the first pull-down node PD1 and the second pull-down node PD2.

[0070] The output sub-circuit 103 includes a third transistor M3 and an eleventh transistor M11. The output sub-circuit 103 is connected to the pull-up node PU, the clock signal terminal CK, the first pull-down node PD1, the third voltage signal terminal V3, and the first output signal terminal O1.

[0071] The control electrode of the third transistor M3 is connected to the pull-up node PU, the first electrode is connected to the clock signal terminal CK, and the second electrode is connected to the first output signal terminal O1.

[0072] The control electrode of the eleventh transistor M11 is connected to the first pull - down node PD1, the first pole is connected to the first output signal terminal O1, and the second pole is connected to the third voltage signal terminal V3.

[0073] The output sub - circuit 103 may further include a fourteenth transistor M11'. The control electrode of the fourteenth transistor M11' is connected to the second pull - down node PD2, the first pole is connected to the first output signal terminal O1, and the second pole is connected to the third voltage signal terminal V3.

[0074] The output sub - circuit 103 is configured to transmit the clock signal provided by the clock signal terminal CK to the first output signal terminal O1 under the control of the pull - up node PU, and transmit the third voltage signal provided by the third voltage signal terminal V3 to the first output signal terminal O1 under the control of the first pull - down node PD1 or the second pull - down node PD2, so as to output a driving signal.

[0075] The noise reduction sub - circuit 104 includes a tenth transistor M10. The noise reduction sub - circuit 104 is connected to the pull - up node PU, the third voltage signal terminal V3, and the first pull - down node PD1.

[0076] The control electrode of the tenth transistor M10 is connected to the first pull - down node PD1, the first pole is connected to the pull - up node PU, and the second pole is connected to the third voltage signal terminal V3.

[0077] In some embodiments, the noise reduction sub - circuit 104 further includes a ninth transistor M10'. The control electrode of the ninth transistor M10' is connected to the second pull - down node PD2, the first pole is connected to the pull - up node PU, and the second pole is connected to the third voltage signal terminal V3.

[0078] The noise reduction sub - circuit 104 is configured to transmit the third voltage signal provided by the third voltage signal terminal V3 to the pull - up node PU under the control of the first pull - down node PD1.

[0079] The first reset sub - circuit 105 includes a second transistor M2. The first reset sub - circuit 105 is connected to the pull - up node PU, the first reset signal terminal Rs, and the third voltage signal terminal V3.

[0080] The control electrode of the second transistor M2 is connected to the first reset signal terminal Rs, the first pole is connected to the pull - up node PU, and the second pole is connected to the third voltage signal terminal V3.

[0081] The first reset sub - circuit 105 is configured to transmit the third voltage signal provided by the third voltage signal terminal V3V3 to the pull - down node under the control of the reset signal provided by the first reset signal terminal Rs.

[0082] In some embodiments of the present disclosure, the driving circuit may further include a cascading sub - circuit, such as Figure 1BAs shown, the cascaded sub-circuit includes a thirteenth transistor M13 and a twelfth transistor M12.

[0083] The cascaded sub-circuit is connected to an upper pull node PU, a clock signal terminal CK, a first lower pull node PD1, a third voltage signal terminal V3, and a second output signal terminal O2.

[0084] Specifically, the control electrode of the thirteenth transistor M13 is connected to the upper pull node PU, the first electrode is connected to the clock signal terminal CK, and the second electrode is connected to the second output signal terminal O2.

[0085] The control electrode of the twelfth transistor M12 is connected to the first lower pull node PD1, the first electrode is connected to the second output signal terminal O2, and the second electrode is connected to the third voltage signal terminal V3.

[0086] In some embodiments, the cascaded sub-circuit further includes a fifteenth transistor M12', the control electrode of the fifteenth transistor M12' is connected to the second lower pull node PD2, the first electrode is connected to the second output signal terminal O2, and the second electrode is connected to the third voltage signal terminal V3.

[0087] The cascaded sub-circuit is used to transmit the clock signal provided by the clock signal terminal CK to the second output signal terminal O2 under the control of the upper pull node PU, and to transmit the third voltage signal provided by the third voltage signal terminal V3 to the second output signal terminal O2 under the control of the first lower pull node PD1, so as to output a carry control signal.

[0088] In some embodiments, a second reset sub-circuit is further included, the second reset sub-circuit is used to implement the global reset of the cascaded sub-circuit, the second reset sub-circuit includes a seventh transistor M7, the control electrode of the seventh transistor M7 is connected to the second reset control signal terminal STV, the first electrode is connected to the upper pull node PU, and the second electrode is connected to the third voltage signal terminal V3.

[0089] The second reset sub-circuit is used to transmit the third voltage signal provided by the third voltage signal terminal V3 to the upper pull node PU under the control of the second reset control signal provided by the second reset control signal terminal STV, so as to pull down the potential of the upper pull node PU for reset.

[0090] When the input signal enters from the input signal terminal I, the potential of the upper pull node PU is raised, the potential of the first lower pull node PD1 is pulled down by the sixth transistor M6, when the potential of the upper pull node PU is pulled down by the reset signal of the second transistor M2, the potential of the first lower pull node PD1 resumes to a high potential again, noise reduction of the upper pull node PU is performed through the tenth transistor M10, noise reduction of the first output signal G_out1 is performed through the eleventh transistor M11, and noise reduction of the second output signal G_out2 is performed through the twelfth transistor M12.

[0091] In this embodiment, the control process of the second pull-down node PD2 is similar to that of the first pull-down node PD1. Therefore, only the control process corresponding to the first pull-down node PD1 is taken as an example for illustration in this embodiment.

[0092] The pull-down node driving sub-circuit includes a fifth transistor M5. The pull-down node driving sub-circuit is connected to a first power supply voltage signal terminal V1, a second power supply voltage signal terminal V2, a pull-up node PU, and a first pull-down node PD1.

[0093] The pull-down node driving sub-circuit is configured to transmit the first power supply voltage signal provided by the first voltage signal terminal V1 to the first pull-down node PD1 under the control of the first voltage signal terminal V1 and the pull-up node PU.

[0094] Please further combine Figure 2 with the driving timing diagram of the display substrate shown in Figure 2 wherein, STV0 and STV1 correspond to the second reset control signal provided by the above-mentioned second reset control signal terminal STV, CLK1 to CLK10 are the clock signals provided by the above-mentioned clock signal terminal CK, VDD1 is the first control voltage signal provided by the first voltage signal terminal V1, VDD2 is the second control voltage signal provided by the second voltage signal terminal V2, VGL and LVGL are voltage signals with constant levels, S-out corresponds to the above-mentioned first output signal G_out1, the t1 period corresponds to the Nth frame of image, the t3 period corresponds to the (N + 1)th frame of image, the t2 period corresponds to the blank interval between the Nth frame of image and the (N + 1)th frame of image, and the t4 period corresponds to turning off the display panel.

[0095] Combined with Figure 1B and Figure 2 it can be known that the fifth transistor M5 is turned on for a long time. In this way, the first pull-down node PD1 will be in a high-level state for a long time. In this way, the sixth transistor M6 and the sixteenth transistor M16 are under long-term high-voltage stress. Specifically, the source of the sixth transistor M6 is connected to the LVGL low level, the drain is connected to the first pull-down node PD1, and the gate is connected to the pulse signal of the pull-up node PU. In this way, the sixth transistor M6 is prone to failure. When the sixth transistor M6 fails, the potential of the first pull-down node PD1 cannot be pulled down, and the potentials of the pull-up node PU, the first output signal G_out, and the second output signal G_out2 cannot be set high, resulting in abnormal output.

[0096] Figure 3The simulation results for the sixth transistor M6, where the abscissa is time (microseconds) and the ordinate is voltage (volts). Vgs represents the voltage difference between the gate and the source of the sixth transistor M6, and Vds represents the voltage difference between the source and the drain of the sixth transistor M6. Here, the gate is the control electrode of the sixth transistor M6, and one of the source and the drain is the first electrode of the sixth transistor M6, and the other is the second electrode of the sixth transistor M6. Figure 4 It is the relationship curve between the initial state and the failure state of the sixth transistor M6. Among them, curve 401 corresponds to the initial state, and curve 402 corresponds to the failure state. The abscissa Vg represents the threshold voltage (volts), and the ordinate Id is the drain current (amperes). For the sixth transistor M6, the on-state current is the ordinate. It is vulnerable to the hot carrier effect, manifested as no significant shift in the threshold voltage Vth, but a significant attenuation in the on-state current Ion and a reduction in the output ability.

[0097] As Figure 5 shown, among them, the upper images of the three states on the right correspond to the cross-section A-A', and the lower images of the three states on the right correspond to the cross-section B-B'. Due to the aggravation of Coulomb scattering, the damage caused by hot carrier injection is more serious at low temperatures. For n-type IGZO (indium gallium zinc oxide) semiconductors, the lower the temperature, the closer the Fermi level is to the conduction band; the influence of hot carriers near the conduction band inducing interface states on device characteristics is greater; therefore, it shows that transistors are more likely to fail at low temperatures. For high-mobility oxide thin-film transistors, compared with traditional IGZO thin-film transistors, its valence band is higher and the Fermi level is closer to the conduction band. Therefore, its hot carrier injection effect is more significant, and the device is more likely to fail due to the hot carrier effect.

[0098] In summary, the voltage received by the sixth transistor M6 has the following characteristics: when Vgs is at a high level and Vds is at a low level, electrons accumulate at the source terminal S and the drain terminal D at this time, at the interface between the gate insulating layer and IGZO; when Vgs is at a low level and Vds is at a high level, at this time, at the source terminal S and the drain terminal D, electrons are discharged from the interface to IGZO, and at the same time, they gather towards the drain terminal S under the electric field between the source and the drain; electrons obtain high energy from the electric field to generate hot carriers. Therefore, defects will be generated at the interface between the semiconductor and the gate insulating layer, causing degradation.

[0099] As Figure 6 shown, in the embodiment of the present disclosure, the connection relationship between the fifth transistor M5 and the sixth transistor M6 is simulated, and the corresponding first power supply voltage signal terminal V1, the voltage change of the pull-up node PU, and the constant voltage LVGL of -15V are provided.

[0100] Adjust the voltage of the pull-up node PU and the first power supply voltage signal terminal V1. As shown in Table 1, the high and low levels of the first power supply voltage signal terminal V1 in the original signal are 32V and -15V respectively, and the high and low levels of the pull-up node PU are 40V and -15V respectively. At this time, the measured high and low levels of the first pull-down node PD1 are 22V and -10V respectively.

[0101] Please continue to refer to Experiment 2 in Table 1. When the high level of the first power supply voltage signal terminal V1 is changed to 20V, it is found that after the high level of the first power supply voltage signal terminal V1 decreases, the characteristics of the sixth transistor M6 change less.

[0102] Please refer to Experiment 3 in Table 1. When the high level of the pull-up node PU changes from 40 to 28V, the sixth transistor M6 still deteriorates in characteristics. Thus, it can be proved that reducing the high level of the first power supply voltage signal terminal V1 can reduce the damage to the sixth transistor M6.

[0103] Table 1: Influence of the first power supply voltage signal terminal and the pull-up node voltage on the transistor M6

[0104]

[0105] To obtain the voltage range of the first power supply voltage signal provided by the first power supply voltage signal terminal V1, in the embodiments of the present disclosure, different voltages of the first power supply voltage signal are further set for testing.

[0106] Exemplarily, as shown in Table 2, for a high-mobility Oxide TFT with a bandgap of 2.9eV, when the first power supply voltage signal is greater than 27V, the sixth transistor M6 decays significantly, and its Ion decays by about 40%, indicating that at this time, the hot carrier injection effect is significant. When the first power supply voltage signal is reduced to below 27V, the Ion decay of the sixth transistor M6 is significantly improved, and the Ion decays by about 15%. Continuing to reduce the first power supply voltage signal terminal V1, the decay is slightly improved.

[0107] Table 2: Influence of different first power supply voltage signal terminals on the transistor M6

[0108]

[0109]

[0110] Through research, it is found that when the first power supply voltage signal is reduced to below 26V, the electric field intensity between the drain terminal D and the gate terminal decreases, and the hot carrier effect is not obvious.

[0111] Based on the above research results, it is considered that in order to make the high voltage difference and delay output by the GOA small, the VGH and LVGL / VGL voltages need to maintain a high voltage difference, and the following technical solutions are proposed.

[0112] An embodiment of the present disclosure provides a voltage supply unit, which is applied to a display panel and is used to provide a control voltage signal for a driving circuit.

[0113] As Figure 7 shown, in some embodiments, the voltage supply unit includes a buck circuit 701 and a first level conversion circuit 702.

[0114] The buck circuit 701 is configured to receive a first voltage signal VGH, perform a buck operation on the first voltage signal VGH, and obtain a second voltage signal VGH'.

[0115] The first level conversion circuit 702 is connected to the buck circuit 701, and is configured to receive an input control voltage VDD, a third voltage signal VGL, and the second voltage signal VGH', and generate control voltage signals VDDO and VDDE according to the input control voltage VDD, the third voltage signal VGL, and the second voltage signal VGH', so that the voltage values of the control voltage signals VDDO and VDDE are less than a predetermined voltage value.

[0116] Here, the control voltage signals VDDO and VDDE respectively correspond to Figure 1B the first power supply voltage signal provided by the first power supply voltage signal terminal V1 and the second power supply voltage signal provided by the second power supply voltage signal terminal V2 in the shown embodiment.

[0117] In some embodiments, the predetermined voltage value is less than or equal to 27V. Further, the range of the predetermined voltage value is 15V to 26V. According to the above experimental results, controlling the predetermined voltage value to be less than or equal to 27V can reduce the possible adverse effects on transistors, for example, the above-mentioned sixth transistor M6.

[0118] The first level conversion circuit 702 may select a level shifter. The first level conversion circuit 702 generates the control voltage signals VDDO and VDDE according to the waveform of the input control voltage VDD signal provided by the timing controller 705 and the levels of the third voltage signal VGL and the second voltage signal VGH'. Here, the timing controller may be a logic board TCON.

[0119] The buck circuit 701 in this embodiment may select an existing or improved buck circuit 701 as long as it can meet the buck requirement.

[0120] In some embodiments, the buck circuit 701 includes a switching unit, a storage unit, and a freewheeling unit.

[0121] As Figure 8As shown, the first end of the switching unit is connected to the input node 801 of the buck circuit 701, the second end of the switching unit is connected to the first node N1, and the switching unit is configured to transmit the signal input to the buck circuit 701 to the storage unit when it is turned on.

[0122] The storage unit is respectively connected to the first node N1, the second node N2, and the output node 802 of the buck circuit 701. The storage unit is configured to store and transmit the signal from the switching unit to the output node 802 when the switching unit is conducting, and transmit the stored signal from the switching unit to the output node 802 when the switching unit is off.

[0123] The freewheeling unit is connected to the first node N1 and the second node N2, and the freewheeling unit is configured to convert the signal stored in the storage unit into a current to maintain the continuity of the current when the switching unit is off.

[0124] In some embodiments, the switching unit includes: a control switch tube T, the control switch tube T has a control end, a first end, and a second end. The control end of the control switch tube T is connected to the control signal terminal Ctrl to obtain a control signal. The first end of the control switch is connected to the input node 801, and the second end of the control switch is connected to the first node N1.

[0125] The storage unit includes: a first inductor L, one end of the first inductor L is connected to the first node N1, and the other end is connected to the output node 802; a first capacitor C1, one end of the first capacitor C1 is connected to the second node N2, and the other end is connected to the output node 802; the freewheeling unit includes: a first diode VD, the positive electrode of the first diode VD is connected to the second node N2, and the negative electrode of the first diode VD is connected to the first node N1; the second node N2 is grounded.

[0126] The buck circuit of this embodiment can adjust the third voltage signal VGL with a higher level to the second voltage signal VGH' with a lower level to achieve voltage regulation.

[0127] The embodiments of the present disclosure provide a voltage providing method applied to the voltage providing unit described in any one of the above.

[0128] In one embodiment, the voltage providing method includes:

[0129] The buck circuit receives the first voltage signal VGH and performs a buck operation on the first voltage signal VGH to obtain the second voltage signal VGH';

[0130] The first level conversion circuit receives an input control voltage VDD, a third voltage signal VGL, and a second voltage signal VGH', and generates control voltage signals VDDO and VDDE according to the input control voltage VDD, the third voltage signal VGL, and the second voltage signal VGH', so that the voltage values VDDO and VDDE of the control voltage signals are less than a predetermined voltage value.

[0131] In this embodiment, the first level conversion circuit generates control voltage signals VDDO and VDDE according to the waveform of the input control voltage signal VDD provided by the timing controller and the levels of the third voltage signal VGL and the second voltage signal VGH'.

[0132] In some embodiments, the control voltage signal is a square wave voltage signal;

[0133] The high voltage value of the control voltage signals VDDO and VDDE is the voltage value of the second voltage signal VGH', and the low voltage value of the control voltage signals VDDO and VDDE is the voltage value of the third voltage signal VGL;

[0134] The high voltage value of the control voltage signals VDDO and VDDE is less than the predetermined voltage value.

[0135] In some embodiments, both the first voltage signal VGH and the third voltage signal VGL are constant voltage signals. Correspondingly, the second voltage signal VGH' obtained by stepping down the first voltage signal VGH is also a constant voltage signal. During the adjustment process, the period and duty cycle of the input control voltage signal VDD are kept unchanged, and the high level of the input control voltage signal VDD is adjusted based on the second voltage signal VGH', and the low level of the input control voltage signal VDD is adjusted based on the third voltage signal VGL to obtain the control voltage signals VDDO and VDDE.

[0136] In some embodiments, the predetermined voltage value is less than or equal to 27V. Further, the range of the predetermined voltage value is 15V to 26V. Controlling the predetermined voltage value to be less than or equal to 27V can reduce the possible adverse effects on the transistors.

[0137] In some of these embodiments, the control voltage signals VDDO and VDDE have the same period and duty cycle as the input control voltage VDD.

[0138] By providing this step-down circuit, the high level of the input control voltage VDD can be reduced to obtain the control voltage signals VDDO and VDDE, avoiding the possible adverse effects of the high level on the transistors, which helps to improve the reliability of the display panel. Exemplarily, it can be the above-mentioned sixth transistor M6.

[0139] The embodiments of the present disclosure provide a display driving module, such asFigure 7 As shown, it includes a driving circuit 704, a timing controller 705, a power management integrated circuit 703, and the voltage providing unit in any one of the above embodiments. Among them, the timing controller 705 is used to provide an input control voltage VDD. The power management integrated circuit 703 can be a PMIC (Power Management IC). The power management integrated circuit 703 is used to provide a first voltage signal VGH. The voltage providing unit is used to control the voltage signals VDDO and VDDE to the driving circuit 704.

[0140] In some embodiments, the display driving module further includes a second level conversion circuit 406. When applied to Figure 1B the driving circuit 704 as shown, the second level conversion circuit 706 is used to receive the first timing control signals CLK1 to CLK10, the first driving control signal STVN, the third voltage signal VGL, and the first voltage signal VGH. Then, according to the levels of the first voltage signal VGH and the third voltage signal VGL, it adjusts the levels of the first timing control signals CLK1 to CLK10 and the first driving control signal STVN to obtain the second timing control signals CLK1' to CLK10' and the second driving control signal STVN', and outputs them to the driving circuit 704. At the same time, the second level conversion circuit 706 is also used to provide the common voltage VSS to the driving circuit 704.

[0141] Here, the first driving control signal STVN refers to the above-mentioned second reset control signal. Exemplarily, it can be Figure 2 STV0 and STV1 shown in, and the third voltage signal VGL and the first voltage signal VGH correspond to the signals with fixed levels above.

[0142] In some embodiments, the driving circuit 704 includes a pull-down node control circuit. The pull-down node control circuit is respectively connected to the control voltage terminal and the pull-down node, and is used to transmit the control voltage signals VDDO and VDDE from the control voltage terminal to the pull-down node.

[0143] In this embodiment, since the high voltages of the control voltage signals VDDO and VDDE are relatively low, it can avoid the influence of the high voltage on the transistors connected to the pull-down node. Exemplarily, it can be Figure 1B the sixth transistor M6 in the driving circuit 704 as shown, which helps to reduce the possibility of transistor failure, and thus helps to improve the reliability of the display panel.

[0144] An embodiment of the present disclosure provides a display device, including the display driving module in any one of the above.

[0145] The display device according to the embodiments of the present disclosure includes all the technical solutions of the above-described display driving module embodiments, and thus can at least achieve all the above technical effects, which will not be elaborated herein.

[0146] The above are the preferred embodiments of the embodiments of the present disclosure. It should be noted that for those of ordinary skill in the art, without departing from the principles described in the present disclosure, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present disclosure.

Claims

1. A display driving module, comprising a driving circuit, a timing controller, a power management integrated circuit, and a voltage providing unit; The voltage providing unit is applied to a display panel and is configured to provide a control voltage signal for the driving circuit. The voltage providing unit includes a buck circuit and a first level conversion circuit; The buck circuit is configured to receive a first voltage signal and perform a buck operation on the first voltage signal to obtain a second voltage signal; The first level conversion circuit is connected to the buck circuit and is configured to receive an input control voltage, a third voltage signal, and the second voltage signal, and generate a control voltage signal according to the input control voltage, the third voltage signal, and the second voltage signal, so that the voltage value of the control voltage signal is less than a predetermined voltage value; The timing controller is configured to provide the input control voltage; The power management integrated circuit is configured to provide the first voltage signal; The voltage providing unit is configured to provide a control voltage signal to the driving circuit; The display driving module further includes a second level conversion circuit. The second level conversion circuit is connected to the timing controller, the power management integrated circuit, and the driving circuit. The second level conversion circuit is configured to receive a first timing control signal, a first driving control signal, the first voltage signal, and the third voltage signal, and then generate a second timing signal, a common signal, and a second driving control signal, and transmit them to the driving circuit.

2. The display driving module according to claim 1, wherein, The buck circuit includes a switching unit, a storage unit, and a freewheeling unit; A first end of the switching unit is connected to an input node of the buck circuit, a second end of the switching unit is connected to a first node, and the switching unit is configured to transmit a signal input to the buck circuit to the storage unit when it is turned on; The storage unit is respectively connected to the first node, a second node, and an output node of the buck circuit. The storage unit is configured to store and transmit a signal from the switching unit to the output node when the switching unit is turned on, and transmit the stored signal from the switching unit to the output node when the switching unit is turned off; The freewheeling unit is connected to the first node and the second node, and the freewheeling unit is configured to convert the signal stored in the storage unit into a current when the switching unit is turned off.

3. The display driving module according to claim 2, wherein, The switching unit includes: A control switch transistor, which has a control terminal, a first end, and a second end. The control terminal of the control switch transistor is connected to a control signal terminal to obtain a control signal. The first end of the control switch is connected to the input node, and the second end of the control switch is connected to the first node; The storage unit includes: A first inductor, one end of the first inductor is connected to the first node, and the other end is connected to the output node; A first capacitor, one end of the first capacitor is connected to the second node, and the other end is connected to the output node; The freewheeling unit includes: A first diode, the positive electrode of the first diode is connected to the second node, and the negative electrode of the first diode is connected to the first node; The second node is grounded.

4. The display driving module according to any one of claims 1 to 3, wherein, The predetermined voltage value is less than or equal to 27 volts.

5. The display driving module according to claim 4, wherein, The range of the predetermined voltage value is from 15 to 26 volts.

6. The display driving module according to claim 1, wherein, The drive circuit includes: An input sub-circuit, connected to an input signal terminal and a pull-up node, the input sub-circuit is configured to transmit an input signal provided by the input signal terminal to the pull-up node under the control of the input signal terminal; A pull-down node control sub-circuit, connected to the input signal terminal, a first power supply voltage signal terminal, the pull-up node, and a first pull-down node, the pull-down node control sub-circuit is configured to transmit a power supply voltage signal provided by the first power supply voltage signal terminal to the first pull-down node under the control of the first power supply voltage signal terminal and the pull-up node; An output sub-circuit, connected to the pull-up node, a clock signal terminal, the first pull-down node, a third voltage signal terminal, and a first output signal terminal, the output sub-circuit is configured to transmit a clock signal provided by the clock signal terminal to the first output signal terminal under the control of the pull-up node, and transmit a third voltage signal provided by the third voltage signal terminal to the first output signal terminal under the control of the first pull-down node; A noise reduction sub-circuit, connected to the pull-up node, the third voltage signal terminal, and the first pull-down node, the noise reduction sub-circuit is configured to transmit a third voltage signal provided by the third voltage signal terminal to the pull-up node under the control of the first pull-down node; A first reset sub-circuit, connected to the pull-up node, a first reset signal terminal, and the third voltage signal terminal, the first reset sub-circuit is configured to transmit a third voltage signal provided by the third voltage signal terminal to the first pull-down node under the control of a reset signal provided by the first reset signal terminal.

7. A voltage supply method, applied to a voltage supply unit in the display driving module according to any one of claims 1 to 6, the voltage supply method includes: The buck circuit receives a first voltage signal and performs a buck operation on the first voltage signal to obtain a second voltage signal; The first level conversion circuit receives an input control voltage, a third voltage signal, and the second voltage signal, and generates a control voltage signal according to the input control voltage, the third voltage signal, and the second voltage signal, so that the voltage value of the control voltage signal is less than a predetermined voltage value.

8. The voltage providing method according to claim 7, wherein, The control voltage signal is a square wave voltage signal; The high voltage value of the control voltage signal is the voltage value of the second voltage signal, and the low voltage value of the control voltage signal is the voltage value of the third voltage signal; The high voltage value of the control voltage signal is less than the predetermined voltage value.

9. A display device, including the display driving module according to any one of claims 1 to 6.

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