Parallel rectifier phase verification method and device

Abstract

The present invention provides a method and device for verifying the phase of parallel rectifiers, relating to the field of power electronics technology. The method comprises: for multiple parallel rectifiers, during the pre-charging process of each rectifier, collecting the incoming line voltage signal of each rectifier; filtering the incoming line voltage signal of each rectifier to obtain the incoming line voltage signal of each rectifier at a first frequency and a second frequency; superimposing the incoming line voltage signals of each rectifier at the first frequency and the second frequency to obtain a superimposed incoming line voltage signal; filtering the superimposed incoming line voltage signal to determine the effective value of the superimposed incoming line voltage signal before and after filtering; if the ratio of the effective value of the superimposed incoming line voltage signal before and after filtering is greater than a preset threshold, determining that there is a phase deviation of the multiple parallel rectifiers. The present invention can verify the phase of the parallel rectifiers and ensure the stability of the parallel rectifier circuit.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a method and device for verifying the phase of a parallel rectifier. Background Art

[0002] This section is intended to provide a background or context to the embodiments of the invention that are recited in the claims. No statement herein is admitted to be prior art by virtue of its inclusion in this section.

[0003] During the use of parallel rectifiers, due to the characteristics of the rectifiers and the influence of the external environment, the phase of the parallel rectifiers may deviate. This phase deviation can cause logical errors in the trigger signal, destroying the stability of the parallel rectifier circuit, causing one rectifier in the circuit to withstand excessive voltage, resulting in damage to the rectifier. Therefore, it is necessary to verify the phase of the parallel rectifiers. Summary of the Invention

[0004] In an embodiment of the present invention, a parallel rectifier phase verification method is proposed to verify the parallel rectifier phase and ensure the stability of the parallel rectifier circuit, including:

[0005] For multiple rectifiers connected in parallel, during the pre-charging process of each rectifier, the incoming line voltage signal of each rectifier is collected;

[0006] Filtering the incoming line voltage signal of each rectifier to obtain the incoming line voltage signal of each rectifier at a first frequency and a second frequency;

[0007] Superimposing the incoming line voltage signals of each rectifier at the first frequency and the second frequency to obtain a superimposed incoming line voltage signal;

[0008] Filtering the superimposed incoming line voltage signal to determine the effective value of the superimposed incoming line voltage signal before and after filtering;

[0009] If the ratio of the effective values ​​of the superimposed incoming line voltage signals before and after filtering is greater than a preset threshold, it is determined that there is a phase deviation between the plurality of rectifiers connected in parallel.

[0010] In an embodiment of the present invention, a parallel rectifier phase verification device is provided to verify the phase of the parallel rectifier and ensure the stability of the parallel rectifier circuit, including:

[0011] The voltage acquisition module is used to collect the incoming line voltage signal of each rectifier during the pre-charging process of each rectifier for multiple rectifiers connected in parallel;

[0012] a first filtering module, configured to filter the incoming line voltage signal of each rectifier to obtain the incoming line voltage signal of each rectifier at a first frequency and a second frequency;

[0013] A voltage superposition module is used to superimpose the incoming line voltage signals of each rectifier at the first frequency and the second frequency to obtain a superimposed incoming line voltage signal;

[0014] a second filtering module, configured to filter the superimposed incoming line voltage signal and determine effective values ​​of the superimposed incoming line voltage signal before and after filtering;

[0015] The phase verification module is used to determine that there is a phase deviation between the multiple rectifiers connected in parallel if the ratio of the effective values ​​of the superimposed incoming line voltage signals before and after filtering is greater than a preset threshold.

[0016] An embodiment of the present invention provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, a method for verifying the phase of a parallel rectifier is implemented.

[0017] An embodiment of the present invention provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, a method for verifying the phase of a parallel rectifier is implemented.

[0018] An embodiment of the present invention provides a computer program product, which includes a computer program. When the computer program is executed by a processor, a method for verifying the phase of a parallel rectifier is implemented.

[0019] The embodiment of the present invention collects the incoming line voltage signal of each rectifier during the pre-charging process of each rectifier for multiple parallel rectifiers; filters the incoming line voltage signal of each rectifier to obtain the incoming line voltage signal of each rectifier at a first frequency and a second frequency; superimposes the incoming line voltage signals of each rectifier at the first frequency and the second frequency to obtain a superimposed incoming line voltage signal; filters the superimposed incoming line voltage signal to determine the effective value of the superimposed incoming line voltage signal before and after filtering; if the ratio of the effective value of the superimposed incoming line voltage signal before and after filtering is greater than a preset threshold, it is determined that there is a phase deviation of the multiple parallel rectifiers. The embodiment of the present invention verifies the phase of the parallel rectifiers, ensures the correct logic of the trigger signal of each rectifier, ensures the stability of the parallel rectifier circuit, enables each rectifier to maintain normal operation, and extends the service life of the rectifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 1 is a flow chart of a method for verifying the phase of a parallel rectifier according to an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of a high-power rectifier circuit in an embodiment of the present invention;

[0023] Figure 3 1 is a specific example diagram of a method for verifying the phase of parallel rectifiers according to an embodiment of the present invention;

[0024] Figure 4 1 is a specific example diagram of a method for verifying the phase of parallel rectifiers according to an embodiment of the present invention;

[0025] Figure 5 1 is a specific example diagram of a method for verifying the phase of parallel rectifiers according to an embodiment of the present invention;

[0026] Figure 6 is a schematic diagram of a parallel rectifier phase verification device according to an embodiment of the present invention;

[0027] Figure 7 1 is a diagram showing a specific example of a parallel rectifier phase verification device according to an embodiment of the present invention;

[0028] Figure 8 Schematic diagram of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] To make the purpose, technical solutions and advantages of the embodiments of the present invention more clear, the embodiments of the present invention are further described in detail below with reference to the accompanying drawings. Here, the exemplary embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0030] The term "and / or" herein simply describes an association relationship, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, and the existence of B alone. In addition, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0031] In the description of this specification, the terms "include", "including", "have", "contain", etc. are all open terms, which mean including but not limited to. The descriptions with reference to the terms "one embodiment", "a specific embodiment", "some embodiments", "for example", etc. mean that the specific features, structures or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. The order of steps involved in each embodiment is used to schematically illustrate the implementation of the present application, and the order of steps therein is not limited and can be appropriately adjusted as needed.

[0032] The principles and spirit of the present invention are explained in detail below with reference to several representative embodiments of the present invention.

[0033] Figure 1 FIG. 1 is a flow chart of a method for verifying the phase of a parallel rectifier according to an embodiment of the present invention. Figure 1 As shown, the method includes:

[0034] Step 101: For multiple rectifiers connected in parallel, during the pre-charging process of each rectifier, collect the line voltage signal of each rectifier;

[0035] Step 102: Filter the incoming line voltage signal of each rectifier to obtain the incoming line voltage signal of each rectifier at a first frequency and a second frequency;

[0036] Step 103, superimposing the incoming line voltage signals of each rectifier at the first frequency and the second frequency to obtain a superimposed incoming line voltage signal;

[0037] Step 104: Filter the superimposed incoming line voltage signal to determine the effective value of the superimposed incoming line voltage signal before and after filtering;

[0038] Step 105: If the ratio of the effective values ​​of the superimposed incoming line voltage signals before and after filtering is greater than a preset threshold, it is determined that there is a phase deviation between the plurality of rectifiers connected in parallel.

[0039] Depend on Figure 1As can be seen from the process shown, the embodiment of the present invention collects the incoming line voltage signal of each rectifier during the pre-charging process of each rectifier for multiple parallel rectifiers; performs a first filtering on the incoming line voltage signal of each rectifier to obtain the incoming line voltage signal of each rectifier at the first frequency and the second frequency; superimposes the incoming line voltage signals of each rectifier at the first frequency and the second frequency to obtain the superimposed incoming line voltage signal; performs a second filtering on the superimposed incoming line voltage signal to determine the effective value of the superimposed incoming line voltage signal before and after filtering; if the ratio of the effective value of the superimposed incoming line voltage signal before and after filtering is greater than a preset threshold, it is determined that there is a phase deviation of the multiple parallel rectifiers. The embodiment of the present invention realizes the verification of the phase of the parallel rectifiers, ensures the correct logic of the trigger signal of each rectifier, ensures the stability of the parallel rectifier circuit, enables each rectifier to maintain normal operation, and extends the service life of the rectifier.

[0040] The embodiments of the present invention are particularly suitable for phase verification of parallel high-power rectifiers. Figure 2 is a schematic diagram of a high-power rectifier circuit in an embodiment of the present invention, Figure 2 C1, C2, and C3 are DC capacitors; D1, D2, D3, D4, D5, and D6 are diodes; G1, G2, G3, G4, G5, and G6 are transistors; L11, L12, and L13 are incoming line reactors; R1, R2, and R3 are protection resistors; Ru, Rv, and Rw are pre-charge resistors; Sw is a three-phase contactor, which includes moving contacts 1, 3, and 5 and static contacts 2, 4, and 6; during the pre-charging process, after the three-phase contactor Sw receives the closing command, the three-phase contactor Sw is energized, and the three-phase moving contact gradually approaches the three-phase static contact. When the moving and static contacts are fully in contact, the contactor energization action is completed. Since the moving contacts of the three-phase contactor Sw cannot move in completely consistent manner during the closing process, some moving contacts may contact the static contacts first. When the two moving and static contacts that first contact close, a single-phase full-bridge rectifier circuit is formed, thereby charging the DC capacitor. Assuming that the U and V phase moving and static contacts are in contact first, forming a single-phase full-bridge rectifier circuit, the charging current I passes through the moving contact 1 and static contact 2 of the three-phase contactor Sw, then passes through the pre-charging resistor Ru, the incoming line reactor L11, and the diode D1 of the insulated gate bipolar transistor IGBT to flow to the positive DC bus, charging the DC capacitors C1~C3, and then passes through the diode D4 of the insulated gate bipolar transistor IGBT, the incoming line reactor L12, and the pre-charging resistor Rv, and then passes through the static contact 4 and moving contact 3 of the three-phase contactor Sw, forming a complete current closed loop between the U phase and the V phase. When the three moving and static contacts are closed, a three-phase full-bridge rectifier circuit is formed to achieve simultaneous pre-charging of the three phases. The embodiment of the present invention can realize phase verification of the parallel high-power rectifiers during the pre-charging process of the parallel high-power rectifiers.

[0041] In order to explain the above-mentioned method for determining if the rectifier incoming line is missing phase more clearly, each step will be described in detail below.

[0042] Figure 3 The following is a specific example of the method for verifying the phase sequence of parallel rectifiers according to an embodiment of the present invention. The detailed process of determining the phase sequence of parallel rectifiers includes:

[0043] Step 301, obtaining the phase sequence of each rectifier;

[0044] Step 302: If the phase sequences of the multiple rectifiers connected in parallel are all positive or negative, pre-charge each rectifier;

[0045] Step 303: If the phase sequence of at least one rectifier among the plurality of rectifiers connected in parallel is different from the phase sequence of the other rectifiers, stop precharging each rectifier.

[0046] In one embodiment of the present invention, when multiple rectifiers connected in parallel are used, the phase sequences of the multiple rectifiers connected in parallel are required to be all positive or negative, which can ensure the normal use of the multiple rectifiers connected in parallel and facilitate the debugging and maintenance of each rectifier. During the pre-charging process of each rectifier, when the DC bus voltage of each rectifier reaches 15% of the rated voltage, the phase sequence of each rectifier is obtained through the upper controller. If the phase sequences of the multiple rectifiers connected in parallel are all positive or negative, pre-charging of each rectifier continues. If the phase sequence of at least one rectifier among the multiple rectifiers connected in parallel is different from the phase sequence of the other rectifiers, pre-charging of each rectifier is stopped, closing of the main circuit breaker is prohibited, thereby extending the service life of the rectifier, and an alarm of "inconsistent phase sequence" is issued.

[0047] In one embodiment of the present invention, a first bandpass filter is used to filter the incoming line voltage signal of each rectifier to obtain the incoming line voltage signal of each rectifier at a first frequency and a second frequency; wherein the center frequency of the first bandpass filter is the average of the first frequency and the second frequency, and the bandwidth is the difference between the first frequency and the second frequency; in a specific implementation, the first frequency is 50 Hz and the second frequency is 100 Hz, that is, the center frequency is 75 Hz and the bandwidth is 50 Hz.

[0048] Figure 4 1 is a specific example diagram of the phase verification method of parallel rectifiers in an embodiment of the present invention.

[0049] In one embodiment of the present invention, during the pre-charging process, the collected line voltage signal U between the U phase and the V phase is UV , the line voltage signal U between phase V and phase W VW refer to Figure 4, a band-pass filter with a center frequency of 75 Hz and a bandwidth of 50 Hz is used to filter the incoming line voltage signal, and all interfering incoming line voltage signals are filtered out, so that the incoming line voltage signals of the rectifier at 50 Hz and 100 Hz can be obtained.

[0050] In one embodiment of the present invention, the incoming line voltage signals of each rectifier at the first frequency and the second frequency are superimposed to obtain a superimposed incoming line voltage signal. Taking the case where the phase difference between two parallel rectifiers is 120 degrees, the incoming line voltage signals of the U phase and the V phase of the two rectifiers are superimposed as an example:

[0051] The line voltage signals of the U-phase and V-phase of the first rectifier are expressed as follows:

[0052] U uv1 (t) = sin(2πft+t1);

[0053] The line voltage signals of the U-phase and V-phase of the second rectifier are expressed as follows:

[0054] U uv2 (t) = sin(2πft-120+t2);

[0055] The superposition of the U-phase and V-phase incoming voltage signals of the two rectifiers is calculated as follows:

[0056]

[0057] Among them, dU uv (t) is the superimposed line voltage signal of the U-phase and V-phase of the two rectifiers; U uv1 (t) is the line voltage signal of the U phase and V phase of the first rectifier; U uv2 (t) is the incoming line voltage signal of phase U and phase V of the second rectifier; f is the frequency of the incoming line voltage signal; t is the sampling point time; t1 is the phase deviation of the first rectifier; t2 is the phase deviation of the second rectifier.

[0058] Figure 5 1 is a specific example diagram of the parallel rectifier phase verification method in an embodiment of the present invention. The detailed process of filtering the superimposed incoming line voltage signal and determining the effective value of the superimposed incoming line voltage signal before and after filtering includes:

[0059] Step 501: Filter the superimposed incoming line voltage signal using a second bandpass filter; wherein the center frequency of the second bandpass filter is a second frequency, and the bandwidth is a preset value;

[0060] Step 502, determining an effective value of the superimposed incoming line voltage signal before filtering based on the period corresponding to the first frequency or the second frequency and the superimposed incoming line voltage signal before filtering;

[0061] Step 503 : determining an effective value of the filtered superimposed incoming line voltage signal according to the period corresponding to the second frequency and the filtered superimposed incoming line voltage signal.

[0062] In one embodiment of the present invention, a second bandpass filter is used to filter the superimposed incoming line voltage signal; wherein the center frequency of the second bandpass filter is 100 Hz, and the bandwidth can be set to a small frequency, such as 2 Hz.

[0063] In one embodiment of the present invention, the superimposed incoming line voltage signal before filtering includes incoming line voltage signals of 50 Hz and 100 Hz. The effective value of the superimposed incoming line voltage signal before filtering is determined based on a period corresponding to 50 Hz, i.e., 20 ms, and the superimposed incoming line voltage signal before filtering. The superimposed incoming line voltage signal after filtering includes an incoming line voltage signal of 100 Hz. The effective value of the superimposed incoming line voltage signal after filtering within 10 ms is determined. The effective value of the superimposed incoming line voltage signal is determined according to the following formula:

[0064]

[0065] Among them, RMS dU is the effective value of the superimposed incoming line voltage signal; t0 is the starting time of the period corresponding to the first frequency or the second frequency; Δt is the period corresponding to the first frequency or the second frequency; dU(t) is the superimposed incoming line voltage signal.

[0066] In one embodiment of the present invention, if the ratio of the effective values ​​of the superimposed incoming line voltage signals before and after filtering is greater than a preset threshold, it is determined that there is a phase deviation of the multiple rectifiers connected in parallel; if the ratio of the effective values ​​of the superimposed incoming line voltage signals before and after filtering is less than or equal to the preset threshold, it is determined that there is no phase deviation of the multiple rectifiers connected in parallel.

[0067] In a specific implementation, if the ratio of the effective values ​​of the superimposed incoming voltage signals before and after filtering is greater than 5%, it is determined that there is a phase deviation among the multiple rectifiers connected in parallel. The phase of each rectifier needs to be checked to ensure that the trigger signal logic of each rectifier is correct, and the main circuit breaker is prohibited from closing, so that each rectifier maintains normal operation, which can extend the service life of the rectifier. If the ratio of the effective values ​​of the superimposed incoming voltage signals before and after filtering is less than or equal to 5%, it is determined that there is no phase deviation among the multiple rectifiers connected in parallel, and the parallel rectifier circuit can operate normally.

[0068] It should be noted that although the operations of the method of the present invention are described in a specific order in the above embodiments and drawings, this does not require or imply that these operations must be performed in this specific order, or that all illustrated operations must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0069] The implementation of the parallel rectifier phase verification device can be referenced to the implementation of the above-mentioned method, and any repetitions will not be repeated. The terms "module" or "unit" used below may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0070] Based on the same inventive concept, the present invention also proposes a parallel rectifier phase verification device, such as Figure 6 As shown, the device includes:

[0071] The voltage acquisition module 601 is used to collect the line voltage signal of each rectifier during the pre-charging process of each rectifier for multiple rectifiers connected in parallel;

[0072] A first filtering module 602 is configured to filter the incoming line voltage signal of each rectifier to obtain the incoming line voltage signal of each rectifier at a first frequency and a second frequency;

[0073] A voltage superposition module 603 is configured to superimpose the incoming line voltage signals of each rectifier at the first frequency and the second frequency to obtain a superimposed incoming line voltage signal;

[0074] A second filtering module 604 is configured to filter the superimposed incoming line voltage signal and determine effective values ​​of the superimposed incoming line voltage signal before and after filtering;

[0075] The phase verification module 605 is configured to determine that there is a phase deviation between the plurality of rectifiers connected in parallel if the ratio of the effective values ​​of the superimposed incoming line voltage signals before and after filtering is greater than a preset threshold.

[0076] Figure 7 FIG is a specific example diagram of a parallel rectifier phase verification device according to an embodiment of the present invention. Figure 7 As shown, in one embodiment of the present invention, Figure 6 The parallel rectifier phase verification device further includes:

[0077] Phase sequence determination module 701, used to obtain the phase sequence of each rectifier;

[0078] The pre-charging control module 702 is used to pre-charge each rectifier if the phase sequences of the multiple rectifiers connected in parallel are all positive or negative sequences; if the phase sequence of at least one rectifier in the multiple rectifiers connected in parallel is different from the phase sequence of the other rectifiers, stop pre-charging each rectifier.

[0079] In one embodiment of the present invention, the first frequency is 50 Hz and the second frequency is 100 Hz.

[0080] In one embodiment of the present invention, the first filtering module 602 is specifically configured to:

[0081] A first bandpass filter is used to filter the incoming line voltage signal of each rectifier to obtain the incoming line voltage signal of each rectifier at the first frequency and the second frequency; wherein the center frequency of the first bandpass filter is the average value of the first frequency and the second frequency, and the bandwidth is the difference between the first frequency and the second frequency.

[0082] In one embodiment of the present invention, the second filtering module 604 is specifically configured to:

[0083] A second band-pass filter is used to filter the superimposed incoming line voltage signal; wherein the center frequency of the second band-pass filter is the second frequency, and the bandwidth is a preset value;

[0084] determining an effective value of the superimposed incoming line voltage signal before filtering based on a period corresponding to the first frequency or the second frequency and the superimposed incoming line voltage signal before filtering;

[0085] The effective value of the filtered superimposed incoming line voltage signal is determined according to the period corresponding to the second frequency and the filtered superimposed incoming line voltage signal.

[0086] In one embodiment of the present invention, the phase verification module 605 is further configured to:

[0087] If the ratio of the effective values ​​of the superimposed incoming line voltage signals before and after filtering is less than or equal to a preset threshold, it is determined that there is no phase deviation between the plurality of rectifiers connected in parallel.

[0088] It should be noted that while the detailed description above mentions several modules of the parallel rectifier phase verification device, this division is merely exemplary and not mandatory. In practice, according to embodiments of the present invention, the features and functions of two or more modules described above may be embodied in a single module. Conversely, the features and functions of a single module described above may be further divided and embodied by multiple modules.

[0089] Based on the above invention concept, Figure 8As shown, the present invention also proposes a computer device 800, including a memory 801, a processor 802, and a computer program 803 stored in the memory 801 and executable on the processor 802, wherein the processor 802 implements the aforementioned parallel rectifier phase verification method when executing the computer program 803.

[0090] Based on the aforementioned inventive concept, the present invention proposes a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the aforementioned parallel rectifier phase verification method is implemented.

[0091] Based on the aforementioned inventive concept, the present invention proposes a computer program product, which includes a computer program. When the computer program is executed by a processor, a method for verifying the phase of a parallel rectifier is implemented.

[0092] The embodiment of the present invention collects the incoming line voltage signal of each rectifier during the pre-charging process of each rectifier for multiple parallel rectifiers; filters the incoming line voltage signal of each rectifier to obtain the incoming line voltage signal of each rectifier at a first frequency and a second frequency; superimposes the incoming line voltage signals of each rectifier at the first frequency and the second frequency to obtain a superimposed incoming line voltage signal; filters the superimposed incoming line voltage signal to determine the effective value of the superimposed incoming line voltage signal before and after filtering; if the ratio of the effective value of the superimposed incoming line voltage signal before and after filtering is greater than a preset threshold, it is determined that there is a phase deviation of the multiple parallel rectifiers. The embodiment of the present invention verifies the phase of the parallel rectifiers, ensures the correct logic of the trigger signal of each rectifier, ensures the stability of the parallel rectifier circuit, enables each rectifier to maintain normal operation, and extends the service life of the rectifier.

[0093] It will be understood by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0094] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0095] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0096] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0097] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for verifying the phase of a parallel rectifier, characterized in that: include: For multiple rectifiers connected in parallel, during the pre-charging process of each rectifier, the incoming line voltage signal of each rectifier is collected; Filtering the incoming line voltage signal of each rectifier to obtain the incoming line voltage signal of each rectifier at a first frequency and a second frequency; Superimposing the incoming line voltage signals of each rectifier at the first frequency and the second frequency to obtain a superimposed incoming line voltage signal; Filtering the superimposed incoming line voltage signal to determine the effective value of the superimposed incoming line voltage signal before and after filtering; If the ratio of the effective values ​​of the superimposed incoming line voltage signals before and after filtering is greater than a preset threshold, it is determined that there is a phase deviation between the multiple rectifiers connected in parallel; The method of filtering the incoming line voltage signal of each rectifier to obtain the incoming line voltage signal of each rectifier at the first frequency and the second frequency includes: Filtering the incoming line voltage signal of each rectifier using a first bandpass filter to obtain the incoming line voltage signal of each rectifier at a first frequency and a second frequency; wherein the center frequency of the first bandpass filter is an average of the first frequency and the second frequency, and the bandwidth is a difference between the first frequency and the second frequency; The step of filtering the superimposed incoming line voltage signal and determining the effective value of the superimposed incoming line voltage signal before and after filtering includes: A second band-pass filter is used to filter the superimposed incoming line voltage signal; wherein the center frequency of the second band-pass filter is the second frequency, and the bandwidth is a preset value; determining an effective value of the superimposed incoming line voltage signal before filtering based on a period corresponding to the first frequency or the second frequency and the superimposed incoming line voltage signal before filtering; The effective value of the filtered superimposed incoming line voltage signal is determined according to the period corresponding to the second frequency and the filtered superimposed incoming line voltage signal.

2. The method according to claim 1, characterized in that Before collecting the incoming line voltage signal of each rectifier, the following steps are also included: Get the phase sequence of each rectifier; If the phase sequences of multiple rectifiers connected in parallel are all positive or negative, pre-charge each rectifier; If the phase sequence of at least one rectifier among the plurality of rectifiers connected in parallel is different from the phase sequence of the other rectifiers, pre-charging of each rectifier is stopped.

3. The method according to claim 1, characterized in that The first frequency is 50 Hz, and the second frequency is 100 Hz.

4. The method according to claim 1, wherein Also includes: If the ratio of the effective values ​​of the superimposed incoming line voltage signals before and after filtering is less than or equal to a preset threshold, it is determined that there is no phase deviation between the plurality of rectifiers connected in parallel.

5. A parallel rectifier phase verification device, characterized in that: include: The voltage acquisition module is used to collect the incoming line voltage signal of each rectifier during the pre-charging process of each rectifier for multiple rectifiers connected in parallel; a first filtering module, configured to filter the incoming line voltage signal of each rectifier to obtain the incoming line voltage signal of each rectifier at a first frequency and a second frequency; A voltage superposition module is used to superimpose the incoming line voltage signals of each rectifier at the first frequency and the second frequency to obtain a superimposed incoming line voltage signal; a second filtering module, configured to filter the superimposed incoming line voltage signal and determine effective values ​​of the superimposed incoming line voltage signal before and after filtering; A phase verification module is used to determine that there is a phase deviation between the multiple rectifiers connected in parallel if the ratio of the effective values ​​of the superimposed incoming line voltage signals before and after filtering is greater than a preset threshold; The first filtering module is specifically configured to filter the incoming line voltage signal of each rectifier using a first bandpass filter to obtain the incoming line voltage signal of each rectifier at a first frequency and a second frequency; wherein the center frequency of the first bandpass filter is an average of the first frequency and the second frequency, and the bandwidth is a difference between the first frequency and the second frequency; The second filtering module is specifically used for: A second band-pass filter is used to filter the superimposed incoming line voltage signal; wherein the center frequency of the second band-pass filter is the second frequency, and the bandwidth is a preset value; determining an effective value of the superimposed incoming line voltage signal before filtering based on a period corresponding to the first frequency or the second frequency and the superimposed incoming line voltage signal before filtering; The effective value of the filtered superimposed incoming line voltage signal is determined according to the period corresponding to the second frequency and the filtered superimposed incoming line voltage signal.

6. The device according to claim 5, characterized in that Also includes: Phase sequence judgment module, used to obtain the phase sequence of each rectifier; The pre-charging control module is used to pre-charge each rectifier if the phase sequences of the multiple rectifiers connected in parallel are all positive or negative sequences; if the phase sequence of at least one rectifier in the multiple rectifiers connected in parallel is different from the phase sequence of the other rectifiers, stop pre-charging each rectifier.

7. The device according to claim 5, characterized in that The first frequency is 50 Hz, and the second frequency is 100 Hz.

8. The device according to claim 5, characterized in that The phase verification module is also used to: If the ratio of the effective values ​​of the superimposed incoming line voltage signals before and after filtering is less than or equal to a preset threshold, it is determined that there is no phase deviation between the plurality of rectifiers connected in parallel.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 4 is implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

11. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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