Wafer Exposure Method and System

Abstract

The present application discloses a wafer exposure method and system. The wafer exposure method includes the following steps: dividing a plurality of exposure units on the wafer surface, including complete exposure units located in the internal area of the wafer and incomplete exposure units located in the edge area of the wafer; obtaining a focus energy matrix table of the photolithography layer to be exposed; obtaining the pattern topography and line width of each complete exposure unit after being exposed under the initial exposure conditions; correcting the exposure conditions of each complete exposure unit according to the focus energy matrix table so that its pattern topography and line width meet the specifications; correcting the exposure conditions of the incomplete exposure units according to the corrected exposure conditions of the complete exposure units adjacent to the incomplete exposure units. By correcting the exposure conditions of the complete exposure units according to their pattern topography and line width, and correcting the exposure conditions of the incomplete exposure units by the exposure conditions of the complete exposure units adjacent to the incomplete exposure units, the present application can greatly improve the pattern topography and line width uniformity within the wafer surface.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing, and particularly to a wafer exposure method and system. Background Art

[0002] The lithography process is a key process in semiconductor manufacturing. The smaller the critical dimension of the lithography pattern, the smaller the size of the manufactured chip. However, as the critical dimension of the pattern decreases, the process window of the lithography process will be significantly reduced, thereby deteriorating the uniformity of the lithography pattern within the wafer plane, reducing the process tolerance, and resulting in the inability to meet the production requirements.

[0003] With the continuous development of semiconductor manufacturing processes, the manufacturing of the first-generation semiconductors (silicon-based semiconductors) and the second-generation semiconductors (compound semiconductors such as gallium arsenide and indium phosphide) gradually tend to use larger-sized wafers to reduce product costs. However, the larger wafer size will bring problems such as wafer warping and poor flatness, which will also reduce the process window of the lithography process, thereby deteriorating the uniformity of the lithography pattern within the wafer plane. In addition, in the lithography process of the third-generation semiconductors (wide-bandgap semiconductors such as silicon carbide and gallium nitride), due to problems such as their own light transmittance and refractive index, the process window of the lithography process will also be reduced, deteriorating the uniformity of the lithography pattern within the wafer plane, making it unable to meet the production requirements. The deterioration of the uniformity of the lithography pattern will cause serious differences in parameters such as the critical dimension and topography of the pattern within the wafer plane, resulting in problems such as large product performance differences and low yield.

[0004] Therefore, it is necessary to propose a new wafer exposure method and system to solve the above problems. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of this application is to provide a wafer exposure method and system for solving the problem of poor uniformity of the lithography pattern within the wafer plane in the prior art.

[0006] To achieve the above purpose and other related purposes, this application provides a wafer exposure method, including the following steps:

[0007] Divide a plurality of exposure units on the surface of the wafer, where the exposure units include complete exposure units located in the internal area of the wafer and incomplete exposure units located in the edge area of the wafer;

[0008] Obtain the focal length energy matrix table of the lithography layer to be exposed;

[0009] Obtain the pattern topography and line width of each of the complete exposure units after being exposed under the initial exposure conditions;

[0010] Modify the exposure conditions of each of the complete exposure units according to the focal length energy matrix table, so that the pattern topography and line width of the complete exposure units meet the specifications;

[0011] Modify the exposure conditions of the incomplete exposure units according to the modified exposure conditions of the complete exposure units adjacent to the incomplete exposure units.

[0012] As an alternative embodiment of the present application, after obtaining the modified exposure conditions of multiple exposure units, partition the multiple exposure units, and modify the exposure conditions of each exposure unit in the same partition, so that each exposure unit in the same partition has the same exposure conditions.

[0013] As an alternative embodiment of the present application, obtain the pattern topography and line width of the complete exposure units by measuring the process control monitoring units in the complete exposure units.

[0014] As an alternative embodiment of the present application, the method for modifying the exposure conditions of the incomplete exposure units includes: obtaining by performing a weighted average calculation on multiple exposure conditions of the complete exposure units adjacent to the incomplete exposure units.

[0015] As an alternative embodiment of the present application, the method for modifying the exposure conditions of the incomplete exposure units includes: obtaining by calculating the linear change trend of multiple exposure conditions of multiple complete exposure units from the incomplete exposure unit to the center of the wafer.

[0016] As an alternative embodiment of the present application, after obtaining the modified exposure conditions of multiple exposure units, it further includes the steps of exposing each exposure unit using the exposure conditions, and obtaining the pattern topography and line width of the complete exposure units, so as to modify the exposure conditions of the complete exposure units and the incomplete exposure units again.

[0017] As an alternative embodiment of the present application, during the lithography exposure process of products in different batches, obtain the pattern topography and line width of the complete exposure units in the previous batch, and modify the exposure conditions of the complete exposure units and the incomplete exposure units, and use the exposure conditions for the lithography exposure of the next batch of products.

[0018] As an alternative embodiment of the present application, the method for obtaining the focal length energy matrix table of the to-be-exposed photolithography layer includes: establishing a focal length energy matrix table library for different products and different photolithography levels, and retrieving the focal length energy matrix table according to the product and photolithography level information.

[0019] The present application also provides a wafer exposure system, including:

[0020] A data storage module, which is used to store the focal length energy matrix tables for different products and lithography levels;

[0021] A lithography exposure module, which divides multiple exposure units on the surface of the wafer. The exposure units include complete exposure units located in the internal area of the wafer and incomplete exposure units located in the edge area of the wafer. The lithography exposure module performs exposure processing on each exposure unit of the wafer according to the input exposure conditions, and outputs the graphic morphology and line width of the exposure units;

[0022] A data processing module, which is used to obtain the focal length energy matrix table stored in the data storage module according to the information of the product and the lithography level, correct the exposure conditions of each complete exposure unit according to the focal length energy matrix table, so that the graphic morphology and line width of the complete exposure unit meet the specifications, correct the exposure conditions of the incomplete exposure unit according to the corrected exposure conditions of the complete exposure unit adjacent to the incomplete exposure unit, and output the corrected exposure conditions to the lithography exposure module.

[0023] As an alternative scheme of the present application, after obtaining the corrected exposure conditions of multiple exposure units, the data processing module partitions the multiple exposure units and corrects the exposure conditions of each exposure unit in the same partition, so that each exposure unit in the same partition has the same exposure conditions.

[0024] As an alternative scheme of the present application, after obtaining the corrected exposure conditions of multiple exposure units, the data processing module outputs the exposure conditions to perform exposure on each exposure unit to the lithography exposure module, and obtains the graphic morphology and line width of the complete exposure unit from the lithography exposure module to correct the exposure conditions of the complete exposure unit and the incomplete exposure unit again.

[0025] As described above, the wafer exposure method and system provided by the present application correct the exposure conditions according to the graphic morphology and line width of the complete exposure unit, and correct the exposure conditions of the incomplete exposure unit through the exposure conditions of the complete exposure unit adjacent to the incomplete exposure unit, which can greatly improve the uniformity of the graphic morphology and line width within the wafer surface. Description of the Drawings

[0026] Figure 1 It shows a flowchart of the steps of the wafer exposure method provided in Embodiment 1 of the present application.

[0027] Figure 2 It shows a flowchart of the specific process of the wafer exposure method provided in Embodiment 1 of the present application.

[0028] Figure 3It shows the flowchart of the composite algorithm partition exposure process provided in Embodiment 1 of the present application.

[0029] Figure 4 It shows the flowchart of the exposure compensation algorithm provided in Embodiment 1 of the present application.

[0030] Figure 5 It shows the flowchart of the edge compensation algorithm provided in Embodiment 1 of the present application.

[0031] Figure 6 It shows the flowchart of the partition algorithm provided in Embodiment 1 of the present application.

[0032] Figure 7 It shows the line width distribution diagram of the exposure unit using the initial exposure conditions provided in Embodiment 1 of the present application.

[0033] Figure 8 It shows the partition distribution diagram of the exposure unit after the partition algorithm provided in Embodiment 1 of the present application.

[0034] Figure 9 It shows the line width distribution diagram of the exposure unit using the corrected exposure conditions provided in Embodiment 1 of the present application. Detailed implementation manners

[0035] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. When detailing the embodiments of the present application, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples, and they should not limit the protection scope of the present application here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0036] For the convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intervening layers.

[0037] In the context of the present application, the structure where the first feature described is "above" the second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0038] Please refer to Figures 1 to 9 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Although only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation, the form, number, and ratio of each component in actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex.

[0039] Embodiment 1

[0040] Please refer to Figures 1 to 9 . This embodiment provides a wafer exposure method, including the following steps:

[0041] 1) Divide a plurality of exposure units on the surface of the wafer to be processed. The exposure units include complete exposure units located in the internal area of the wafer and incomplete exposure units located in the edge area of the wafer;

[0042] 2) Obtain a focus energy matrix table of the photoresist layer to be exposed;

[0043] 3) Obtain the pattern topography and line width of each of the complete exposure units after being exposed under the initial exposure conditions;

[0044] 4) Modify the exposure conditions of each of the complete exposure units according to the focus energy matrix table, so that the pattern topography and line width of the complete exposure units meet the specifications;

[0045] 5) Modify the exposure conditions of the incomplete exposure units according to the modified exposure conditions of the complete exposure units adjacent to the incomplete exposure units.

[0046] In step 1), please refer to Figure 1 step S1 and Figure 7 . Divide a plurality of exposure units (shots) on the surface of the wafer to be processed. The exposure units include complete exposure units 101 located in the internal area of the wafer (i.e., the center of the wafer) and incomplete exposure units 102 located in the edge area of the wafer. In Figure 7Among them, the area covered by the circle represents the area occupied by the wafer for the lithography process, and multiple rectangular areas of the same size represent the areas exposed by the stepper in a single exposure, that is, the exposure units. Among them, the light-colored rectangular area has an area that coincides with the wafer, which is the effective exposure unit that actually performs the exposure operation, while the shaded area is the invalid exposure unit 103, because it has no overlapping area with the wafer or the overlapping area is so small that it can be ignored, so no exposure operation is actually performed. Among the light-colored rectangular areas, the light-colored rectangular areas marked with numbers are entirely located inside the wafer, which are defined as complete exposure units 101, and the numbers marked on them represent the feature size measured by the process control monitor (PCM) unit of the exposure unit, also known as the line width. The process control monitor unit is an area in the wafer used to monitor whether each process step in the semiconductor manufacturing process meets the expectations. It has multiple structures designed for process monitoring. For the monitoring of the lithography process, it is generally monitored by measuring the line width, that is, a graphic structure (generally an L-bar type or hole type graphic structure) specifically designed for line width measurement is set on the lithography mask, and the line width size of the line width measurement structure is measured after lithography exposure to characterize the line width characteristics of the lithography pattern of the exposure unit. The line width measurement structure of the process control monitor unit is generally set in the scribing slot in the edge area of a single exposure unit. When the exposure unit is located in the edge area of the wafer, it is defined as an incomplete exposure unit 102, and the line width measurement structure may be missing, resulting in its inability to measure the feature size through the process control monitor unit. In Figure 7 Among them, the unmarked light-colored rectangular areas are incomplete exposure units 102, which cannot directly measure the feature size of the lithography pattern through the process control monitor unit.

[0047] In step 2), please refer to Figure 1 step S2 of Figure 2 and obtain the focus-energy matrix table of the lithography layer to be exposed. The focus-energy matrix (FEM) is a test method used to check the lithography process window and determine the optimal exposure conditions. It generates different combinations of exposure focus and exposure energy by using different exposure focuses (focus) and exposure energies (energy) on the exposure units at different positions on the wafer, and obtains the graphic morphology and line width under different exposure focuses and exposure energies. The combination of the above data constitutes the focus-energy matrix table. The focus-energy matrix table can determine the optimal exposure focus and exposure energy under specific specification requirements. When performing the test of the focus-energy matrix, for the exposure units within the wafer surface, such as Figure 7In the X-axis and Y-axis directions as shown, generally, different exposure energies are set while fixing the exposure focal length in the X-axis direction, and different exposure focal lengths are set while fixing the exposure energy in the Y-axis direction. In this way, different exposure units within the wafer surface will be exposed under different combinations of exposure focal lengths and exposure energies, and the graphic feature sizes thereof are measured to obtain a focal length - energy matrix table. As an example, a library of focal length - energy matrix tables is established for different products and different lithography levels, and the focal length - energy matrix table is retrieved according to the product and lithography level information. For different lithography levels of different products, the corresponding focal length - energy matrix tables are obtained and stored, and a library of focal length - energy matrix tables is established. In subsequent lithography processes, the corresponding focal length - energy matrix tables can be directly retrieved according to the product and lithography level information to quickly determine the optimal lithography exposure conditions without repeatedly testing and collecting the focal length - energy matrix.

[0048] Figure 2 FIG. is an exemplary flowchart of the specific process of the wafer exposure method provided in this embodiment. After the start node, product information and process layer information of the wafer to be exposed are sequentially obtained at nodes 201 and 202, so as to search for stored lithography process information and focal length - energy matrix tables according to the above information, or as retrieval tags when storing the focal length - energy matrix tables. At node 203, lithography process information is obtained, which should include but is not limited to parameters such as the type of photoresist used in this layer of lithography process, the thickness of the photoresist, the designed line width of the photomask, the target line width of the lithography pattern, and the actual line width variation range. These parameters directly affect the graphic line width and topography of the photoresist after the lithography process under different exposure conditions, and thus also directly affect the data of the focal length - energy matrix table. After obtaining the lithography process information, it is judged whether there is the same lithography process information in the existing database. If not, new focal length - energy matrix (FEM) table data is created at node 204, and the method for obtaining the FEM data is as described above. If there is the same lithography process information in the existing database, the existing focal length - energy matrix (FEM) table data is directly called at node 205, and composite algorithm partition exposure is performed at node 206 according to the focal length - energy matrix (FEM) table data. The specific algorithm process of the composite algorithm partition exposure includes an exposure compensation algorithm, an edge compensation algorithm, and a partition algorithm that are sequentially performed. The above three algorithm processes will be described in detail below.

[0049] In step 3), please refer to Figure 1 step S3 of Figure 3 and Figure 7 to obtain the graphic topography and line width of each of the complete exposure units after being exposed under the initial exposure conditions. The initial exposure conditions can be obtained by retrieving the focal length - energy matrix table. As Figure 7As shown, it is a data distribution diagram obtained by measuring the feature sizes of each exposure unit after lithographic exposure of a specific lithography layer of a specific product. Among them, the numbers marked on the complete exposure unit 101 are the measured feature size values. As an example, Figure 7 For the wafer exposed in the middle, a 4-inch silicon carbide substrate is used, and the epitaxial layer above it includes materials such as GaN, AlN, AlGaN, GaN, or SiN. The size of a single exposure unit is 10.4 mm in length and 96 mm in width. The photoresist used is of the SPR series, the photoresist thickness is 1 μm, the photoresist film thickness uniformity is 0.1%, and the designed line width is 1.8 μm. As an example, in this embodiment, a Nikon NSR i11 lithography machine is taken as an example. In other implementation cases of the present invention, other feasible step-and-repeat lithography machines, scanning lithography machines, immersion lithography machines, etc. with zoned exposure conditions can also be used.

[0050] As Figure 7 shown, the extreme difference in the line width dimensions within the wafer surface is 0.35 μm, and its uniformity is poor, not meeting the specification requirements, which has seriously affected the product yield. As Figure 3 shown, it is Figure 2 a flowchart of the composite algorithm zoned exposure method in Figure 7 As shown. After the start node, at node 301, the focus energy matrix (FEM) information is retrieved, and at node 302, the initial exposure conditions are determined based on the FEM information. At node 303, photolithography process steps such as coating, exposure, and development are performed on the wafer to be exposed according to the initial exposure conditions. At node 304, the line width and topography of each exposure unit are measured. Specifically, the process control monitor (PCM) units of each complete exposure unit are measured to determine the line width and topography. At node 305, a judgment is made as to whether all exposure units meet the specification requirements. If the graphic line width and topography of each exposure unit (shot) meet the specification requirements, the composite algorithm zoned exposure ends. If there are exposure units that do not meet the specification requirements, such as Figure 7 the poor uniformity situation shown, then the exposure compensation algorithm, edge compensation algorithm, and zoned algorithm can be sequentially executed at node 306, and the corrected exposure conditions are obtained at node 307. After the new corrected exposure conditions are obtained at node 307, the wafer is stripped and reworked, and it returns to node 303 to perform coating, exposure, and development again until all exposure units meet the specification requirements.

[0051] In step 4), please refer to Figure 1 step S4 in Figure 4 and Figure 7 , and correct the exposure conditions of each of the complete exposure units according to the focus energy matrix table, so that the graphic topography and line width of the complete exposure units meet the specifications. In Figure 7After exposure under the initial exposure conditions, all the complete exposure units 101 measured the line width for the process control monitor (PCM) unit. Compared with the specification value of 1.8 μm, the value in the central region of the wafer is larger (> 1.9 μm), and the value in the edge region of the wafer is smaller (< 1.7 μm). In this step, by executing the exposure compensation algorithm, the exposure conditions of each of the complete exposure units are corrected so that the pattern topography and line width of the complete exposure units meet the specifications. Figure 7 and Figure 9 The unit of the line width number in the figure is μm. Specifically, as Figure 4 shown, it is Figure 3 the flowchart of the exposure compensation algorithm in the figure. After the start node, at node 401, the coordinates of the current exposure unit (shot) to be corrected are obtained. At node 402, the parameters of the current exposure unit (such as exposure conditions, line width, and topography) are obtained. At node 403, it is judged whether the pattern topography of the current exposure unit meets the specification requirements. If not, at nodes 404 and 405, the exposure focus is compensated according to the focus energy matrix (FEM) table in sequence and the compensated conditions are saved. At node 406, it is judged whether the pattern line width of the current exposure unit meets the specification requirements. If not, at nodes 407 and 408, the exposure energy is compensated according to the focus energy matrix (FEM) table in sequence and the compensated conditions are saved. If the judgments at nodes 403 and 406 both meet the specification requirements, the current exposure conditions are saved at node 409. For the I-line step-and-repeat projection lithography machine, when a positive photoresist is used, the exposure amount is sufficient, and the focus is the main factor affecting the pattern appearance; when the pattern topography is normal, that is, the sidewall of the structure after photoresist development is vertical, the main factor affecting the line width of the photoresist pattern is the exposure energy. Therefore, generally, the pattern appearance is adjusted by adjusting the exposure focus, and the pattern line width is adjusted by adjusting the exposure energy. The actual pattern line width and the specification line width can be compared with the corresponding line width in the focus energy matrix (FEM) table to obtain the compensation value of the exposure focus or energy required to reach the specification line width. In other embodiments of the present invention, the exposure focus and the exposure energy can also be adjusted simultaneously to adjust the pattern topography or line width. At node 410, it is judged whether the currently processed exposure unit is the last one. If it is the last one, the exposure compensation algorithm process ends; if it is not the last one, at node 411, the coordinates of the next exposure unit to be processed are obtained, and the process loops back to node 402 to perform exposure compensation on the next exposure unit.

[0052] In step 5), please refer to Figure 1 step S5 in Figure 5 and Figure 7 , and correct the exposure conditions of the incomplete exposure units according to the corrected exposure conditions of the complete exposure units adjacent to the incomplete exposure units. AsFigure 7 As shown, due to the absence of the process control monitor (PCM) unit of the incomplete exposure unit 102, the line width of its lithography pattern cannot be directly measured. In this embodiment, through the edge compensation algorithm, the exposure condition of the incomplete exposure unit 102 is corrected according to the corrected exposure condition of the adjacent complete exposure unit 101. Optionally, the method for correcting the exposure condition of the incomplete exposure unit includes: obtaining it by weighted average calculation of multiple exposure conditions of the complete exposure unit adjacent to the incomplete exposure unit; or, when the number of surrounding complete exposure units is small, calculating it through the linear change trend of multiple exposure conditions of multiple complete exposure units from the incomplete exposure unit to the center of the wafer.

[0053] As Figure 5 shown, Figure 3 is the flowchart of the edge compensation algorithm in Figure 7 . After the start node, at node 501, a coordinate list of incomplete exposure units at the edge is obtained, and at node 502, the coordinates of the initial exposure unit are selected from the list. At node 503, the exposure condition information of the complete exposure units around the current incomplete exposure unit is obtained. For example, in Figure 7 , the surrounding complete exposure units of the incomplete exposure unit 102 in the upper right of the wafer are three complete exposure units arranged in the Y direction with line widths of 1.6329μm, 1.6842μm, and 1.6845μm on the left side respectively. At node 504, the exposure condition of the current incomplete exposure unit is calculated through the exposure conditions of the obtained surrounding complete exposure units. For example, the exposure condition of the incomplete exposure unit can be obtained by weighted average calculation. For the incomplete exposure unit 102 in Figure 7 , the weights of weighted average calculation of its left complete exposure unit, upper left complete exposure unit, and lower left complete exposure unit can be set as 0.4:0.3:0.3 respectively. In other embodiments of the present invention, the selection range of the surrounding complete exposure units can also be expanded, and different weights of weighted average calculation can be set according to their distances from the incomplete exposure unit. In addition, in other embodiments of the present invention, it can also be calculated through the linear change trend of multiple exposure conditions of multiple complete exposure units from the incomplete exposure unit to the center of the wafer. For example, in Figure 7 , the line widths of the complete exposure units from the incomplete exposure unit 102 to the center of the wafer on the left side are 1.6842μm, 1.7385μm, 1.7324μm, 1.8361μm, 1.9537μm, and 1.9871μm in sequence. The above complete exposure units pass through Figure 4The exposure compensation algorithm in can obtain the compensation value of the exposure conditions, and by linearly fitting the above exposure conditions, the compensation value of the exposure conditions of the incomplete exposure units can be deduced. At node 505, the exposure conditions after compensation of the current exposure unit are saved, and at node 506, it is judged whether the current exposure unit is the last one. If it is the last one, the current edge compensation algorithm ends; if it is not the last one, at node 507, the coordinates of the next exposure unit are obtained, and it returns to node 503 to continue the edge compensation algorithm for the next exposure unit.

[0054] Through the exposure compensation algorithm and the edge compensation algorithm, the exposure conditions of each complete exposure unit and incomplete exposure unit in the wafer surface can be compensated and calculated respectively to obtain the corrected exposure conditions of each exposure unit. However, if different exposure conditions are to be used for each exposure unit during the lithography process, it will lead to an excessive number of exposure conditions and redundancy, and in actual production, the lithography machine cannot support such a large number of exposure conditions in a single lithography process. Therefore, the exposure conditions with similar parameters must be approximately unified according to partitions, so that the number of exposure conditions used in a single lithography process is reduced to several. This requires, after obtaining the corrected exposure conditions of each exposure unit, using a partitioning algorithm to partition each exposure unit and making the exposure units in the same partition have the same exposure conditions.

[0055] As an example, after obtaining the corrected exposure conditions of multiple said exposure units, the multiple said exposure units are partitioned, and the exposure conditions of each said exposure unit in the same partition are corrected so that each said exposure unit in the same partition has the same exposure condition. As Figure 6 shown, it is Figure 3 the flowchart of the partitioning algorithm in . After the start node, at node 601, the exposure conditions of all exposure units on the wafer are obtained, and at node 602, the evaluation of the exposure conditions is normalized. For example, for the main parameters in the exposure conditions: focal length and energy, different weights are given during the normalization process to obtain the distribution map of the normalized exposure conditions in the wafer surface. At node 603, the distribution of the normalized exposure conditions is fuzzily partitioned so that the exposure conditions with similar values are grouped into the same partition, and the exposure conditions of this partition are determined by calculating the average value, etc. As Figure 8As shown, according to the zoning algorithm, the exposure units within the wafer are divided into five zones. The exposure units labeled with numbers 1 to 5 belong to the first to fifth zones respectively. Each zone has different and unique exposure conditions, and a unified exposure condition is used for the lithography process of the exposure units within the zone. At node 604, the normalized exposure conditions after zoning are denormalized to obtain specific parameters of exposure conditions such as focal length and energy. At node 605, the exposure conditions of all exposure units on the wafer are saved. The lithography process is carried out according to the saved corrected exposure conditions. As Figure 9 shown, it is a distribution diagram of the measured line widths of the in-plane exposure units after the lithography process using the corrected exposure conditions. From Figure 9 it can be seen that after the exposure of the wafer in-plane exposure units using the composite algorithm zoning of this embodiment, the extreme difference of the measured line widths has dropped to 0.04 μm, compared with Figure 7 the extreme difference has decreased significantly, which can greatly improve the stability of the lithography process and ensure the yield of mass-produced products.

[0056] As an example, after obtaining the corrected exposure conditions of the multiple exposure units, it further includes the steps of exposing each of the exposure units using the exposure conditions, and obtaining the graphic morphology and line width of the complete exposure units, so as to correct the exposure conditions of the complete exposure units and the incomplete exposure units again. Through the above negative feedback process, a dynamic cyclic correction of the exposure conditions can be established during the production process of mass-produced products, so that the appearance and line width results of the exposed patterns are stabilized within the specification range. Optionally, during the actual mass production process, during the lithography exposure process of products in different batches, the graphic morphology and line width of the complete exposure units of the previous batch are obtained, and the exposure compensation algorithm, edge compensation algorithm and zoning algorithm of this embodiment are used to correct the exposure conditions of the complete exposure units and the incomplete exposure units, and the exposure conditions are used for the lithography exposure of the next batch of products, so that the lithography process results of the products are continuously stabilized within the set specification range.

[0057] Embodiment 2

[0058] This embodiment provides a wafer exposure system, including:

[0059] A data storage module for storing the focal length energy matrix tables of different products and lithography levels;

[0060] A lithography exposure module that divides multiple exposure units on the surface of the wafer. The exposure units include complete exposure units located in the internal area of the wafer and incomplete exposure units located in the edge area of the wafer. The lithography exposure module performs exposure processing on each exposure unit of the wafer according to the input exposure conditions, and outputs the graphic morphology and line width of the exposure units;

[0061] A data processing module, which is configured to obtain the focal length energy matrix table stored in the data storage module according to the information of the product and the lithography level, correct the exposure conditions of each of the complete exposure units according to the focal length energy matrix table, so that the pattern topography and line width of the complete exposure units meet the specifications, correct the exposure conditions of the incomplete exposure units according to the corrected exposure conditions of the complete exposure units adjacent to the incomplete exposure units, and output the corrected exposure conditions to the lithography exposure module.

[0062] As an example, the wafer exposure system in this embodiment can be used to execute the wafer exposure method in Embodiment 1. The lithography exposure module divides a plurality of exposure units on the surface of the wafer and can perform a lithography process according to the input exposure conditions; the data processing module is connected to the data storage module and the lithography exposure module, can obtain the focal length energy matrix table from the data storage module, and output the corrected exposure conditions to the lithography exposure module. The data processing module can correct the exposure conditions of each of the complete exposure units according to the focal length energy matrix table, so that the pattern topography and line width of the complete exposure units meet the specifications, and correct the exposure conditions of the incomplete exposure units according to the corrected exposure conditions of the complete exposure units adjacent to the incomplete exposure units. The algorithm processing process is as described in Embodiment 1 and will not be elaborated here.

[0063] As an example, after obtaining the corrected exposure conditions of a plurality of the exposure units, the data processing module partitions the plurality of exposure units and corrects the exposure conditions of each of the exposure units in the same partition, so that each of the exposure units in the same partition has the same exposure condition. The partitioning process is as Figure 6 shown in the partitioning algorithm flowchart of Figure 8 to obtain the partitioning result as shown in

[0064] As an example, after obtaining the corrected exposure conditions of a plurality of the exposure units, the data processing module outputs the exposure conditions to expose each of the exposure units to the lithography exposure module, and obtains the pattern topography and line width of the complete exposure units from the lithography exposure module to correct the exposure conditions of the complete exposure units and the incomplete exposure units again. The data processing module can continuously correct the exposure conditions of each of the exposure units by establishing a negative feedback loop, and this negative feedback process is as described in Embodiment 1.

[0065] In summary, the present application provides a wafer exposure method and system. The wafer exposure method includes the following steps: dividing a plurality of exposure units on the surface of the wafer, where the exposure units include complete exposure units located in the internal area of the wafer and incomplete exposure units located in the edge area of the wafer; obtaining a focus energy matrix table of the photolithography layer to be exposed; obtaining the pattern topography and line width of each of the complete exposure units after being exposed under the initial exposure conditions; correcting the exposure conditions of each of the complete exposure units according to the focus energy matrix table to make the pattern topography and line width of the complete exposure units meet the specifications; correcting the exposure conditions of the incomplete exposure units according to the corrected exposure conditions of the complete exposure units adjacent to the incomplete exposure units. By correcting the exposure conditions of the complete exposure units according to their pattern topography and line width, and correcting the exposure conditions of the incomplete exposure units according to the exposure conditions of the complete exposure units adjacent to them, the present application can greatly improve the uniformity of the pattern topography and line width within the wafer surface.

[0066] The above embodiments are only illustrative of the principles and effects of the present application, and are not intended to limit the present application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present application should still be covered by the claims of the present application.

Claims

1. A wafer exposure method, characterized in that, It includes the following steps: Divide multiple exposure units on the surface of the wafer. The exposure units include complete exposure units located in the internal area of the wafer and incomplete exposure units located in the edge area of the wafer; Obtain the focus energy matrix table of the photolithography layer to be exposed; Obtain the pattern topography and line width of each of the complete exposure units after exposure under the initial exposure conditions; Correct the exposure conditions of each of the complete exposure units according to the focus energy matrix table so that the pattern topography and line width of the complete exposure units meet the specifications; Correct the exposure conditions of the incomplete exposure units according to the corrected exposure conditions of the complete exposure units adjacent to the incomplete exposure units. The method for correcting the exposure conditions of the incomplete exposure units includes: performing weighted average calculation on multiple exposure conditions of the complete exposure units adjacent to the incomplete exposure units; 2. The wafer exposure method according to claim 1, wherein After obtaining the corrected exposure conditions of multiple exposure units, partition the multiple exposure units and correct the exposure conditions of each exposure unit in the same partition so that each exposure unit in the same partition has the same exposure conditions; 3. The wafer exposure method according to claim 1, characterized in that, Obtain the pattern topography and line width of the complete exposure units by measuring the process control monitoring units in the complete exposure units; 4. The wafer exposure method according to claim 1, wherein After obtaining the corrected exposure conditions of multiple exposure units, it further includes the step of exposing each exposure unit with the exposure conditions and obtaining the pattern topography and line width of the complete exposure units to correct the exposure conditions of the complete exposure units and the incomplete exposure units again; 5. The wafer exposure method according to claim 4, wherein During the photolithography exposure process of products in different batches, obtain the pattern topography and line width of the complete exposure units of the previous batch, correct the exposure conditions of the complete exposure units and the incomplete exposure units, and use the exposure conditions for the photolithography exposure of the next batch of products; 6. The wafer exposure method according to claim 1, wherein The method for obtaining the focus energy matrix table of the photolithography layer to be exposed includes: establishing a focus energy matrix table library for different products and different photolithography levels, and retrieving the focus energy matrix table according to the product and photolithography level information; 7. A wafer exposure system, characterized in that, It includes: A data storage module for storing the focus energy matrix tables of different products and photolithography levels; A photolithography exposure module that divides multiple exposure units on the surface of the wafer. The exposure units include complete exposure units located in the internal area of the wafer and incomplete exposure units located in the edge area of the wafer. The photolithography exposure module performs exposure processing on each exposure unit of the wafer according to the input exposure conditions and outputs the pattern topography and line width of the exposure units; A data processing module, which is used to obtain the focal length energy matrix table stored in the data storage module according to the information of the product and the lithography level, correct the exposure conditions of each of the complete exposure units according to the focal length energy matrix table, so that the pattern topography and line width of the complete exposure units meet the specifications, perform weighted average calculation according to the corrected exposure conditions of the complete exposure units adjacent to the incomplete exposure units to correct the exposure conditions of the incomplete exposure units, and output the corrected exposure conditions to the lithography exposure module.

8. The wafer exposure system according to claim 7, wherein After obtaining the corrected exposure conditions of multiple exposure units, the data processing module partitions the multiple exposure units and corrects the exposure conditions of each exposure unit in the same partition, so that each exposure unit in the same partition has the same exposure condition.

9. The wafer exposure system according to claim 7, wherein After obtaining the corrected exposure conditions of multiple exposure units, the data processing module outputs the exposure conditions to expose each exposure unit to the lithography exposure module, and obtains the pattern topography and line width of the complete exposure units from the lithography exposure module to correct the exposure conditions of the complete exposure units and the incomplete exposure units again.

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