Embedded processor architecture

Abstract

An embedded processor architecture is provided in an embodiment of the present disclosure, belonging to the technical field of communication architectures. It includes a first DSP processing module and a second DSP processing module that are mirror-integrated within a physical single box, as well as a high-speed fault-tolerant bus application layer and a high-speed fault-tolerant bus protocol layer. The first DSP processing module and the second DSP processing module form a dual channel. The two channels are strongly independent and weakly coupled with each other. To save space resources, the dual channels need to be integrated inside one box, and the operations of the two channels do not affect each other, and the system interface signals are independent of each other. Even if the system connector of one channel is disconnected or not connected, it will not affect the normal operation of the other channel, and single-point fault sources are eliminated as much as possible from the outside to the inside.

Description

Technical Field

[0001] The present invention belongs to the technical field of the architecture of airborne computers, and particularly relates to an architecture of an embedded processor. Background Art

[0002] For an airborne fault-tolerant computer system with a dual-channel architecture, a reliability working model of parallel or serial operation is usually adopted between the internal dual channels. Among them, "parallel" means that the two channels are in a backup relationship, that is, when one channel fails, the other channel continues to maintain operation to improve the reliable operation characteristics of the entire computer system. And "serial" means that the two channels are in a monitoring operation relationship, that is, one channel in the computer is used as the main control channel and the other channel is used for monitoring. When any one of the two channels fails or a fault is detected, the external control output of the entire computer is cut off to ensure the safe operation characteristics of the entire computer system. Design a structural framework belonging to the airborne computer system for data interaction between systems. Summary of the Invention

[0003] In view of this, an architecture of an embedded processor provided by an embodiment of the present disclosure is a new structural design solution. The inside of its single box body is composed of dual channels, and the dual channels are strongly independent and weakly coupled with each other, and single-point fault sources are eliminated as much as possible. At the same time, it supports data communication with the communication system network through a shared high-speed fault-tolerant bus.

[0004] An architecture of an embedded processor, which mirror-integrates a first DSP processing module and a second DSP processing module, as well as a high-speed fault-tolerant bus application layer and a high-speed fault-tolerant bus protocol layer in a physical single box body, wherein:

[0005] The first DSP processing module and the second DSP processing module respectively receive a plurality of external system parameters, process them and give feedback;

[0006] The high-speed fault-tolerant bus application layer is used to obtain the data transmitted by the first DSP processing module and the second DSP processing module, and after packing and converting the data bus protocol data, send it to the high-speed fault-tolerant bus protocol layer;

[0007] The high-speed fault-tolerant bus protocol layer is used to process the protocol of the link layer and output data outward in a dual-redundancy manner.

[0008] The interior of the single cabinet consists of two channels. The two channels are strongly independent and weakly coupled with each other, and single-point failure sources are eliminated as much as possible. At the same time, it supports data communication with the communication system network through a shared high-speed fault-tolerant bus. Different from the general "series" or "parallel" dual-redundancy computer architecture, the two channels are strongly independent and weakly coupled with each other. To save space resources, the two channels need to be integrated inside one cabinet, and the operation of the two channels does not affect each other, and the system interface signals are independent of each other (even if the system connector of one channel is disconnected or not connected, it will not affect the normal operation of the other channel). Single-point failure sources are eliminated as much as possible from the outside to the inside. At the same time, both channels in the computer can realize data communication with the communication system network through a shared high-speed fault-tolerant bus. Description of the Drawings

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0010] Figure 1 is the framework diagram of the present invention;

[0011] Figure 2 is the schematic diagram of the A data channel. Detailed Embodiments

[0012] The embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0013] The following specific examples illustrate the implementation manners of the present disclosure. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. The present disclosure can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts belong to the scope of protection of the present disclosure.

[0014] It should be noted that the following description pertains to various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on this disclosure, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of the aspects set forth herein can be used to implement an apparatus and / or practice a method. Additionally, this apparatus and / or method can be implemented using other structures and / or functionality in addition to one or more of the aspects described herein.

[0015] The embedded processor architecture of the present invention, as Figure 1 shown, integrally mirrors in a physical single enclosure a first DSP processing module (corresponding to the A data channel in the figure) and a second DSP processing module (corresponding to the B data channel in the figure), as well as a high-speed fault-tolerant bus application layer and a high-speed fault-tolerant bus protocol layer, wherein:

[0016] The first DSP processing module and the second DSP processing module respectively receive a plurality of external system parameters, and process and provide feedback.

[0017] The high-speed fault-tolerant bus application layer is used to obtain the data transmitted by the first DSP processing module and the second DSP processing module, and after packing and converting the data bus protocol data, send it to the high-speed fault-tolerant bus protocol layer.

[0018] The high-speed fault-tolerant bus protocol layer is used to process the protocol of the link layer and output data outward in a dual-redundancy manner.

[0019] As a specific implementation manner provided in this case, the first DSP processing module and the second DSP processing module are respectively provided with a power supply (corresponding to the +5V power supplies on the left and right sides in the figure). The power supplies are both provided with overcurrent protection circuits. The power supply of the second DSP processing module serves as a hot backup for the power supply of the first DSP processing module. After the external system is powered on, the power supply of the first DSP processing module preferentially powers the high-speed fault-tolerant bus application layer through a set selection switch, and the power supply of the second DSP processing module powers the high-speed fault-tolerant bus protocol layer through the selection switch. When the power supply of the first DSP processing module fails in power supply, the selection switch is controlled to switch, and the power supply of the second DSP processing module powers the high-speed fault-tolerant bus application layer and the high-speed fault-tolerant bus protocol layer to maintain normal power supply.

[0020] It should be noted that the +5V power supply, as a special power supply, only powers the high-speed fault-tolerant bus application layer and / or the high-speed fault-tolerant bus protocol layer. Additionally, +15V and -15V power supplies are respectively set on the left and right sides of the figure. Other modules of the first DSP processing module and the second DSP processing module freely select the +15V power supply and the -15V power supply as the power supply according to their own models, and the specific form is not limited. After the externally input voltage is filtered, it is connected to power supply modules of different models.

[0021] As a specific implementation manner provided in this case, the first DSP processing module and the second DSP processing module are respectively provided with an inter-channel interaction module. Data is exchanged between the two inter-channel interaction modules, and at least status indication, data synchronization, and data transmission are performed.

[0022] As a specific implementation manner provided in this case, as Figure 2 shown, the first DSP processing module includes a first DSP processor, a control system high-speed bus protocol node, an integrated monitoring module, a first data exchange pool, a parallel expansion bus, and multiple data interaction modules, where:

[0023] The first DSP processor exchanges data with the integrated monitoring module, the first data exchange pool, and multiple data interaction modules through the parallel expansion bus, and is used for data reading, processing, and instruction sending;

[0024] The first data exchange pool transmits the processing information of the first DSP processor through the parallel expansion bus, and exchanges data with the high-speed fault-tolerant bus application layer through the high-speed internal bus. That is, the data received by the first DSP processor and the corresponding processing results are both fed back to the first data exchange pool, and then the first data exchange pool transmits to the high-speed fault-tolerant bus application layer and finally outputs to external devices;

[0025] The integrated monitoring module is used to monitor the working status of the configured auxiliary modules;

[0026] The control system high-speed bus protocol node is connected to the control system high-speed bus of the external device, and is connected to the parallel expansion bus through the high-speed internal bus for protocol conversion of the data interaction method (converted into data that the control system high-speed bus protocol node can recognize through the "high-speed internal bus");

[0027] Multiple data interaction modules receive and transmit signals or data by configuring different signal lines.

[0028] It should be noted that the structure and data interaction method of the second DSP processor are the same as those of the first DSP processor, and they are set in a mirror-symmetric manner. Only the first DSP processor is introduced in this text, and the structure of the second DSP processor will not be elaborated.

[0029] As a specific embodiment provided in this case, it further includes a strobe switch, an isolation drive, and a D / A converter, the comprehensive monitoring module and multiple power modules included in the first DSP processing module, the comprehensive monitoring module includes a watchdog circuit monitoring module, a channel ID module, and an LRU_ID module, and each power module corresponds to a data interaction module, where:

[0030] The comprehensive monitoring module monitors the working states of the watchdog circuit, the channel ID module, the LRU_ID, and multiple power modules in real time. The LRU_ID module is used for identifying the state of the LRU_ID input signal. The comprehensive monitoring module is connected to the strobe switch. When the watchdog circuit, the channel ID module, or multiple power modules are abnormal, the first DSP processor sends a signal and after being converted by the D / A converter, it is input to the isolation drive. The comprehensive monitoring module controls the strobe switch to perform analog quantity output to monitor whether monitoring information is sent, and the action result of the strobe switch is fed back.

[0031] As a specific embodiment provided in this case, multiple data interaction modules include a discrete input / output module, an HB6096 input / output module, and an RS422S input / output module, and all communicate with the first DSP processor, where:

[0032] The discrete input / output module includes an isolation conversion module, a drive output module, and a first internal bus isolator. The isolation conversion module and the drive output module are respectively connected to the first internal bus isolator. When discrete quantities are input, they are processed by the isolation conversion and then in an isolation mode. When the first DSP processor accesses, the first internal bus isolator is opened. When the first internal bus isolator is opened, the isolation conversion module is also opened, and only then can the data of the isolation conversion module enter the first DSP processor through the parallel expansion bus;

[0033] When discrete quantities are output, they are first input to the first internal bus isolator and then to the drive output, and the drive output performs the output of discrete quantities. That is, when the first DSP processor transmits the processing result, the first internal bus isolator is opened, the processing result is input to the drive output module, and then output; the first internal bus isolator protects the parallel expansion bus from the influence of external bus interface fault signals;

[0034] The RS422S input / output module includes a second internal bus isolator, a first data buffer module, a serial conversion module, and a first terminal matching, where: the serial conversion module is used for the conversion of serial and parallel data (when input, serial to parallel; when output, parallel to serial), and the first data buffer module is used for the conversion of input or output data; the principle of the second internal bus isolator is the same as that of the first internal bus isolator, and it is only opened when the first DSP processor initiates an access or sends a processing result, to protect the parallel expansion bus;

[0035] The HB6096 input / output module includes a third internal bus isolator, a second data buffer module, a serial protocol conversion module (for converting the serial data formats of input and output data), and a second terminal matching. When the data corresponding to the HB6096 bus is input or output, the third internal bus isolator protects the parallel expansion bus.

[0036] As a specific implementation provided in this case, further, an AC reference power supply module is provided to process the filtered voltage and output AC reference data. It also includes a displacement monitoring and conversion module, a proportional adjustment module, and an A / D converter. The displacement monitoring and conversion module and the proportional adjustment module are respectively connected to the A / D converter.

[0037] The displacement monitoring and conversion module receives an external AC reference (converting AC voltage to DC voltage), and after being connected and converted by the A / D converter (converted into an analog signal), it is sent to the parallel expansion bus, then to the first DSP for processing, and then transmitted to the first data exchange pool.

[0038] The proportional adjustment module receives the analog input signal transmitted from an external device, adjusts it according to a preset ratio, then inputs it to the A / D converter for conversion, and then inputs it to the parallel expansion bus.

[0039] As a specific implementation provided in this case, the external input voltage is 28V, and after filtering, it supplies power to each power module.

[0040] 1. Functionally symmetric A and B channels are integrated within a physical single box.

[0041] 2. Design with strong independence and extremely weak coupling characteristics between the two channels.

[0042] 3. Eliminate single-point fault sources from the outside to the inside for the two channels.

[0043] 4. The core DSP processing functional circuit adopts a non-equivalent design for different communication buses.

[0044] 5. The two channels support data communication with the communication system network through a shared high-speed fault-tolerant bus.

[0045] Its single box is internally composed of two channels. The two channels are strongly independent and weakly coupled with each other, and single-point fault sources are eliminated as much as possible. At the same time, it supports data communication with the communication system network through a shared high-speed fault-tolerant bus. The detailed content is as follows.

[0046] 1. A physical single mounting housing, and two functionally symmetric functional channels, namely channel A and channel B, are integrated within the single physical housing, as shown in the attached drawings.

[0047] 2. Channels A and B are independently designed from the outside to the inside. The system signals and power supplies for input and output are all independent of each other. Each uses an independent connector to provide a physical signal connection path. Channels A and B are completely physically isolated at the physical signal layer. The signals of each channel are divided into 3 categories, and each category uses 3 different connectors to provide physical access. The +28V power supply signal uses an independent power supply connector; system signal (including: output AC reference, displacement sensor input, analog input, RS422 input, RS422 output, HB6096 input, HB6096 output, discrete input, discrete output, analog output, LRU_ID) connector, control system high-speed bus connector;

[0048] 3. The internal functional components of Channels A and B are the same and independent. The system electrical signals of each channel are cross-linked with the internal relevant functional circuits after passing through the "lightning protection layer" function, as follows:

[0049] a. The +28V power supply is connected to the secondary power generation circuits such as the AC reference source (with over-current and over-voltage protection functions), +15V (with over-current and over-voltage protection functions), -15V (with over-current and over-voltage protection functions), and +5V (with over-current and over-voltage protection functions) respectively after "filtering"; the AC signal generated by the secondary power supply of the AC reference source is output to the "displacement monitoring and conversion" functional circuit and is also output externally after passing through the "lightning protection layer";

[0050] b. The input signal of the displacement sensor is connected to the "displacement monitoring and conversion" functional circuit after passing through the "lightning protection layer", and is converted into a DC signal and then output to connect to the "A / D conversion" functional circuit;

[0051] c. The analog input signal is connected to the "ratio adjustment" circuit after passing through the "lightning protection layer", and the "ratio adjustment" circuit outputs the processed DC analog signal to connect to the "A / D conversion" circuit;

[0052] d. The RS422 input signal is converted into a parallel signal through the "terminal matching 1" after passing through the "lightning protection layer" and then output to the "data buffer 1" function through the "serial conversion" function;

[0053] e. The RS422 signal to be sent is output from the "data buffer 1" function, converted into a serial signal through the "serial conversion" function, and then output through the "terminal matching 1" through the lightning protection layer;

[0054] f. The HB6096 input signal is converted into a parallel signal through the "terminal matching 2" after passing through the "lightning protection layer" and then output to the "data buffer 2" function through the "protocol conversion" function;

[0055] g. The output signal of HB6096 to be sent is output by the "Data Buffer 2" function, then converted into a serial signal through the "Protocol Conversion" function, and then output through the "Terminal Matching 2" and the "Lightning Protection Layer".

[0056] h. The discrete input signal passes through the lightning protection layer, is output to the internal bus isolation after isolation conversion.

[0057] i. The discrete output signal to be output is output after being driven by the internal bus isolation connection and passing through the lightning protection layer.

[0058] j. The "D / A Conversion" converts the parallel digital quantity into a DC analog signal, then connects to control the "Strobe Switch" through the "Isolation Drive". The signal after the "Strobe Switch" passes through the "Lightning Protection Layer" to achieve analog output.

[0059] k. The whole machine serial number information LRU_ID signal of the processor in the control system is input to the "LRU_ID" monitoring part in the "Comprehensive Monitoring" function through the "Lightning Protection Layer" to realize the identification of the validity of the LRU_ID signal.

[0060] l. The result signal of the "Comprehensive Monitoring" function (covering the monitoring of LRU_ID, watchdog, power supply, channel ID) is connected to the "Strobe Switch" to realize the control of analog output.

[0061] 4. The "Core DSP Processing Function" realizes data interaction and control with functions such as "A / D Conversion", "Internal Bus Isolation", "D / A Conversion", "Comprehensive Monitoring", "Data Exchange Pool", "Transfer to High-Speed Internal Bus", and "Inter-Channel Interaction" through the parallel expansion bus of the processor.

[0062] 5. Loose coupling connection between channels. The "Inter-Channel Interaction" functions inside channels A and B are connected through two-way data interaction, synchronization, and status mutual indication to realize the transmission of data information and status between the two channels, but do not participate in hard logic monitoring.

[0063] 6. The core DSP processing function circuit adopts a non-equivalent design for different communication buses. It is designed as the master device end for communication with the control system high-speed bus, and as the slave device end for communication with the high-speed fault-tolerant bus.

[0064] 7. The "Transfer to High-Speed Internal Bus" function is connected to the "Control System High-Speed Bus Protocol Node". The "Transfer to High-Speed Internal Bus" function is the master end of this section of high-speed internal bus communication, and the "Control System High-Speed Bus Protocol Node" is the slave node end of this section of high-speed internal bus communication.

[0065] 8. The "main processing function of the application layer of the high-speed fault-tolerant bus" serves as the master node of the three groups of high-speed internal bus communication buses, and is interconnected with the "data exchange pool" of Channel A, the "data exchange pool" of Channel B, and the "function of the high-speed fault-tolerant bus protocol layer" through the high-speed internal bus, enabling peer-to-peer communication between Channels A and B with avionics network devices through the high-speed fault-tolerant bus;

[0066] 9. The A port and B port of the dual-redundancy communication bus of the high-speed fault-tolerant bus respectively use independent connectors to achieve physical docking with the outside, supporting non-unidirectional external wiring;

[0067] 10. The "+5V" secondary power supplies in Channels A and B are both connected to the "switch". The function of the "switch" ensures that when any one of the "+5V" secondary power supplies in Channels A and B is normal, +5V power supply can be provided to the "main processing function of the application layer of the high-speed fault-tolerant bus" and the "function of the high-speed fault-tolerant bus protocol layer".

[0068] It can be seen that whether in "parallel" or "series", the two channels are operating in a coupled relationship, that is, the state of one channel will affect the working mode of the other channel. At the same time, in the external system signal distribution, it is also divided into two and distributed to the two channels. Obviously, the two channels are not completely independent. In an airborne control system, a completely independent dual-channel computer system is also required. To save space resources, the dual channels need to be integrated inside one box, and the operation of the two channels does not affect each other, and the system interface signals are independent of each other (even if the system connector of one channel is disconnected or not connected, it will not affect the normal operation of the other channel). At the same time, both dual channels in the computer can communicate with the airborne avionics system network through the same high-speed fault-tolerant bus. Therefore, it is necessary to design a new dual-channel computer architecture with mutual independence and extremely weak coupling to meet the usage requirements of the airborne system.

[0069] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present disclosure should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An embedded processor architecture, characterized in that, The first DSP processing module and the second DSP processing module are mirror-integrated in a physical single box, as well as a high-speed fault-tolerant bus application layer and a high-speed fault-tolerant bus protocol layer, where: The first DSP processing module and the second DSP processing module respectively receive multiple external system parameters, and perform processing and feedback; The high-speed fault-tolerant bus application layer is used to obtain the data transmitted by the first DSP processing module and the second DSP processing module, and after packing and converting the data bus protocol data, send it to the high-speed fault-tolerant bus protocol layer; The high-speed fault-tolerant bus protocol layer is used to process the protocol of the link layer and output data externally in a dual-redundancy manner; The first DSP processing module and the second DSP processing module are respectively provided with an inter-channel interaction module, and data interaction occurs between the two inter-channel interaction modules, at least for status mutual indication, data synchronization and data mutual transmission. The first DSP processing module includes a first DSP processor, a control system high-speed bus protocol node, an integrated monitoring module, a first data exchange pool, a parallel expansion bus, and multiple data interaction modules and a watchdog circuit, where: The first DSP processor interacts with the integrated monitoring module, the first data exchange pool and multiple data interaction modules through the parallel expansion bus, and is used for data reading, processing and instruction sending; The first data exchange pool transmits the processing information of the first DSP processor through the parallel expansion bus, and interacts with the high-speed fault-tolerant bus application layer through the high-speed internal bus; The integrated monitoring module is used to monitor the working status of the configured auxiliary modules; The control system high-speed bus protocol node is connected to the control system high-speed bus of the external device, and is connected to the parallel expansion bus through the high-speed internal bus to perform protocol conversion of the data interaction method; Multiple data interaction modules receive and transmit signals or data by configuring different signal lines.

2. The embedded processor architecture according to claim 1, characterized in that, The first DSP processing module and the second DSP processing module are respectively provided with a power supply, and the power supply is provided with an overcurrent protection circuit. The power supply of the second DSP processing module is used as the hot backup of the power supply of the first DSP processing module. After the external system is powered on, the power supply of the first DSP processing module preferentially powers the high-speed fault-tolerant bus application layer through the set selection switch, and the power supply of the second DSP processing module powers the high-speed fault-tolerant bus protocol layer through the selection switch. When the power supply of the first DSP processing module fails in power supply, the selection switch is controlled to switch, and the power supply of the second DSP processing module powers the high-speed fault-tolerant bus application layer and the high-speed fault-tolerant bus protocol layer to maintain normal power supply.

3. The embedded processor architecture according to claim 2, wherein The first DSP processing module further includes a gating switch, an isolation drive module, a D / A converter and multiple power modules. The integrated monitoring module includes a watchdog circuit monitoring module, a channel ID module, and an LRU_ID. Each power module corresponds to a data interaction module. The gating switch is respectively connected to the isolation drive module and the integrated monitoring module, where: The comprehensive monitoring module monitors the working states of the watchdog circuit, channel ID module, LRU_ID, and multiple power modules in real time. When the watchdog circuit, channel ID module, or multiple power modules are abnormal, it sends a signal to the first DSP processor. The first DSP processor processes the data. After the processing result is converted by the D / A converter, it is input to the isolation drive. The comprehensive monitoring module controls the gating switch to perform analog output to monitor whether monitoring information is sent.

4. The embedded processor architecture according to claim 3, characterized in that, The multiple data interaction modules include discrete input / output modules, HB6096 input / output modules, and RS422S input / output modules, and all communicate with the first DSP processor, where: The discrete input / output module includes isolation conversion, drive output, and a first internal bus isolator. The isolation conversion and drive output are respectively connected to the first internal bus isolator. When discrete quantities are input, they are processed by the isolation conversion and then input to the internal bus isolator. When discrete quantities are output, they are first input to the first internal bus isolator and then input to the drive output, and the drive output performs the output of discrete quantities. The first internal bus isolator protects the parallel expansion bus from the influence of external bus interface fault signals. The RS422S input / output module includes a second internal bus isolator, a first data buffer module, a serial conversion module, and a first terminal matching, where: the serial conversion module is used for the conversion between serial and parallel data, and the first data buffer module is used for the conversion of input or output data. The HB6096 input / output module includes a third internal bus isolator, a second data buffer module, a serial protocol conversion module, and a second terminal matching. When the data corresponding to the HB6096 bus is input or output, the third internal bus isolator protects the parallel expansion bus.

5. The embedded processor architecture according to claim 4, wherein It further includes a displacement monitoring and conversion module, a proportional adjustment module, and an A / D converter. The displacement monitoring and conversion module and the proportional adjustment module are respectively connected to the A / D converter. The displacement monitoring and conversion module receives the internal AC reference voltage and converts it into a DC voltage, which is connected and converted by the A / D converter and then transmitted to the parallel expansion bus. The proportional adjustment module receives external analog input, adjusts it according to a preset ratio, inputs it to the A / D converter for conversion, and then inputs it to the parallel expansion bus.

6. The embedded processor architecture according to claim 5, wherein, The external input voltage is 28V, and after filtering, it supplies power to each power module.

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