An FPGA Technology Mapping Algorithm Based on Logic Gate Decomposition

Abstract

The present invention belongs to the technical field of FPGA integrated electronic design automation, and specifically relates to an FPGA technology mapping algorithm based on logic gate decomposition. In the process of technology mapping, the algorithm of the present invention selectively performs logic gate decomposition to optimize the area and timing performance of the synthesized circuit; the algorithm simultaneously executes wide logic gate decomposition and K-cut enumeration mapping; when performing mapping, it dynamically generates the decomposition form of wide logic gates according to the mapping requirements, avoiding the contradiction between the number of decompositions and the optimization effect caused by pre-logic gate decomposition, and achieving the purpose of shortening the calculation time and obtaining better optimization effects at the same time. The present invention is applicable to both the development of FPGA integrated EDA tools and the development of EDA tools for FPGA hardware simulation systems. The idea of logic gate decomposition and technology mapping of the present invention is also applicable to the development of ASIC technology mapping algorithms and EDA tools.

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGA integrated Electronic Design Automation (EDA), and specifically relates to an FPGA technology mapping algorithm based on logic gate decomposition, aiming to improve the area and timing optimization effects of existing algorithms. Background Art

[0002] FPGA technology mapping is to map a general logic gate (AND, OR, NOT, and other complex logic gates) netlist into a K-LUT netlist. In modern FPGAs, K is generally 6. Traditional technology mapping algorithms first decompose multi-input logic gates into 2-input gates and then perform technology mapping. This method may lead to a decrease in the area and timing of technology mapping due to inappropriate logic gate decomposition.

[0003] Figure 1 (a) is an 8-bit signal comparator composed of 8 exclusive-OR gates and an 8-input OR gate. The conventional solution needs to first decompose this 8-input OR gate into 7 2-input OR gates and then perform technology mapping to obtain a 3-level logic of 4 LUTs ( Figure 1 (b)). However, if the decomposition method as shown in Figure 1 (c) is adopted, a 2-level logic of 3 LUTs can be obtained.

[0004] Current technology mapping algorithms are all affected by the logic gate decomposition scheme, and this situation is also called structural bias.

[0005] For algorithms that combine logic gate decomposition and technology mapping, those currently published include: the ABC choice algorithm [1] and the SLDMap algorithm [2]. The common point of their algorithms is to pre-generate some logic gate decomposition schemes and then let the technology mapping algorithm select an optimized decomposition scheme. However, there is a contradiction between the number of alternative schemes and the mapping effect in their methods.

[0006] The present invention proposes an FPGA technology mapping algorithm that combines logic gate decomposition technology to eliminate the structural bias problem of conventional solutions and obtain a more optimized technology mapping result. The present invention simultaneously performs logic gate decomposition and technology mapping, and can selectively generate logic gate decomposition schemes with good optimization effects, thereby ensuring the optimization effect of the technology mapping algorithm.

[0007] Explanation of Proprietary Terms:

[0008] FPGA: Field Programmable Gate Array chip;

[0009] FPGA technology mapping: Mapping a netlist composed of logic gates into a netlist composed of LUTs;

[0010] Cut: Cutting; each logic gate and all its fan-in nodes form a multi-input, single-output netlist. A cut is a cut that completely separates this output root node from the input nodes;

[0011] Wide-cut: A cut with more than K inputs. For an FPGA composed of 6-LUTs, K is 6;

[0012] Wide-gate: AND or OR logic gates with more than K inputs. Summary of the Invention

[0013] The object of the present invention is to provide an FPGA technology mapping algorithm based on logic gate decomposition to optimize the area and timing performance of the synthesized circuit, which can be applied to the development of EDA tools for FPGA synthesis and also to the development of EDA tools for FPGA hardware simulation systems.

[0014] The FPGA technology mapping algorithm based on logic gate decomposition proposed by the present invention selectively performs logic gate decomposition during the process of technology mapping to optimize the area and timing performance of the synthesized circuit, thus eliminating the need to pre-generate a large decomposition set to ensure the optimization quality. The algorithm flow is shown in Figure 2 as follows. The specific steps are:

[0015] Traverse all logic gates from the netlist input node PI to the output node PO in topological order;

[0016] (1) For 2-input logic gates, use the traditional node cut enumeration algorithm [3];

[0017] (2) For multi-input AND or OR logic gates, first, enumerate the wide-cuts of this logic gate according to the multi-input logic gate cut enumeration algorithm (key technology 1), and then use the logic gate decomposition algorithm (key technology 2) to form the logic decomposition schemes of these wide-cuts and the technology mapping schemes of K-LUTs, so as to obtain the area and timing evaluations of these wide-cuts; then, use the traditional cut sorting method [3] to retain several (usually 10 - 30) cuts with better area and timing; these retained cuts are used both for generating subsequent mapping schemes and for cut enumeration of the fan-out logic gates of this logic gate;

[0018] (3) After the cutting enumeration of all logic gates is completed, a technology mapping scheme is generated through the cutting selection algorithm (Key Technology 3); the cutting selection algorithm selects the root nodes of the LUTs to be generated and the corresponding cuts from the output nodes PO to the input nodes PI: First, all PO nodes are marked as LUT root nodes; then, for each LUT root node, select one of its best cuts to form an LUT, and mark the inputs of this cut as LUT root nodes. This process will continue until all the marked LUT root nodes are traversed. At this time, the corresponding set of selected cuts constitutes a complete technology mapping result.

[0019] The following further details three key technologies in the proposed algorithm flow: the multi-input logic gate cutting enumeration algorithm, the logic gate decomposition algorithm, and the cutting selection algorithm.

[0020] (1) Multi-input logic gate cutting enumeration algorithm

[0021] Suppose a logic gate has W inputs, and each input has C cuts. Then the direct enumeration method needs to enumerate C W cuts. The present invention proposes a cutting enumeration algorithm with a complexity of C 2 :

[0022] Enumerate by considering the cuts of each input gate in turn. First, generate an empty cutting queue L. Then, merge L with the cuts of the input gate in turn to generate a queue Ltemp of partial cuts. Then, set L to Ltemp and merge it with the cuts of the next input until all input logic gates are processed. For partial cuts, the area calculation formula is (1):

[0023]

[0024] The pseudocode of this algorithm is shown in the appendix.

[0025] (2) Logic gate decomposition algorithm

[0026] For a wide cut with more than K inputs, the multi-input logic gate it represents must be decomposed to form a logic decomposition and technology mapping scheme composed of K-cuts. The present invention uses the bin-packing algorithm to perform logic gate decomposition and technology mapping.

[0027] Figure 3 (a) is Figure 1 a wide cut formed by an example. Figure 3 (b) is the result of a bin-packing algorithm, and its corresponding technology mapping result is Figure 3 (c). The logic gate decomposition it represents is Figure 3 (d).

[0028] The bin packing algorithm is to use a fixed-size box to pack some small boxes. The requirement is that the total volume of these small boxes cannot exceed the volume of the large box, and at the same time, use as few large boxes as possible to pack these small boxes. A commonly used algorithm is to sort these small boxes from large to small, and then select the current largest small box to be packed in the current large box each time. If the large box cannot hold this small box, a new large box is used to pack it. For the detailed algorithm, please refer to [4].

[0029] Now, the method for evaluating the width cut area after bin packing is introduced. Suppose the set of these small boxes is {cut i}, and their areas are fanout i is the fanout number of the i-th input. Suppose a cut is the number of large boxes required by the bin packing algorithm. The area evaluation formula for the width cut is (2). In this way, all the width cuts of a logic gate can be evaluated and sorted, and then several cuts with good optimization effects are retained, usually 10 to 30. The rest of the cuts are no longer retained.

[0030]

[0031] where, i-thinput represents the i-th fan-in of the wide logic gate.

[0032] (3) Cut Selection Algorithm

[0033] After the enumeration is completed, the cut selection of the entire netlist will be performed and finally the LUT netlist will be generated. Its basic steps are as follows: first, mark the output node PO of the netlist as the LUT root node, and then traverse the netlist from PO to the netlist input node PI in reverse topological order. For each LUT root node, select the best cut, and at the same time, mark the input node of the selected cut as the LUT root node. This process continues until all LUT root nodes are visited.

[0034] In the present invention, the cut selection algorithm adopts a multi-iteration algorithm to improve the area optimization effect. First, assign a variable m i to each node, representing the area weight of this node. The m i of a node marked as the LUT root node is 0, otherwise it is 1. The new cut selection area calculation formula is (3):

[0035]

[0036] The proposed algorithm will calculate the actual cost of the cut of the LUT root node according to the above formula, and select the cut with the minimum cost to form the final mapping solution. The LUT root nodes marked in the last iteration and the corresponding selected cuts constitute the result of an optimized technology mapping.

[0037] The characteristics of the algorithm of the present invention lie in simultaneously performing wide logic gate decomposition and K-cut enumeration mapping. Different from the previous algorithms (ABC-choice 【1】, SLDMap 【2】) that generate wide gate decomposition choices in advance, the proposed algorithm dynamically generates the decomposition forms of wide logic gates according to the mapping needs during mapping, avoiding the contradiction between the number of decompositions and the optimization effect caused by pre-logic gate decomposition, and achieving the purpose of shortening the calculation time and obtaining better optimization effects at the same time. If the algorithms of 【1】 and 【2】 generate a large number of logic gate decomposition schemes, it will lead to excessive memory and long running time of the algorithm. Reducing the decomposition schemes will affect the optimization effect. The patent of the present invention can reduce the time and space complexity of the algorithm while achieving better optimization effects. The present invention is applicable to both the development of FPGA synthesis EDA tools and the development of FPGA hardware simulation system EDA tools. The idea of logic gate decomposition and technology mapping of the present invention is also applicable to the algorithms and EDA tool development of ASIC technology mapping. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is for the relationship between logic gate decomposition and technology mapping.

[0039] Figure 2 It is the algorithm flowchart of the combination of logic gate decomposition and technology mapping of the present invention.

[0040] Figure 3 It is a logic gate decomposition method. DETAILED IMPLEMENTATION MANNER

[0041] The algorithm of the present invention synthesizes a gate-level logic netlist into an FPGA logic netlist composed of K-LUTs through technology mapping. The algorithm of the present invention corresponds to the "cut enumeration and gate decomposition" module. For a netlist composed of input general AND and OR logic gates, we first merge the connected AND and OR logic gates to form multi-input AND and OR logic gates. Then, we first judge whether each logic gate in this logic netlist is a 2-input or 1-input. If it is such a 2-input logic netlist, we adopt the technology mapping algorithm of 【3】. Otherwise, we adopt the technology mapping algorithm combining logic gate decomposition proposed by the present invention. The specific algorithm steps are as follows: perform cut enumeration on all logic gates in topological order. For multi-input logic gates, use wide cut enumeration Sanofi. While enumerating, calculate the area and timing information of each cut, and delete some cuts with poor performance. After enumerating the cuts of all logic gates, we then find the root nodes of the LUTs and the corresponding cuts of the LUTs in topological order from P0 to PI. Finally, generate an FPGA logic netlist composed of LUTs for subsequent placement and routing with all the selected cuts.

[0042] Based on the above algorithm description, we implemented the proposed algorithm in the C++ programming language. Based on a set of test benchmarks consisting of circuits generated by the open-source circuit benchmark EPFL and high-level synthesis, the proposed algorithm was compared with the technology mapping algorithm of the current state-of-the-art open-source logic synthesis tool ABC [5]. The results are listed in Tables 1 and 2 (performing technology mapping for area optimization and timing optimization respectively). In the ABC-LS column in the table is the result of the ABC algorithm, and ABC-LS+&satlut is the effect after further optimizing the ABC mapping result by adding SAT-based remaping.

[0043] Table 1 shows the result comparison for area optimization. The algorithm of the present invention has an improvement of 12.4%.

[0044] Table 1:Area-oriented mapping results of ABC lossless synthesis and AGDMap for K=6.

[0045]

[0046] Table 2 shows the result comparison for timing optimization. On the premise of achieving the same timing effect, the algorithm of the present invention further reduces the area by 9.2%.

[0047] Table 2:Delay-oriented mapping results of ABC lossless synthesis and AGDMap for K=6.

[0048]

[0049] The above specific implementation manners are specific supports for the combination of logic gate decomposition and technology mapping proposed by the present invention, and the protection scope of the present invention cannot be limited thereby. Any equivalent change or equivalent modification made on the basis of this technical solution according to the technical idea proposed by the present invention still belongs to the protection scope of the technical solution of the present invention. The technical idea of our combination of logic gate decomposition and technology mapping can also be applied to the technology mapping algorithm of ASIC.

[0050] Appendix: Pseudo-code of the multi-input logic gate cutting enumeration algorithm

[0051]

[0052] References

[0053] [1] A. Mishchenko, S. Chatterjee, and R. Brayton, Improvements to Technology Mapping for LUT-Based FPGAs. In Proceedings of the 2006 ACM / SIGDA 14th International Symposium on Field Programmable Gate Arrays.

[0054] [2] G. Chen and J. Cong, Simultaneous Logic Decomposition with Technology Mapping in FPGA esigns. In Proceedings of the 2001 ACM / SIGDA Ninth International Symposium on Field Programmable Gate Arrays.

[0055] [3] J. Cong, C. Wu and Y. Ding, Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution. In Proceedings of the 1999 ACM / SIGDA Seventh International Symposium on Field Programmable Gate Arrays.

[0056] [4] R. Francis, J. Rose, and Z. Vranesic, Technology mapping of lookup table-based FPGAs for performance. In 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers. 568–571.

[0057] [5]R. Brayton and A. Mishchenko, ABC: An academic industrial strength verification tool. In International Conference on Computer Aided Verification 2010. Springer, 24–40。

Claims

1. An FPGA technology mapping algorithm based on logic gate decomposition, characterized in that During the process of technology mapping, logical gate decomposition is selectively performed to optimize the area and timing performance of the synthesized circuit. The specific steps are as follows: Traverse all logical gates from the input nodes PI to the output nodes PO of the netlist in topological order; (1) For 2-input logical gates, use the traditional node splitting enumeration algorithm; (2) For multi-input AND and OR logical gates: First, enumerate the wide-cuts of this logical gate according to the multi-input logical gate splitting enumeration algorithm, and then use the logical gate decomposition algorithm to form the logical decomposition schemes of these wide-cuts and the technology mapping schemes of K-LUTs, so as to obtain the area and timing evaluations of these wide-cuts. Then, use the traditional cut sorting method to retain several cuts with better area and timing. These retained cuts are used both when generating subsequent mapping schemes and when performing cut enumeration for the fan-out logical gates of this logical gate; (3) After the cut enumeration of all logical gates is completed, a technology mapping scheme is generated through the cut selection algorithm. The cut selection algorithm selects the root nodes of the LUTs to be generated and the corresponding cuts from the output nodes PO to the input nodes PI: First, mark all PO nodes as LUT root nodes. Then, for each LUT root node, select one of its best cuts to form an LUT, and mark the inputs of this cut as LUT root nodes. This process will continue until all marked LUT root nodes are traversed. At this time, the corresponding set of selected cuts constitutes a complete technology mapping result.

2. The FPGA technology mapping algorithm based on logic gate decomposition according to claim 1, wherein The multi-input logical gate splitting enumeration algorithm is specifically as follows: Assume that a logic gate has W inputs, each input has C cuts, and the complexity of the cut enumeration algorithm is C 2 : Consider the cuts of each input gate in turn for enumeration. First, generate an empty cut queue L. Then, merge L with the cuts of the input gate in turn to generate a queue Ltemp of partial cuts. Then, set L to Ltemp and merge it with the cuts of the next input until all input logical gates are processed. For partial cuts, the area calculation formula is formula (1):

3. The FPGA technology mapping algorithm based on logic gate decomposition according to claim 2, characterized in that, The logical gate decomposition algorithm is specifically: For a wide-cut with more than K inputs, decompose the multi-input logical gate it represents to form a logical decomposition and technology mapping scheme composed of K-cuts. Specifically, use the bin-packing algorithm to perform logical gate decomposition and technology mapping; The bin-packing algorithm is to use a fixed-size box to pack some small boxes, requiring that the total volume of these small boxes does not exceed the volume of this large box, and at the same time use as few large boxes as possible to pack these small boxes. If a large box cannot hold this small box, use a new large box to hold it; Perform wide cut area evaluation after bin packing: Assume the set of these small bins is {cut i}, and their areas are fanout i is the fanout of the i-th input; Assume a cut is the number of large bins required by the bin packing algorithm; The area evaluation formula for wide cut is (2): Among them, i-thinput represents the i-th fan-in of the wide logical gate. In this way, all wide-cuts of a logical gate can be evaluated and sorted, and then several cuts with good optimization effects are retained, and the rest of the cuts are no longer retained.

4. The FPGA process mapping algorithm based on logic gate decomposition according to claim 3, wherein The cut selection algorithm is specifically: After the enumeration is completed, the cut selection of the entire netlist will be executed and finally the LUT netlist will be generated; The steps are as follows: First, mark the netlist output node PO as the LUT root node, then traverse the netlist from the PO to the netlist input node PI in reverse topological order. For each LUT root node, select a best cut, and at the same time, mark the input nodes of the selected cut as LUT root nodes; this process continues until all LUT root nodes are visited; The cutting selection algorithm adopts an iterative algorithm multiple times to improve the area optimization effect; first, assign a variable m to each node i , representing the area weight of this node; the m of a node marked as the LUT root node i is 0, otherwise it is 1; the new cut selection area calculation formula is (3): The actual cost of the cut of the LUT root node will be calculated according to the above formula, and the cut with the minimum cost will be selected to form the final mapping solution.

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