High-density ferroelectric memory, its fabrication methods and applications

Abstract

This invention discloses a high-density ferroelectric memory, its fabrication method, and its applications, belonging to the field of semiconductor memories. The memory consists of an array of multiple memory cells connected on both sides by substantially orthogonal word lines and bit lines. The memory cell of this invention employs a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, electrically equivalent to a ferroelectric capacitor connected in series with a resistive switching selector. By adjusting the RC delay of the memory cell, the voltage drop across the ferroelectric capacitor in the unselected cell is reduced, thus reducing its disturbance. Furthermore, the ferroelectric capacitor has a stable capacitance value, which can be effectively reduced by RC regulation to mitigate the impact of disturbance voltage. In summary, this invention increases the memory's storage window and reduces the bit error rate without increasing additional area overhead.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory, and particularly to a high-density ferroelectric memory. Background Technology

[0002] With the continuous advancement of electronic information technology, the demand for low-power, high-capacity memory is constantly increasing. Traditional flash memory utilizes the principle of charge storage and employs hot electron injection and FN tunneling for erasing and writing, resulting in high power consumption and long erase / write times. Traditional dynamic random access memory (DRAM), on the other hand, suffers from short memory retention times due to transistor leakage, requiring high-frequency refresh rates and leading to significant dynamic power consumption. Today, with the continuous development of the Internet of Things, artificial intelligence, and big data, these problems will become increasingly severe.

[0003] Ferroelectric materials, due to their asymmetric lattice structure, exhibit spontaneous polarization charges that can be controlled by an electric field, and the polarization reversal rate depends on the lattice relaxation time. Therefore, memories designed based on ferroelectric materials have the advantages of low power consumption and high speed. However, traditional ferroelectric materials based on perovskite structures (such as PZT and BTO) have complex compositions, low CMOS process compatibility, and significant size effects, making them unsuitable for integration in advanced process nodes. As a result, memories based on traditional ferroelectric materials are only used in certain special edge applications.

[0004] In recent years, researchers have discovered that CMOS-compatible hafnium oxide (HfO2) thin films can induce ferroelectricity under specific doping, stress, and annealing conditions, breaking the constraints of poor integration and miniaturization of ferroelectric material devices. Among different types of hafnium oxide-based ferroelectric memories, cross-matrix memories based on ferroelectric capacitors have high storage density, enabling high-speed data read and write, and exhibiting good data retention and low power consumption, making them a promising alternative to traditional DRAM. However, further research has revealed that HfO2-based ferroelectric materials possess polycrystalline and multi-domain characteristics, and their ferroelectric domains have a wide coercive field distribution. This results in significant perturbations to unselected cells during write and read operations on selected cells in the array, easily causing severe bit-flipping problems. One technique involves connecting a resistive selector in series with the gate of a traditional perovskite ferroelectric transistor and utilizing the high resistance of the selector at lower voltages to increase the RC delay during writes, thereby reducing the gate voltage of disturbed cells. However, this approach ignores the difference in capacitance between semiconductor materials at different voltages. At lower voltages, the semiconductor capacitance is small, resulting in insufficient RC delay, and existing techniques cannot effectively reduce disturbances in unselected cells. Therefore, achieving low-disturbance ferroelectric cross-matrix memory has become a pressing problem. Summary of the Invention

[0005] The purpose of this invention is to provide a high-density ferroelectric memory. This invention features lower read / write perturbations, a lower bit error rate, and a larger memory window.

[0006] The specific technical solution of this invention is as follows:

[0007] A cross-matrix ferroelectric capacitor memory is characterized in that the memory consists of an array of multiple memory cells, and the two sides of the memory cell array are connected by substantially orthogonal word lines and bit lines; the memory cell is composed of multiple layers of stacked materials, which, from top to bottom, are a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode. By simultaneously applying positive and negative half-select voltages to the word / bit line, the memory cell connected to the word / bit line can complete the read and write operations.

[0008] The storage cell structure of this invention comprises a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor connected in series with a resistive switching selector. When the voltage applied to the storage cell does not exceed a certain limit, the resistive switching selector is in a high-resistance state. When the voltage is high enough, oxygen vacancies in the resistive switching selector or metal atoms in the electrode undergo directional migration and form a continuous conductive metal filament in the resistive switching dielectric layer, greatly reducing the resistance value of the resistive switching device. The ferroelectric dielectric layer has a spontaneous polarization intensity that can be reversed by an applied voltage, enabling non-volatile data storage.

[0009] When a positive / negative half-select voltage is applied simultaneously to a pair of word / bit lines, the memory cell connected to that word / bit line receives twice the half-select voltage, i.e., the full-swing voltage. This memory cell is then the selected memory cell, and its resistive selector becomes low-resistance. The RC delay of the entire memory cell is small, and the voltage of the ferroelectric capacitor can reach the full-swing voltage and undergo ferroelectric spontaneous polarization reversal during the read / write pulse application time, completing the read / write operation. Other memory cells connected to the corresponding word / bit lines are disturbed memory cells, affected by one half-select voltage. The voltage applied to the disturbed memory cells cannot make their resistive selectors become low-resistance, so the RC delay of the disturbed memory cells is large. During the read / write pulse application time, the voltage of the ferroelectric capacitor cannot rise to the half-select voltage, reducing the voltage drop of the ferroelectric capacitor and thus reducing the disturbance caused by the half-select voltage to the disturbed memory cells.

[0010] The top electrode in the aforementioned memory cell is made of a material that readily undergoes electromigration in the dielectric layer of the resistive switching selector, or a material that readily absorbs oxygen to generate oxygen vacancies in the dielectric layer. Ag or Ti is preferred for the top electrode. To provide sufficient stress during annealing to allow ferroelectric crystal formation in the ferroelectric dielectric layer, the intermediate metal layer and the bottom electrode can be selected from the following electrode materials as required: TiN, TaN, Pt, Mo, Ru, W, etc. The resistive switching dielectric layer is based on HfO2 or TaO. xThe dielectric material can generate resistive switching effect; the ferroelectric dielectric layer: adopts traditional ferroelectric materials such as perovskite ferroelectric (PZT, BFO, SBT) and ferroelectric polymer (P(VDF-TrFE)) or novel ferroelectric materials based on HfO2 that generate ferroelectricity under specific treatments (doping, stress, annealing, etc.). In the above-mentioned cross-array ferroelectric capacitor memory based on resistive switching selectors, the electrode thickness is preferably 10–100 nm; the thickness of the resistive switching dielectric layer and the ferroelectric dielectric layer is preferably 8–15 nm.

[0011] The present invention further provides an electronic device including the above-described cross-matrix ferroelectric capacitor memory.

[0012] The beneficial effects and corresponding principles of the cross-matrix ferroelectric capacitor memory based on resistive selector of the present invention are as follows:

[0013] When accessing a specific memory cell in a cross-matrix ferroelectric capacitor memory, positive and negative half-select voltages are applied to the corresponding word / bit line. The selected memory cell receives a full-swing voltage (twice the half-select voltage), causing its resistive selector to become low-resistance. This significantly reduces the RC delay of the selected memory cell, allowing the ferroelectric voltage to rise to the full-swing voltage within the read / write pulse time, triggering a ferroelectric polarization flip and completing the read / write operation. Conversely, the disturbed memory cell connected to the same word / bit line receives a half-select voltage, keeping its resistive selector in a high-resistance state. This results in a larger RC delay for the disturbed memory cell, making it difficult for the ferroelectric voltage to rise to the half-select voltage within the read / write pulse time. This reduces the disturbance of the half-select voltage to the information stored in the ferroelectric capacitor, lowers the memory error rate, and increases the memory window. Furthermore, since the ferroelectric capacitance value in the memory cell is relatively stable under different voltages, the resistive selector can effectively reduce the ferroelectric voltage drop in the disturbed memory cell. Compared with traditional cross-matrix ferroelectric capacitor memories, the memory of the present invention has smaller read / write perturbations, lower bit error rate and larger storage window. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a cross-matrix ferroelectric capacitor memory based on a resistive selector according to an embodiment of the present invention.

[0015] In the picture:

[0016] 1—Substrate; 2—Bit Line (BL)

[0017] 3 – Word Line (WL) 4 – Storage Cell (SC)

[0018] Figure 2 This is a cross-sectional schematic diagram of a single storage cell according to an embodiment of the present invention.

[0019] In the picture:

[0020] 5 – Top Electrode (TE) 6 – Upper Dielectric (UD)

[0021] 7 – Middle Electrode (ME) – 8 – Lower Dielectric (LD) –

[0022] 9—Bottom Electrode, BE Detailed Implementation

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] like Figure 1 As shown, this embodiment provides a cross-matrix ferroelectric capacitor memory, which consists of multiple memory cells arranged in an array, with the two sides of the memory cell array connected by substantially orthogonal word lines and bit lines. Wherein, as Figure 2 As shown, each memory cell consists of a top electrode TE, a resistive switching dielectric layer UD, an intermediate metal layer ME, a ferroelectric dielectric layer LD, and a bottom electrode BE, from top to bottom. The top electrode is preferably made of Ag or Ti; the intermediate metal layer and the bottom electrode are made of TiN, TaN, Pt, Mo, Ru, W, etc. The resistive switching dielectric layer is based on HfO2 or TaO. x The dielectric material can generate resistive switching effect; the ferroelectric dielectric layer: adopts traditional ferroelectric materials such as perovskite ferroelectric (PZT, BFO, SBT) and ferroelectric polymer (P(VDF-TrFE)) or novel ferroelectric materials based on HfO2 to generate ferroelectricity under specific treatments (doping, stress, annealing, etc.). The electrode thickness is preferably 10-100 nm; the thickness of the resistive switching dielectric layer and the ferroelectric dielectric layer is preferably 8-15 nm. This embodiment also provides a method for fabricating the above-mentioned cross-matrix ferroelectric capacitor memory based on resistive switching selector, and the fabrication process is as follows:

[0025] (1) The bottom electrode was fabricated on a SiO2 substrate by physical vapor deposition (PVD);

[0026] (2) Define the bottom electrode pattern by photolithography and form the bottom electrode by wet etching or dry etching;

[0027] (3) A ferroelectric dielectric layer is grown on the surface of the bottom electrode prepared in step (2) by atomic layer deposition (ALD);

[0028] (4) Define the intermediate layer metal pattern using photolithography;

[0029] (5) An intermediate metal layer is grown on a patterned photoresist by PVD;

[0030] (6) The intermediate metal layer is peeled off and shaped by removing adhesive;

[0031] (7) Continue to grow the resistive switching dielectric layer by ALD;

[0032] (8) Define the top electrode pattern using photolithography;

[0033] (9) A top electrode metal layer is grown on a patterned photoresist by PVD;

[0034] (10) The top electrode is peeled and shaped by removing adhesive;

[0035] (11) The upper dielectric material crystallizes and the lower dielectric material becomes ferroelectric by rapid thermal annealing (RTA) crystallization under certain conditions;

[0036] (12) Photolithography defines the position of the bottom electrode contact hole;

[0037] (13) Etch to expose the bottom electrode for contact.

[0038] For example, when accessing a memory cell, a positive half-select voltage V is applied to the word line containing that memory cell. dd / 2, apply a negative half-select voltage -V to the corresponding bit line. dd / 2, other word / bit lines are grounded. At this time, the selected memory cell is subjected to a full-swing voltage V. dd In this memory cell, the resistive selector switches to a low-resistance state, reducing the RC delay of the memory cell. During the read / write pulse time, the ferroelectric capacitor voltage can rise to its full swing voltage, enabling the ferroelectric capacitor to write or read information. Simultaneously, the disturbed memory cell on the same word / bit line is subjected to a half-select voltage V. dd Due to the influence of / 2, its resistive selector maintains a high resistance state, resulting in a high RC delay of the storage cell. During the read / write pulse time, the ferroelectric capacitor voltage is difficult to rise to the half-select voltage. The voltage division of the ferroelectric capacitor is very small, which reduces the disturbance of the half-select voltage to the stored information.

[0039] The beneficial effects of the present invention are illustrated in this embodiment:

[0040] Conventional ferroelectric cross-matrix capacitor memories suffer from severe half-selection disturbance voltage perturbations, resulting in high bit error rates and small storage windows. This invention addresses this issue by employing a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode. This reduces the voltage drop across unselected cells, thus minimizing disturbance. Furthermore, the stable capacitance of the ferroelectric capacitors allows for effective RC modulation to reduce the impact of disturbance voltages. In summary, this invention improves the storage window and reduces the bit error rate without increasing area overhead.

[0041] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

Claims

1. A cross-matrix ferroelectric capacitor memory, characterized in that, The memory consists of an array of multiple memory cells connected on both sides by substantially orthogonal word lines and bit lines. Each memory cell is constructed from multiple layers of stacked materials, consisting of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, from top to bottom. The resistive switching dielectric layer is based on HfO2 or TaO. x The dielectric material that generates the resistive switching effect is a perovskite ferroelectric material, a ferroelectric polymer material, or a ferroelectric material based on HfO2 that generates ferroelectricity after treatment. The top electrode is Ag or Ti, and the intermediate metal layer and bottom electrode are TiN, TaN, Pt, Mo, Ru, or W. The thickness of the top electrode, bottom electrode, or intermediate metal layer ranges from 10 to 100 nm, and the thickness of the resistive switching dielectric layer or ferroelectric dielectric layer ranges from 8 to 15 nm. When a positive / negative half-select voltage is applied to a pair of word / bit lines simultaneously, the memory cell connected to that word / bit line receives twice the half-select voltage. This memory cell is then selected, and read / write operations are performed on the selected memory cell. Other memory cells corresponding to the word / bit lines are disturbed memory cells.

2. A method for fabricating a cross-matrix ferroelectric capacitor memory as described in claim 1, comprising the following steps: 1) The bottom electrode material is prepared on the substrate by physical vapor deposition; 2) Define the bottom electrode pattern using photolithography, and form the bottom electrode using wet etching or dry etching methods; 3) Ferroelectric materials are grown on the surface of the bottom electrode via atomic layer deposition; 4) Define the intermediate metal pattern using photolithography; 5) An intermediate metal layer is grown on a patterned photoresist using physical vapor deposition; 6) The intermediate metal layer is peeled off and shaped by removing the adhesive; 7) Continue to grow resistive switching dielectric materials using atomic layer deposition (ALD). 8) Define the top electrode pattern using photolithography; 9) A top electrode metal layer is grown on a patterned photoresist using physical vapor deposition. 10) The top electrode is peeled and shaped by removing the adhesive; 11) Rapid thermal annealing crystallizes resistive switching materials, and ferroelectric materials develop ferroelectricity. 12) Photolithography defines the location of the bottom electrode contact hole; 13) Etch to expose the bottom electrode for contact.

3. An electronic device, characterized in that, Including the cross-matrix ferroelectric capacitor memory as described in claim 1.

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