Optical phased array driver

Abstract

An optical phased array including a row-column drive mechanism is disclosed that reduces the number of digital-to-analog converter (DAC) channels to N rows, reducing the total number of interface pins to the number of columns plus the number of rows M+N. Systems and architectures for thermal waveguide-based phase shifters are disclosed herein that improve thermal efficiency by arranging the multiple pass waveguides proximate to a heating element in a serpentine fashion, which can increase the phase shift without increasing the length or power consumption of the heating element by increasing the total length of the waveguides heated by a single heating element.

Description

Technical Field

[0001] This disclosure relates to thermal optical phaseshifters used in integrated photonics, and more particularly to a driver for an array of thermal optical phaseshifters. Background Technology

[0002] Phase shifters are commonly used to change the phase of light propagating through waveguides. Thermal phase shifters, also known as thermo-optical phase shifters, can be used to change the phase of light in a waveguide by heating it, thereby altering the refractive index of the waveguide in the heated region via a thermo-optical effect. Any light whose index value changes slightly as it propagates through the heated region travels at a different phase velocity, resulting in a net phase shift after a certain propagation distance. In this way, thermal phase shifters can be used to control the switching, attenuation, or modulation of optical signals.

[0003] Achieving high resolution, large aperture, and large field of view (FOV) simultaneously in an optical phased array (OPA) requires operating a large number of phase shifters concurrently. Traditionally, this has been achieved by forcibly controlling each individual phase shifter using separate analog drive channels. However, this approach is difficult to scale to very large phase shifter arrays, and becomes unmanageable as the number of independent channels becomes too large: 1) too many independent metal traces need to be wired to the outside of the photonic chip, and 2) too many independent analog-to-digital converter (DAC) channels increase cost and complicate control.

[0004] The purpose of this invention is to overcome the shortcomings of the prior art by providing a more efficient driver for optical phased arrays. Summary of the Invention

[0005] Therefore, the present invention relates to an optical phased array device, comprising:

[0006] An optical phase shifter array, comprising multiple rows of optical phase shifters and multiple columns of optical phase shifters;

[0007] Multiple digital-to-analog converters (DACs), each of which is configured to output an independent voltage or current to one of the multiple line optical phase shifters;

[0008] Multiple ground buses, each of which is configured to connect one of the multiple optical phase shifters to a common ground;

[0009] A multiplexer configured to selectively connect one of the plurality of ground buses to the common ground while disconnecting the other ground buses among the plurality of ground buses;

[0010] processor; and

[0011] Non-volatile memory used to store instructions, which, when executed by the processor:

[0012] Sequentially select one of the multiple optical phase shifters to connect to the common ground, while disconnecting any other ground bus among the plurality of ground buses; and

[0013] Update the voltage or current of each of the plurality of DACs that serve as the basis for selecting one of the plurality of optical phase shifters. Attached Figure Description

[0014] The invention will be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention, wherein:

[0015] Figure 1 This is a top view of an optical phase shifter array fed by an optical phased array;

[0016] Figure 2A This is a side view of an optical phase shifter;

[0017] Figure 2B yes Figure 2A Top view of an optical phase shifter;

[0018] Figure 3 yes Figure 1 A schematic diagram of the driver system for an optical phased array;

[0019] Figure 4A It is a graph of the time of multiple DACs and multiple switches versus voltage or current over multiple pulse cycles;

[0020] Figure 4B This is a flowchart of the pulse period;

[0021] Figure 5 This is a top view of a multi-pass waveguide phase shifter according to an exemplary embodiment of the present invention;

[0022] Figure 6A yes Figure 5 A top view of an exemplary optical waveguide arrangement for a multi-pass optical waveguide phase shifter;

[0023] Figure 6B yes Figure 6A A cross-sectional view of the optical waveguide arrangement;

[0024] Figure 7A yes Figure 5 A top view of an exemplary optical waveguide arrangement for a multi-pass optical waveguide phase shifter;

[0025] Figure 7B yes Figure 7A A cross-sectional view of the optical waveguide arrangement;

[0026] Figure 8A yes Figure 5A top view of an exemplary doped silicon heater for a multi-channel optical waveguide phase shifter;

[0027] Figure 8B yes Figure 8A A schematic diagram of a silicon-doped heater;

[0028] Figure 9A This is a top view of an exemplary optical waveguide arrangement for a multi-pass optical waveguide phase shifter;

[0029] Figure 9B yes Figure 9A A cross-sectional view of the optical waveguide arrangement;

[0030] Figure 10 This is a top view of an exemplary optical waveguide arrangement for a multi-pass optical waveguide phase shifter;

[0031] Figure 11 This is a top view of an exemplary optical waveguide arrangement for a multi-pass optical waveguide phase shifter;

[0032] Figure 12 This is a top view of an exemplary optical waveguide arrangement for a multi-pass optical waveguide phase shifter; and

[0033] Figure 13 This is a top view of an exemplary optical waveguide arrangement for a multi-pass optical waveguide phase shifter. Detailed Implementation

[0034] While this teaching is illustrated with various implementations and examples, it is not intended to limit this teaching to these implementations. Rather, those skilled in the art will understand that this teaching includes various alternatives and equivalents.

[0035] Note that for many practical applications of integrated photonics, particularly optical phased arrays, a large number of phase shifters must be densely packed on a chip. When using multiple phase shifters, they must be spaced sufficiently far apart to prevent thermal crosstalk, where a heater will change the phase of light passing through an adjacent phase shifter because the lateral diffusion of heat also heats these waveguides. If the phase shifters are arranged in a simple one-dimensional array (an array of unit vectors perpendicular to the direction of light propagation), they must be spaced more than about 15 μm apart to ensure less than 10% crosstalk. For large arrays, the shape of conventional constructions is also quite awkward, as a 1024 phase shifter array would occupy a rectangle of approximately 500 μm × 16 mm.

[0036] refer to Figure 1 The optical phased array 1 may include a light source structure 5 and multiple phase shifters 10. M,N These phase shifters can be arranged in multiple (M) columns and multiple (N) rows, forming a 2D (MxN) phase shifter. M,NThe array. The light source structure 5 may include: 1) a single light source and an optical waveguide tree configured to emit a single beam, the optical waveguide tree dividing the single beam into multiple sub-beams, each sub-beam being transmitted by optical coupling to one of multiple routing waveguides 8 of the light source structure 5; 2) multiple light sources, each light source being optically coupled to one of multiple routing waveguides 8; or 3) multiple light sources, each light source being optically coupled to multiple routing waveguides 8 via a waveguide tree.

[0037] Phase shifter 10 M,N Adjacent columns can be staggered, for example, adjacent phase shifters 10 in alternating columns. M,N A predetermined gap g can be offset vertically, for example, offsetting at least one phase shifter 10. M,N The width of the adjacent phase shifters 10 M,N They are not directly adjacent to each other, and this extends to phase shifter 10. M,N The input waveguide 14 extends into each phase shifter 10. M,N The output waveguides 16 can also be spaced apart by a predetermined gap g width, so that they do not physically overlap or cause any optical crosstalk between them.

[0038] Routing waveguide 8 in other phase shifters 10 M,N Extending outwards from between. Phase shifter 10 M,N Multiple columns C 1-M and phase shifter 10 M,N Multiple rows of R 1-N It has an interleaved structure, in which phase shifter 10 M,N Odd-numbered columns (e.g., C1, C3, and C5) offset phase shifter 10 M,N At least one phase shifter 10 in even-numbered sequences (e.g., C2, C4, and C6) M,N The length comes from phase shifter 10 M,N The even-numbered sequence of escape waveguide 8 in phase shifter 10 M,N Phase shifter 10 in the odd-numbered sequence M,N Extending between.

[0039] refer to Figure 2A and Figure 2B 10 for each phase shifter M,NThe device may include a substrate 24, which may include silicon or other suitable materials. Adjacent to the substrate 24, for example on top of it, may be a cladding layer, such as an upper cladding layer 26a and a lower cladding layer 26b, which may be dielectric materials such as silicon dioxide. A heater 22 may be located on the upper cladding layer 26a. The heater 22 may be any suitable device or material configured to generate heat, such as titanium nitride, nickel-chromium alloy, heavily doped silicon, silicide, titanium, and tungsten. In some embodiments, the heater 22 includes a resistor, such as a metal or semiconductor wire that heats up when current flows through it. Directly below the heater 22, an optical waveguide 30 may be formed in a device or waveguide layer between the upper cladding layer 26a and the lower cladding layer 26b. Figure 2A As shown, the optical waveguide 30 is parallel to the substrate 24 and is positioned as follows: Figure 2B The top view shows the directional extension parallel to heater 22. Therefore, heat from heater 22 diffuses downwards through the upper cladding 26a and into the optical waveguide 30. Heat also diffuses laterally in the upper cladding 26a, lower cladding 26b, and the underlying substrate 24. The heat distribution at the optical waveguide layer decreases within a few micrometers as the distance from heater 22 and optical waveguide 30 increases.

[0040] Heater 22 may be located on top of or inside the upper cladding 26A. Heater 22 may comprise, for example, a metal, a metal alloy (e.g., a nickel-chromium alloy), a conductive metal nitride, or a silicide. Alternatively, heater 22 may comprise doping in and / or around the optical waveguide 30 itself, such that current flowing through the optical waveguide layer and / or the optical waveguide 30 causes heating of the optical waveguide 30. Other types of phase shifters 10, as described below... M,N Within the scope of this invention, and including those disclosed in U.S. Patent Application 16 / 826051, filed on March 20, 2020, in the name of the applicant of this application.

[0041] In order to drive the phase shifter 10 independently at the same time M,N Multiple columns C 1-M and phase shifter 10 M,N Multiple rows of R 1-N The traditional approach is to use M x N independent DAC channels. However, as the size of the phase shifter increases, this inevitably leads to a high number of driver channels, which complicates wiring layout and control, and quickly reaches the practical limit of the interface pin count.

[0042] refer to Figure 3 By utilizing the relatively slow thermal time constant of heater 22 and by constructing a fast-switching row and column drive scheme, the number of digital-to-analog converter drivers DAC1 to DAC2 can be reduced. N Simultaneous operation of all phase shifters 10 with the number of interface pins M,N .like Figure 3As shown, each heater 22 may include a diode 33 connected in series with the thermal resistance 34 forming the diode heater 22, and a phase shifter 10 M,N Each row R1 to R N The first contact (e.g., the anode) in the diode heater 22 can be connected via suitable wire traces or channels 351 to 35 extending along each row. N Electrically connected to the corresponding common DAC channel (DAC1 to DAC2). N ), and phase shifter 10 M,N Each column C1 to C M The second contact (e.g., cathode) of the diode heater 22 can be fully electrically connected to the phase shifter 10. M,N Columns C1 to C M Extended suitable wire traces or channels to the common ground bus 361 to 36 M .

[0043] Diode 33 may include a silicon PN diode, a silicon PIN diode, a Schottky diode, a germanium diode, or any other suitable diode. The forward voltage and reverse breakdown voltage of diode 33 affect system performance and efficiency. Diode 33 may be configured to include an absolute reverse breakdown voltage greater than the maximum DAC drive voltage, thereby preventing reverse current from flowing through heater 22 to phase shifter 10. M,N Other columns C1 to C M The other heaters 22 in the array are not intended to be part of the driving algorithm. Each diode 33 can be configured such that its anode faces DAC1 to DAC2. N Connect, and the cathode faces the ground bus 361 to 36. M The corresponding connection in (assuming a positive DAC voltage).

[0044] Phase shifter 10 M,N Different columns of ground bus 361 to 36 M It can be connected to analog multiplexer 38, for example, ground bus 361 to 36. M Each of them is connected to the corresponding switch (SW1 to SW2). M This enables the controller processor 40 to execute instructions stored in non-volatile memory to select only the phase shifter 10. M,N A column C1 to C M Simultaneously connected to ground 45°, thus connecting the circuit. Digital-to-analog converter DAC1 to DAC N and switches SW1 to SW M It may not be located at phase shifter 10 M,NOn the same photonic circuit chip, and can be connected to the photonic circuit via wire bonding or bump bonding. For those capable of being connected with, including phase shifter 10 M,N Digital-to-analog converters DAC1 to DAC are generated on the same die as the photonic circuit. N and / or switches SW1 to SW M Photonics technology, digital-to-analog converter DAC1 to DAC N and switches SW1 to SW M Some or all of them can be manufactured and positioned on the same die.

[0045] Switches SW1 to SW in analog multiplexer 38 M This may include metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), junction field-effect transistors (JFETs), or other transistors configured to form a low-resistance path to a common ground 45. Particularly, preferably, each switch SW1 to SW2... M The resistance in the heat-sensitive phase shifter is much smaller than that in the thermal phase shifter. M,N The resistance in it is typically less than that of a thermal phase shifter. M,N One-tenth of the resistance in the circuit is used to minimize crosstalk and maximize the accuracy of the set phase shift. N-type field-effect transistors are generally preferred because they provide a low-resistance path to ground, i.e., low on-resistance, and in switching SW1 to SW2... M It has a very low built-in voltage at both ends, that is, the drain-to-source voltage, which makes the ground bus 361 to 36 M It can maintain the lowest possible voltage relative to the DAC drive voltage. Each switch SW1 to SW2... M and each ground bus 361 to 36 M The built-in voltage is typically less than 1 volt. Advantageously, each switch SW1 to SW2... M Use more than one transistor (e.g., a transfer gate) or add additional control transistors to construct switches SW1 to SW. M To decode signals from controller processor 40 or to ensure that only one switch SW1 to SW is closed at a time. M (i.e., break before making switching).

[0046] like Figure 4A and Figure 4B As shown, when phase shifter 10 M,N When one column (e.g., C1) is selected, for example, SW1 is connected to ground 45, the controller processor 40, containing appropriate hardware and software, executes instructions stored in non-volatile memory, and the phase shifter (e.g., 10) 1,1 Up to 101,N Each row R1 to R N On-board digital-to-analog converter DAC1 to DAC N Current will be fed to the diode heater 22 in this column and row combination (M,N). Current will not be supplied to the phase shifter 10. M,N Other columns (e.g., columns C2 to C3) M The flow is due to the switch (e.g., switch SW2 to SW) N The circuit is disconnected via controller processor 40 and has no path to ground 45. Similarly, the reverse bias blocking behavior of the diode prevents current from flowing through other unintended diode heaters 22. This is for the next phase shifter 10. M,N Feed current, selected by the controller processor 40 via phase shifter 10 M,N The next switch on column C2 (e.g., switch SW2) and deselect phase shifter 10. M,N The switch (SW1) on the previous column (e.g., column C1), and the phase shifter (e.g., phase shifter 10) 2,1 Up to 10 2,N The digital-to-analog converters DAC1 to DAC1 on each row of the DAC1 are... N Updated to correspond to phase shifter 10 M,N New columns (e.g., column C2) and rows (rows R1 to R2) N A new set of DAC values ​​is generated by combining the values ​​in phase shifter 10. M,N All columns C1 to C N Phase shifter 10 is sequentially turned on M,N After the other columns are disconnected, the controller processor 40 loops back and switches to phase shifter 10. 1,N The first column (e.g., C1) is used, and this process is repeated indefinitely. (See reference.) Figure 4A One cycle is called a pulse period.

[0047] Figure 4A It was also marked with R N C M This corresponds to phase shifter 10 in the timing diagram. M,N The timing of the power supply. For example, R2C1 indicates when current is injected into phase shifter 10 in row 2, column 1. 1,2 In heater 22, therefore, heater 22 sees only one current injection pulse for each pulse cycle. As a result, phase shifter array 10 1,1 Up to 10 M,N Total pulse cycle time T pulse It is the number of columns M × each switch SW1 to SW M Switch dwell time t dwell or T pulse =t dwell *M.

[0048] Notice, Figure 4A Only one exemplary implementation is shown, in which digital-to-analog converters DAC1 to DAC2 are shown. N During the switch dwell time t dwell It provides a constant voltage (or current). In practice, the digital-to-analog converter DAC1 to DAC... N A time-varying voltage (or current) waveform can be supplied to each heater 22 within the switching dwell time tdwell. The thermal time constant of heater 22 effectively connects the digital-to-analog converter DAC1 to DAC2. N Rapid changes in the output are averaged or filtered out. In one arrangement, the time-varying voltage or current can be pulse-width modulated, thereby averaging or filtering out each digital-to-analog converter DAC1 to DAC2. N The circuit is switched to high voltage or current for a certain period of time, and then switched to low voltage or current. The total energy delivered to heater 22 is transferred from each digital-to-analog converter DAC1 to DCA. N The duration of conduction is controlled. To ensure a constant temperature, the pulse cycle time T... pulse The thermal time constant of heater 22 can be much shorter, therefore, the heater temperature will rise to a constant value with very slight fluctuations. The number of columns M will limit the switching speed. To minimize fluctuations, ideally, the pulse cycle time T... pulse It is less than or equal to approximately 1 / 100 of the thermal time constant of heater 22. For example, if the thermal time constant is 100 ms, then the pulse cycle time T pulse It can be less than or equal to 1ms, then the on / off dwell time t dwell It can be 10 columns (M=10) 100ns. Therefore, if the switch dwell time t dwell Since 1 / 10 = 10 ns, the switching time is still very manageable for ordinary discrete transistors or integrated circuit switches. For similar pulse period times T... pulse Faster switching will allow for more columns of phase shifters. M,N With more rows and columns of phase shifters 10 M,N When connected, a larger current will flow through each ground bus 361 to 36 M Then the current flows through each switch SW1 to SW M Therefore, with the addition of more line phase shifters 10 M,N Switches SW1 to SW M and ground bus 361 to 36 M Higher current needs to be handled. For example, setting M=10 and N=10, if each phase shifter has 10... M,NFor a 2p phase shift (the maximum phase shifter setting of the OPA) consuming 6mW DC power, then M=10 represents 10 times the instantaneous power in the pulse, i.e., 60mW. If a 3.3V driver (e.g., power supply) is used, then each digital-to-analog converter DAC1 to DAC2... N Provides approximately 18mA, and flows through ground bus 361 to 36. M and each switch SW1 to SW M The maximum instantaneous current is 18mA x N(rows) = 180mA. Therefore, it is generally preferable to use a higher voltage to minimize the current. For the same example, using a 10V driver would allow 361 to 36... M The maximum transient current is reduced to 60mA. However, in this example, 10x10 (100 phase shifters) M,N The OPA only requires 10 DAC channels and 20 pins to connect.

[0049] Non-volatile memory will be allocated to each phase shifter 10 M,N Digital-to-analog converter DAC1 to DAC N The value (voltage or current) is stored in phase shifter 10. M,N In each corresponding row, the value of each DACn(m,p) can be a constant. The value of each DACn(m,p) can be a time-varying waveform.

[0050] Reference Figure 4B The following steps illustrate how to operate an optical phased array driver:

[0051] i) Switch the first ground bus (M=1) to ground 45, for example, by closing the first switch SW1 and opening all other switches, for example, by opening switches SW2 to SW5. M .

[0052] ii) Transfer phase shifter 10 from non-volatile memory M,N All DAC channels (e.g., voltage or current values) in all N rows are updated to phase shifters in column M=1. 1,N The corresponding value, and the optional p-th turning direction (DACn(1,p)). Phase shifter 10 M,N Each row R1 to R N It can be set to different voltages, and the phase shifter 10 M,N Each column C1 to C M A different set of line voltages may be required. Phase shifter 10 M,N It can be configured such that the light leaving the device will form a flat phase wavefront pointing in the p-th turning direction. However, due to manufacturing defects on the chip and phase shifter 10 M,NThe crosstalk between phase shifters means that the phase shifter voltage / current values ​​required to create the output phase are often highly random and may need to be stored in a lookup table in non-volatile memory, or even dynamically calculated by the controller processor 40 using some kind of feedback. Analog control of each heater 22 by the controller processor 40 may be necessary because any angular beam steering in the OPA may require arbitrary phase shifts. This is further complicated by the mismatch and crosstalk between the phase shifter channels and the optical waveguides connecting them.

[0053] iii) Switch the next ground bus (m = m + 1) to ground 45, for example, by closing the second switch SW2 and opening all other switches.

[0054] iv) Transfer phase shifter 10 from non-volatile memory M,N All DAC channels (e.g., voltage or current) in all N rows are updated with the corresponding values ​​in column m+1 and the optional p-th directional direction (DACn(m, p)).

[0055] v) Repeat steps iii) and iv) until phase shifter 10 M,N Each column of phase shifters in other columns 10 M,N Cut off (e.g., disconnect switch SW1 to SW) M At the same time, it has been switched from SW1 to SW M Sequential conduction.

[0056] vi) Steps i) to v) can be repeated, while updating the turning direction p during this infinite loop to turn the beam into a new direction.

[0057] The method can be executed cyclically via controller processor 40, so that the time to execute one cycle of the cycle through steps i to v is faster than the thermal time constant of heater 22. Thus, although not all heaters 22 can be driven simultaneously, their temperatures will not fluctuate significantly, and the phase shifter 10... M,N The phase shift will be relatively constant. The faster steps i to v are executed, the slower the thermal time constant, and the smaller the ripple in the phase shift.

[0058] refer to Figure 5 , Figure 6A , Figure 6B , Figure 7A and Figure 7B 10 for each phase shifter M,N An optical waveguide 50 may be comprised of multiple optical waveguide sections 51, which may be straight and parallel to each other, and are wired adjacent to the heater 22 in a serpentine manner. Each end of these optical waveguide sections is connected by an optical waveguide bend 52 for guiding light back through a subsequent waveguide section 51. Figure 2A and Figure 2BThe implementation scheme shown is similar, phase shifter 10 M,N The system includes a substrate 54 (e.g., silicon) adjacent to a lower cladding layer 55 (e.g., silicon dioxide), an optical waveguide layer 56 including multiple optical waveguide portions 51, and an upper cladding layer 57 above the waveguide layer 56. The heater 22 can be integrated into a waveguide material strip within the optical waveguide layer 56, but other heater arrangements are also possible, such as heaters 22 on the side of waveguides 50 within the same waveguide material layer 56, or heaters 22 made of metal or ceramic material embedded in the upper cladding layer 57. Figure 6A and Figure 6B In the embodiment shown, the optical waveguide 50 includes at least six waveguide portions 51 extending parallel to the heater 22.

[0059] The function of diode 23 is to prevent the signal from each digital-to-analog converter DAC1 to DAC2 from entering the circuit. N The current flows through each row R1 to R N The wire trace or channel 35 in the phase shifter 10 M,N The selected column flows into phase shifter 10 M,N Other unselected columns. Therefore, for all digital-to-analog converters DAC1 to DAC2... N The reverse bias breakdown voltage of diode 23 should always be higher than the maximum drive voltage.

[0060] Connecting the on-chip heater 22 to the external PN diode 23 will reduce the power efficiency caused by the inherent built-in potential of the diode 23, which is typically around 0.7V for silicon PN devices. When the heater 22 is forward biased, the series-connected PN diode 23 will consume power equal to i total ×V turn-on A constant DC power, which generates heat, where i total It is the total current flowing through diode 23 and heater 22, and V turn-on This is the forward voltage of PN diode 23. In addition, there is a series resistance associated with PN diode 23, which also consumes power and generates heat. (The last sentence appears to be incomplete and unrelated to the preceding text.) M,N In the physically separated configuration, the power dissipation in diode 23 is heat and does not cause optical effects. Silicon is mentioned throughout the disclosure, but other materials, such as other optical waveguide materials, are also within the scope of this invention.

[0061] By placing it 10 units closer to each phase shifter M,NThe pn diode 23 is integrated as part of the heater (diode heater) 22, which can improve power efficiency, meaning that heat that would otherwise be wasted also helps to heat the optical waveguide portion 51. Therefore, the heater 22 may include an on-chip heater with an integrated pn diode 23. The heater 22 may include long heating portions of two heavily doped waveguide materials (e.g., silicon) of opposite polarities (p and n). The pn diode 23 may be sandwiched in the middle along the shorter edges of the two heating portions, wherein the p-doped portion may be connected to the anode of the pn diode 23, and the n-side heating portion is connected to the cathode of the pn transistor 23. An exemplary diode heater 22 and equivalent circuit are shown in Figure 8. The diode heater 22 may include three main parts: 1) a p-doped anode 41, for example, with a doping level of 5e16 1 / cm. 3 up to 5e18 1 / cm 3 1) Silicon; 2) pn diode 23, for example, silicon; and 3) n-doped cathode 42, for example, with a doping level of 5e161 / cm. 3 up to 5e18 1 / cm 3 The pn diode 23 may be sandwiched between, for example, a longer heavily p-doped portion 43 and a longer heavily n-doped portion 44 of silicon, wherein the longer heavily p-doped portion 43 comprises a doped material with a higher p-doping concentration than the p-part of the p-diode 23, and the longer heavily n-doped portion 44 comprises an n-doped material with a higher n-doping concentration than the n-part of the pn diode 23. The heavily p-doped portion 43 (e.g., p+ silicon) may be connected to the anode 41 of the pn diode 23, and the heavily n-doped portion 44 (e.g., n+ silicon) may be connected to the cathode 42 of the pn diode 23. The heavily p-doped portion 43 or the heavily n-doped portion 44 may also include a silicide layer formed on top to further reduce its resistivity. Silicide formation is a standard process commonly used in silicon photonics foundries to form ohmic contacts between silicon and metal.

[0062] Since the series resistance of the pn diode 23 is typically very small, the length, width, and sheet resistivity of the heavily p-doped portion 43 and the heavily n-doped portion 44 dominate the overall resistance of the diode heater 22. The reverse breakdown voltage of the pn diode 23 can be adjusted by changing the intrinsic region L. i The length is adjusted to determine the intrinsic region L. i The larger the value, the greater the breakdown voltage of the pn diode 23. However, the longer the intrinsic region L... i This requires increasing the series resistance, which may result in uneven heating of most of the center of the pn diode 23. This uneven heating will reduce thermo-optical efficiency. The p-doped portion L in pn diode 23... p and n-doped portion L pThe length will also change the conduction characteristics and series resistance of the pn diode 23. The anode contact 47 and cathode contact 48 can be placed at opposite distal ends of the diode heater 22 connected to the heavily p-doped portion 43 and the heavily n-doped portion 44, respectively, to minimize heat dissipation, which will also reduce the efficiency of the heater 22. The interfaces between the anode contact 47 and cathode contact 48 and the p-doped portion 43 and the heavily n-doped portion 44 can each have a silicide layer to ensure ohmic contact.

[0063] Anode and cathode contacts 47 and 48 can both be formed on the outermost edge of heater 22 for electrical connection. The width W of heater 22... heater The thickness can range from 0.2 μm to 10 μm. Heavy doped silicon portion L p+ and L n+ The length is ideally between 10 μm and 1000 μm. The p-doped portion L in pn diode 23 p and n-doped L n The length can be between 0 and 2 μm. The intrinsic region L in the pn diode 23... i The length is ideally between 20 nm and 2 μm. In some implementations, the intrinsic region L of diode 23... i This can be omitted, and the p and n doped portions can be in direct contact. Ideally, the pn junction is placed close enough to the phase shifter 10. M,N The waveguide portion 51 is heated by power dissipated on the pn junction, causing a phase shift in the light transmitted therein. Heaters 22 can be placed in an array adjacent to the waveguide portions 51, and each waveguide portion 51 can be a single waveguide or a ridge waveguide. The gap (on both sides) between the heaters 22 and the waveguide portions 51 can be between 0.4 μm and 2 μm.

[0064] like Figures 6A to 7B As shown, optical phase shifter 10 M,N This can be achieved through a relatively high thermo-optic coefficient in the optical waveguide material (e.g., silicon), which can be approximately 10 times that of the cladding layers 55 and 57 (e.g., silicon nitride). With such a thermo-optic coefficient, the refractive index of the optical waveguide material (e.g., silicon) will change with temperature. Therefore, by placing the diode heater 22 very close to the waveguide portion 51, for example, adjacent in the same waveguide layer 56, when a forward bias is applied and current flows through the diode heater 22, the local temperature around the diode heater 22 (including the optical waveguide portion 51) will increase, causing a change in the refractive index in the waveguide material. Light passing through the heated waveguide portion 51 will then experience an additional phase shift. Since the waveguide portion 51 and the diode heater 22 can be fabricated on the same waveguide layer 56 and integrally formed with the same waveguide (e.g., silicon) layer 56, a planar layer (e.g., silicon) connecting the diode heater 22 and the optical waveguide portion 51 can also be present to improve thermal conductivity. Figure 7A However, the gap and its size between the diode heater 22 and the waveguide portion 51 can be carefully selected to: 1) avoid excessive loss, and 2) reduce optical coupling between the optical waveguide portion 51 and the diode heater 22.

[0065] Heater 22 can also be used to heat the alternative serpentine phase shifter 10. M,N For example, as disclosed in U.S. Patent Application 16 / 826051, filed March 20, 2020, in the name of the applicant of this application, which is incorporated herein by reference. This allows for the simultaneous heating of multiple adjacent waveguide sections 51 that are directly or indirectly adjacent to or near the heater 22.

[0066] Thermal phase shifter 10 M,N The implementation scheme can be arranged in a serpentine manner, thereby increasing the total length of the waveguide heated by a single heater 22. By routing the light in this way, so that the light passes under or near the same heater 22 several times, some of the heat that would otherwise be wasted can be recovered. This results in an increase in phase shift associated with the increase in the heated length of the waveguide, without increasing the length of the heater 22 or the power consumption.

[0067] However, there are limitations associated with placing additional optical waveguide sections below or near heater 22, for example, in a serpentine arrangement. Typically, the optical waveguide sections 51 must be spaced several micrometers apart to eliminate light leakage between adjacent optical waveguide sections 51. This typically requires a spacing of several micrometers, meaning that the temperature variation of the optical waveguide sections 51 farther from the center of heater 22 is significantly less than that of any waveguide section 51 closer to the center of heater 22. This limits the number of passes under or near heater 22 and the ultimate efficiency gain of the technique.

[0068] While serpentine arrangements of waveguides have been previously proposed for thermal phase shifter constructions, they have not addressed the constraints limiting the efficiency gain of this technique. For example, some systems have proposed waveguides arranged in a serpentine manner to improve efficiency and minimize power consumption. However, these waveguides all use the same cross-section; for example, they have the same width, which limits the number of passes under the heater.

[0069] refer to Figure 9A and Figure 9B Phase shifter 10 M,NThe waveguide may include optical waveguide portions 320, 322, 324, 326, and 328, which may be straight and parallel to each other, passing in a serpentine manner below or near the heater or heating element 312. Each of the optical waveguide portions 320, 322, 324, 326, and 328 includes a different width, or at least adjacent optical waveguide portions 320, 322, 324, 326, and 328, or at least waveguides spaced at least twice the pitch, include different widths, such that the waveguide portions 320, 322, 324, 326, and 328 have weak coupling to each other, and can therefore be placed closer together below the heating element 312. Similar to... Figure 6B and Figure 7B The implementation scheme shown, Figure 9A and Figure 9B Phase shifter 10 M,N The cladding includes a substrate 314 (e.g., silicon) adjacent to a cladding layer (e.g., silicon dioxide). The cladding layer may include a lower cladding layer 315 and an upper cladding layer 316 located below and above the optical waveguide portions 320, 322, 324, 326, and 328, respectively. A heating element 312 may be mounted on top of or within the upper cladding layer 316, but other heater arrangements are also possible. Figure 9A and Figure 9B In the illustrated embodiment, five waveguide portions 320, 322, 324, 326, and 328 extend below the heating element 312. Each of the waveguide portions 320, 322, 324, 326, and 328 may include different propagation constants (n). i For example, the varying widths (w0) of all or part of the waveguide portions (e.g., waveguide portions 320, 322, 324, 326, and 328) or the area surrounding the cladding (e.g., upper cladding 316, lower cladding 315, or adjacent to the waveguide portions). i Different thicknesses, different doping concentrations, or different material refractive indices result in adjacent parallel waveguide sections having different propagation constants, which can reveal and / or increase wave vector mismatch between adjacent straight parallel waveguide sections, thereby reducing coupling between them.

[0070] Figure 10A simple serpentine routing scheme connecting five straight waveguide sections 512, 514, 516, 518, and 520 is illustrated. This routing scheme requires (N-1) bends for the N channels passing through the heated section, each bend comprising a radius of curvature (or bend radius), for example, half the waveguide pitch. However, arranging the paths of waveguide sections 512, 514, 516, 518, and 520 in a tightly packed serpentine structure requiring a bend radius of half the waveguide pitch (below 400 nm) can lead to problems because silicon channel waveguides typically only tolerate bend radii as small as 1 μm–2 μm without causing significant optical losses at the bends.

[0071] Figure 11 A spiral routing scheme for connecting five waveguide sections 532, 534, 536, 538, and 540 is shown, where some bends, such as the first and last outer bends, have larger radii (e.g., 1.5 times the waveguide pitch or greater than 1 μm), and some bends, such as the second and third inner bends, have smaller radii (e.g., 0.5 times the waveguide pitch or 1 / 3 of the larger radius). Figure 10 Compared to the routing schemes shown, Figure 11 The spiral route shown adds some radii to the bends, but still requires a minimum radius of half the waveguide pitch. This is an arrangement of 5 bends / 4 bends. More generally, for N bends, the first and last bends can have the largest radii, the second and penultimate bends can have smaller radii, the third and penultimate bends can have even smaller radii, and so on, such that bend [i] and bend [N-i+1] have the same radius. Another conceptual approach is to... Figure 11 It can be viewed as a waveguide "wound" around itself around the central heater.

[0072] Figure 12 and Figure 13 A phase shifter 10 including waveguide 574 is shown. M,NWaveguide 574 includes multiple straight parallel waveguide sections (e.g., five waveguide sections 552, 554, 556, 558, and 560), wherein the curved sections allow the waveguide pitch in the active heater region to be much lower than a minimum bending radius (e.g., less than 800 nm), allowing the five waveguide sections 552, 554, 556, 558, and 560 to be closely spaced together. The curved sections may include a first bend extending at least 180°, followed by one or more second bends including sections bending in the opposite direction to the first bend. For example, each curved section may include a circular bend 564 with a larger radius (e.g., 180°) combined with an S-curve 565 (e.g., a bending radius greater than 1 μm) to restore a narrow waveguide pitch (e.g., less than 800 nm). The S-curve may include a recess extending from the 180° bend, and a recess extending between the recess and the next waveguide section. The curved portions can be nested. For example, since waveguide portions 552, 554, 556, 558, and 560 are of different lengths and not adjacent to each other, portions of each 180° bend 564 can be arranged in a nested configuration parallel to portions (e.g., recesses) of each adjacent S-curve 565. Therefore, the total width of the phase shifter 550 will not be much greater than twice the bending radius (e.g., 2 μm), which is important for reducing the total chip area consumed by the phase shifter 550. The bend 564 may include a circular portion, a semi-circular portion, etc. Figure 12 ) part or oval ( Figure 13 In other words, the large-radius 180° bend is used to arrange the long, straight, parallel portions of waveguide sections 552, 554, 556, 558, and 560 as closely as possible together. When further combined with varying waveguide widths, the combination of the large-radius 180° bend 564 and the S-curve 565 in this arrangement allows waveguide sections 552, 554, 556, 558, and 560 to be placed closer together than previously allowed. Figure 13 This shows the case of the chip. Figure 12 The diagram shows a curved routing scheme with an S-curve, and a portion of a serpentine waveguide 574 extending below the heater 572 within the chip 576.

[0073] Another embodiment of the phase shifter 550 includes a bend 564, which includes a local bend radius that gradually and smoothly (e.g., adiabatically) varies along the propagation length of the bend 564. This can be achieved by ensuring that the minimum local bend radius is never less than a predetermined selection value r. min r minA typical value of 2 μm is used to minimize radiation bending loss in waveguide 574. Using this smoothing technique, bend 564 can be extended with a concave bend of angle (180+x) degrees, then with a convex bend of angle (-x) degrees, such that the waveguide exiting bend 564 is parallel to the waveguide entering bend 564, but offset from the waveguide by a distance below heater 572. The transition from concave to convex bends depends particularly on the smoothing of the local bending radius to minimize optical loss. The local bending radius R, as a function of propagation length L, can follow various forms, such as linear (R∝mL) or hyperbolic tangent (R∝tanh(L)). Furthermore, the width of the waveguide portion before or after the large-radius bend typically decreases gradually from the width of the preceding waveguide to the width of the following waveguide, such that the waveguide width remains constant within bend 564. Traditional phase shifters rely heavily on very small bend radii to densely pack waveguides beneath the heater, and because the waveguides all use the same cross-section, there are limitations on how tightly they can be packed together. In other words, those waveguides are plagued by large minimum bend radii and large minimum waveguide-to-waveguide pitches. In contrast, the embodiments of this disclosure (e.g., thermal phase shifter 550) do not have these problems because they allow for a much tighter packing of waveguides, waveguide-to-waveguide pitches (e.g., less than 800 nm, preferably less than 700 nm), whereas most methods may only require 2 μm without the need for tight bends.

[0074] Due to the serpentine phase shifter 10 M,N While the chip's heating zone is traversed multiple times, the escape waveguide 8 only traverses it once. Therefore, considering only thermal attenuation, the escape waveguide 8 effectively receives less thermal crosstalk than if it were not arranged this way. Thus, the escape waveguide 8 can be arranged more efficiently than two serpentine phase shifters 10. M,N The required distance between them is closer to other serpentine phase shifters. M,N In other words, the serpentine phase shifter 10 M,N The spacing between the waveguide 8 and the escape waveguide 8 can be less than that between two serpentine phase shifters 10. M,N The spacing between them is because the escape waveguide 8 is less sensitive to temperature changes and thermal crosstalk. The efficiency gained by making multiple close passes is multiplied (e.g., for a five-channel phase shifter 10). M,N Up to nearly 5 times (allowing for a smaller spacing). Therefore, in each phase shifter 10 M,N Arranging a certain number of escape waveguides 8 between each row will not increase the area of ​​the array. Therefore, each escape waveguide 8 can be arranged in each row of phase shifters 10. M,N The adjacent phase shifters 10 in front of and behind M,N The paths are arranged between them, so that the outgoing waveguide 8 is positioned relative to the adjacent phase shifter 10. M,NAnd get closer to each other.

[0075] The above description of one or more embodiments of the present invention is for descriptive and illustrative purposes only. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible based on the above teachings. The scope of the invention is not limited by this detailed description, but rather by the appended claims.

Claims

1. An optical phased array device, comprising: An optical phase shifter array, comprising multiple rows of optical phase shifters and multiple columns of optical phase shifters; A plurality of digital-to-analog converters, each of which is configured to output an independent voltage or current to one of the multi-row optical phase shifters; Multiple ground buses, each of which is configured to connect one of the multiple optical phase shifters to a common ground; A multiplexer configured to selectively connect one of the plurality of ground buses to the common ground while disconnecting the other ground buses from the plurality of ground buses; processor; and Non-volatile memory used to store instructions, which, when executed by the processor: Select one of the multiple optical phase shifters in sequence to connect to the common ground, while disconnecting any other ground bus from the multiple ground buses; and The voltage or current of each of the plurality of digital-to-analog converters is updated as the basis for selecting one of the plurality of optical phase shifters.

2. The device according to claim 1, wherein, Each optical phase shifter in the optical phase shifter array includes: Optical waveguide; and A heater for heating the optical waveguide to change its refractive index.

3. The device according to claim 2, wherein, Each anode of each heater in the same row of the multi-row optical phase shifters is connected to a common digital-to-analog converter; and In this configuration, each cathode of each heater in the same column of the multiple optical phase shifters is connected to a corresponding ground bus among the multiple ground buses.

4. The device according to claim 2, wherein, Each heater in each optical phase shifter in the optical phase shifter array is connected in series with a corresponding diode, which is configured to prevent current from flowing to other optical phase shifters in the same row.

5. The device according to claim 4, wherein, The absolute reverse breakdown voltage of each of the respective diodes is greater than the maximum drive voltage of each of the plurality of digital-to-analog converters.

6. The device according to claim 4, wherein, Each of the respective diodes is integrated with one of the optical phase shifters on the same chip.

7. The device according to claim 6, wherein, Each of the diodes is selected from the group consisting of silicon PN diodes, silicon PIN diodes, Schottky diodes, and germanium diodes.

8. The device according to claim 2, wherein, Each of the heaters comprises a resistive material selected from the group consisting of titanium nitride, nickel-chromium alloy, heavily doped silicon, silicide, titanium, and tungsten.

9. The device according to claim 1, wherein, The multiplexer includes a plurality of electrical switches, each of which is configured to selectively connect one of the plurality of ground buses to the common ground.

10. The device according to claim 9, wherein, Each of the electrical switches includes an N-type field-effect transistor configured to provide a low-resistance path to ground and a low built-in voltage across each of the electrical switches, thereby maintaining each of the plurality of ground buses at a lower voltage relative to each of the plurality of digital-to-analog converters.

11. The device according to claim 2, wherein, The optical waveguide includes multiple parallel waveguide sections adjacent to each other in the waveguide layer of the photonic integrated circuit, and multiple waveguide bends connecting the multiple parallel waveguide sections.

12. The device according to claim 11, wherein, The optical waveguide comprises an optical waveguide material, and each of the heaters comprises the waveguide material in the waveguide layer and is doped with P and / or N-type materials.

13. The device according to claim 12, wherein, Each heater in each optical phase shifter in the optical phase shifter array is connected in series with a corresponding diode, which is configured to prevent current from flowing to other optical phase shifters in the same row. and Each of the respective diodes includes a PN junction integrated with the respective heater.

14. The device according to claim 11, wherein, Adjacent parallel waveguide sections have different propagation constants, resulting in wave vector mismatch between adjacent straight parallel waveguide sections, thereby attenuating the coupling between them.

15. The device according to claim 14, wherein, Each of the plurality of parallel waveguide sections has a different width.

16. The device according to claim 11, wherein, The plurality of waveguide bending portions include a first bending portion and a final bending portion having a first bending radius, and a second bending portion and a third bending portion having a second bending radius, wherein the second bending radius is smaller than the first bending radius.

17. The device according to claim 16, wherein, The second bending radius is equal to half the waveguide pitch of the plurality of parallel waveguide sections, and the first bending radius is at least three times the second bending radius.

18. The device according to claim 11, wherein, Each of the plurality of waveguide bends includes a first bend that extends at least 180°, and a second bend that follows the first bend, the second bend including a portion that bends in the opposite direction to the first bend.

19. The device according to claim 18, wherein, Each of the first bends comprises a 180° circular bend, and each of the second bends comprises an S-shaped bend.

20. The device according to claim 19, wherein, Each of the first bend and each of the second bend includes a gradually changing local bend radius; and wherein the local bend radius is never lower than a predetermined minimum value.

21. The device according to claim 18, wherein, Each of the plurality of parallel waveguide sections comprises a different length, and the plurality of waveguide bends are thus arranged in staggered, non-adjacent positions.

22. The device according to claim 21, wherein, A portion of each of the first bends is parallel to the parallel portion of each of the second bends in the adjacent waveguide bends.

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