Array substrate, preparation method thereof and display panel

Abstract

An array substrate, a manufacturing method thereof and a display panel, the yield of the array substrate is high, and the production cost is low. The array substrate comprises a plurality of touch units (1) arranged in an array on a substrate (20); the first electrodes (3) of all sub-pixels in each touch unit (1) are electrically connected; a plurality of driving electrode lines, at least part of the orthographic projection of the driving electrode lines on the substrate (20) is arranged between the orthographic projections of two adjacent rows of the first electrodes (3) on the substrate (20) and is electrically connected with at least one first electrode (3); in the two adjacent rows of the first electrodes (3), each row of the first electrodes (3) is arranged along the direction in which the driving electrode lines are arranged; the driving electrode lines comprise at least one break; at least one isolation via (5) is arranged at the junction (S1) of two adjacent touch units (1) arranged along the direction in which the driving electrode lines are arranged and exposes the break of the driving electrode lines; at least one isolation insulation part (6) is arranged in the isolation via (5) and fills the isolation via (5).

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a display panel. BACKGROUND

[0002] With the rapid development of touch display screen technology and the increasing demand of the market for touch display screen, touch display technology has become an indispensable part of human-computer interaction and is widely used in education, business, finance, service and other industries.

[0003] At present, the capacitive touch screen designed based on In Cell Touch technology has the characteristics of low production cost, high stability, and relatively optimal touch technology effect, and occupies the mainstream market. The In Cell Touch technology sets the touch electrode inside the display panel, which requires high pixel design, resulting in many problems of bad detection and maintenance, thereby greatly reducing the yield and increasing the production cost, which is not conducive to product promotion. SUMMARY

[0004] Embodiments of the present application provide an array substrate, a preparation method thereof and a display panel, the yield of the array substrate is high, and the production cost is low.

[0005] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0006] In one aspect, an array substrate is provided, which includes:

[0007] a substrate;

[0008] a plurality of touch units arranged in an array on the substrate, the touch units including a plurality of sub-pixels arranged in an array; the sub-pixels including a first electrode; the first electrodes of all the sub-pixels in each touch unit are electrically connected; the first electrode is configured to serve as a driving electrode in a display phase and a touch sensing electrode in a touch phase;

[0009] a plurality of driving electrode lines, at least part of the projection of the driving electrode lines on the substrate is arranged between the projections of two adjacent rows of the first electrodes on the substrate and is electrically connected to at least one of the first electrodes; in the two adjacent rows of the first electrodes, each row of the first electrodes is arranged along the direction in which the driving electrode lines are located; the driving electrode lines include at least one break, the break of the driving electrode lines is located at the junction of two adjacent touch units arranged along the direction in which the driving electrode lines are located; the driving electrode lines are configured to transmit a driving signal in the display phase and a touch signal in the touch phase;

[0010] At least one isolation via is arranged at the junction of two adjacent touch control units arranged along the direction of the driving electrode lines and exposes the disconnected part of the driving electrode lines;

[0011] At least one isolation insulating part is arranged in the isolation via and fills the isolation via.

[0012] Optionally, the driving electrode lines comprise first electrode lines; the isolation vias comprise first vias; and the isolation insulating parts comprise first insulating parts.

[0013] The first electrode lines are arranged along a first direction and are parallel to a row of first electrodes arranged along a second direction, at least part of the projection of the first electrode lines on the substrate is arranged between the projections of two adjacent rows of the first electrodes on the substrate along the first direction and is electrically connected to the same row of the first electrodes; the first electrode lines comprise disconnected parts, the disconnected parts of the first electrode lines are located at the junction of any two adjacent touch control units arranged along the second direction; and the second direction intersects the first direction.

[0014] The first vias are arranged at the junction of two adjacent touch control units arranged along the second direction and expose the disconnected parts of the first electrode lines.

[0015] The first insulating parts are arranged in the first vias and fill the first vias.

[0016] Optionally, the array substrate further comprises an alignment layer covering the plurality of touch control units.

[0017] The alignment layer and the first insulating parts are an integral structure.

[0018] Optionally, the array substrate further comprises an alignment layer arranged on the side of the touch control units away from the substrate and covering the plurality of touch control units.

[0019] The first insulating parts comprise a first insulating sub-part and a second insulating sub-part, the first insulating sub-part is located at the disconnected part of the first electrode lines, and the second insulating sub-part is arranged on the side of the first insulating sub-part away from the substrate.

[0020] The alignment layer and the second insulating sub-part are an integral structure.

[0021] Optionally, the driving electrode lines comprise second electrode lines; the isolation vias comprise second vias; and the isolation insulating parts comprise second insulating parts.

[0022] The second electrode lines are arranged along the second direction, and a projection of the second electrode lines on the substrate is arranged between projections of two adjacent first electrode lines arranged along the second direction and electrically connected to at least one first electrode belonging to the same touch unit.

[0023] The second via is arranged at a boundary between two adjacent touch units arranged along the first direction and exposes the broken part of the second electrode line; and the second via and the first via do not overlap along a direction perpendicular to a plane in which the substrate is arranged.

[0024] The second insulating part is arranged in the second via and fills the second via.

[0025] Optionally, the array substrate further comprises an alignment layer covering the plurality of touch units.

[0026] The alignment layer and the second insulating part are an integral structure.

[0027] Optionally, the array substrate further comprises a substrate and an alignment layer, the alignment layer being arranged on a side of the touch units away from the substrate and covering the plurality of touch units.

[0028] The second insulating part comprises a third insulating subpart and a fourth insulating subpart, the third insulating subpart being arranged at the broken part of the second electrode line, and the fourth insulating subpart being arranged on a side of the third insulating subpart away from the substrate.

[0029] The alignment layer and the fourth insulating subpart are an integral structure.

[0030] Optionally, the broken parts of the plurality of second electrode lines are arranged along the second direction, and the plurality of second vias are arranged along the second direction.

[0031] Optionally, the sub-pixel further comprises a transistor and a second electrode.

[0032] The transistor does not overlap with the first electrode line, the first electrode and the second electrode line along a direction perpendicular to a plane in which the substrate is arranged; and the transistor comprises a gate, a first electrode and a second electrode.

[0033] A projection of the second electrode on the substrate at least partially overlaps with a projection of the first electrode on the substrate; the second electrode is electrically connected to the first electrode and is configured to form an electric field with the first electrode in a display stage.

[0034] Optionally, the array substrate further comprises:

[0035] a plurality of gate lines arranged along the first direction, a projection of the gate line on the substrate is arranged between projections of two adjacent rows of the first electrodes on the substrate along the first direction and is electrically connected with the gate of the transistor in the same row; the gate line and the first electrode line do not overlap along a direction perpendicular to a plane on which the substrate lies.

[0036] Optionally, the array substrate further comprises:

[0037] a plurality of data lines arranged along the second direction, a projection of the data line on the substrate is arranged between projections of two adjacent rows of the first electrodes on the substrate along the second direction and is electrically connected with the second electrode of the transistor in the same row; the data line and the second electrode line do not overlap along a direction perpendicular to a plane on which the substrate lies.

[0038] Optionally, the gate line and the first electrode line are arranged in the same layer; the data line, the first electrode and the second electrode are arranged in the same layer.

[0039] Optionally, the transistor is a bottom-gate transistor; the first electrode line is overlapped with one side of the first electrode in the same row;

[0040] The array substrate further comprises a gate insulating layer, a first passivation layer and a second passivation layer; the gate insulating layer covers the gate line, the first electrode line and a portion of the first electrode which is not covered by the first electrode line; the first passivation layer covers the data line and the gate insulating layer; the second passivation layer covers the second electrode line and the first passivation layer;

[0041] The first via penetrates the first electrode line, the gate insulating layer, the first passivation layer and the second passivation layer; the second via penetrates the second electrode line and the second passivation layer.

[0042] Optionally, the sub-pixel further comprises a plurality of connection electrodes, the connection electrodes are arranged in the same layer as the second electrode;

[0043] The plurality of first electrode lines are divided into a first group and a second group, the first electrode lines in the first group and the first electrode lines in the second group are arranged alternately along the first direction;

[0044] The connection electrodes are configured to electrically connect the first electrode electrically connected with the first electrode line in the first group and the first electrode electrically connected with the first electrode line in the second group adjacent to the first group.

[0045] In another aspect, a display panel is provided, comprising the above array substrate.

[0046] In still another aspect, a method for manufacturing an array substrate is provided, comprising:

[0047] forming a plurality of first electrodes arranged in an array;

[0048] forming a plurality of drive electrode lines;

[0049] forming a plurality of to-be-detected lines, the to-be-detected lines comprising gate lines and / or data lines;

[0050] detecting the to-be-detected lines;

[0051] forming a plurality of isolation vias and a plurality of isolation insulating portions in a case where the detection state of the to-be-detected lines is normal, the isolation vias being arranged at the junctions of adjacent two touch control units arranged along the direction in which the drive electrode lines are arranged and causing the drive electrode lines to be disconnected at the positions of the isolation vias, and the isolation insulating portions being arranged in the isolation vias and filling the isolation vias.

[0052] Optionally, the forming of the plurality of drive electrode lines comprises forming a plurality of first electrode lines arranged along a first direction.

[0053] The forming of the plurality of isolation vias and the plurality of isolation insulating portions in the case where the detection state of the to-be-detected lines is normal comprises:

[0054] adopting an etching process to remove the film layer at the junctions of adjacent two touch control units arranged along the second direction and expose the portions of the first electrode lines that need to be disconnected;

[0055] adopting a wet etching process to remove the portions of the first electrode lines that need to be disconnected and form first vias;

[0056] adopting a one-time patterning process to form first insulating portions and an alignment layer.

[0057] Optionally, the forming of the plurality of drive electrode lines comprises forming a plurality of first electrode lines arranged along a first direction.

[0058] The forming of the plurality of isolation vias and the plurality of isolation insulating portions in the case where the detection state of the to-be-detected lines is normal comprises:

[0059] adopting an etching process to remove the film layer at the junctions of adjacent two touch control units arranged along the second direction and expose the portions of the first electrode lines that need to be disconnected;

[0060] adopting an oxygen-containing gas etching process to remove the portions of the first electrode lines that need to be disconnected and form first vias and first insulating sub-portions;

[0061] adopting a one-time patterning process to form second insulating sub-portions and an alignment layer.

[0062] Optionally, the forming the plurality of driving electrode lines further comprises: forming a plurality of second electrode lines arranged along the second direction;

[0063] The method further comprises:

[0064] detecting the second electrode lines in the case that the first electrode lines are continuously arranged;

[0065] forming a plurality of second vias and a plurality of second insulating portions in the case that the detection state of the second electrode lines is normal; wherein the second via is arranged at the junction of two adjacent touch control units arranged along the first direction and makes the second electrode line disconnected at the position of the second via; the second via and the first via do not overlap along the direction perpendicular to the plane of the substrate; and the second insulating portion is arranged in the second via and fills the second via.

[0066] Optionally, the forming the plurality of second vias and the plurality of second insulating portions in the case that the detection state of the second electrode lines is normal comprises:

[0067] adopting an etching process to remove the film layer at the junction of two adjacent touch control units arranged along the first direction and expose the part of the second electrode line that needs to be disconnected;

[0068] adopting a wet etching process to remove the part of the second electrode line that needs to be disconnected and form a second via;

[0069] adopting a one-time patterning process to form a second insulating portion and an alignment layer.

[0070] Alternatively, the forming the plurality of second vias and the plurality of second insulating portions in the case that the detection state of the second electrode lines is normal comprises:

[0071] adopting an etching process to remove the film layer at the junction of two adjacent touch control units arranged along the first direction and expose the part of the second electrode line that needs to be disconnected;

[0072] adopting an oxygen-containing gas etching process to remove the part of the second electrode line that needs to be disconnected and form a second via and a third insulating sub-portion;

[0073] adopting a one-time patterning process to form a fourth insulating sub-portion and an alignment layer.

[0074] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the following detailed description can be implemented according to the content of the specification, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following detailed description of the present application is given. BRIEF DESCRIPTION OF DRAWINGS

[0075] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without creative labor.

[0076] Figure 1 A structural schematic diagram of a display panel is schematically shown;

[0077] Figure 2 A structural schematic diagram of an array substrate is schematically shown;

[0078] Figure 3 For Figure 2 A first kind of partial enlarged view of the middle region M is shown;

[0079] Figure 4 In the preparation process of the array substrate shown in a-d of FIG. 1, the following steps are included: Figure 3 A structural schematic diagram of a preparation process of the array substrate shown in a-d of FIG. 1 is shown;

[0080] Figure 5 In the preparation process of the array substrate shown in a-d of FIG. 1, the following steps are included: Figure 3 Another structural schematic diagram of a preparation process of the array substrate shown in a-d of FIG. 1 is shown;

[0081] Figure 6 For Figure 2 A second kind of partial enlarged view of the middle region M is shown;

[0082] Figure 7 In the preparation process of the array substrate shown in a-d of FIG. 1, the following steps are included: Figure 6 A structural schematic diagram of a preparation process of the array substrate shown in a-d of FIG. 1 is shown;

[0083] Figure 8 In the preparation process of the array substrate shown in a-d of FIG. 1, the following steps are included: Figure 6 Another structural schematic diagram of a preparation process of the array substrate shown in a-d of FIG. 1 is shown;

[0084] Figure 9 For Figure 2 A third kind of partial enlarged view of the middle region M is shown;

[0085] Figure 10 For Figure 2 A fourth kind of partial enlarged view of the middle region M is shown;

[0086] Figure 11 A cross-sectional schematic diagram along E1E2 is shown; Figure 10 A cross-sectional schematic diagram along F1F2 is shown;

[0087] Figure 12 A cross-sectional schematic diagram along F1F2 is shown; Figure 10 A cross-sectional schematic diagram along F1F2 is shown;

[0088] Figure 13 Figure 2 The fifth type of magnified view of region M; and

[0089] Figure 14 Figure 2 The sixth magnified view of the central region M. Specific Implementation

[0090] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0091] In the embodiments of this application, the terms "first", "second", "third", "fourth" are used to distinguish the same or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0092] In the embodiments of this application, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly defined.

[0093] In the embodiments of this application, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0094] This application provides an array substrate, combined with... Figures 1-4 As shown in 6 and 7, including:

[0095] Substrate 20; the material of the substrate is not limited, but for example, it can be a rigid material, such as glass.

[0096] Multiple arrays arranged on substrate 20, such as Figure 1 The touch unit 1 shown includes multiple sub-pixels arranged in an array; reference Figure 2 As shown, a sub-pixel includes a first electrode 3; the first electrodes of all sub-pixels in each touch unit are electrically connected; the first electrode is configured to be used as a driving electrode in the display phase and as a touch sensing electrode in the touch phase.

[0097] Multiple driving electrode lines are provided, with at least a portion of the orthographic projection of the driving electrode lines on the substrate disposed between the orthographic projections of two adjacent rows of first electrodes on the substrate and electrically connected to at least one first electrode; in the two adjacent rows of first electrodes, each row of first electrodes is arranged along the direction of the driving electrode lines; the driving electrode lines include at least one break, the break of the driving electrode lines being located at the junction of two adjacent touch units arranged along the direction of the driving electrode lines; the driving electrode lines are configured to transmit driving signals during the display phase and touch signals during the touch phase.

[0098] At least one isolation via is provided at the junction of two adjacent touch units arranged along the direction of the drive electrode line, and exposes the break in the drive electrode line.

[0099] At least one insulating part is disposed within the insulating via and fills the insulating via.

[0100] The aforementioned driving electrode lines may include, for example: Figure 3 and Figure 6 The first electrode line 4 and / or the second electrode line 8 are shown.

[0101] In this array substrate, to reduce the difficulty of implementing In-Cell Touch, the first electrode can be time-division multiplexed. That is, the first electrode is used as a driving electrode in the display stage to drive the liquid crystal deflection; and in the touch stage, it is used as a touch sensing electrode to form a touch capacitance with the finger to achieve the touch effect.

[0102] The aforementioned array substrate can be applied to either ADS (Advanced Super Dimension Switch) or HADS type liquid crystal touch displays, without limitation. Compared to ADS type liquid crystal touch displays, HADS type liquid crystal touch displays were developed to further improve the aperture ratio. The biggest difference between ADS and HADS types lies in the different electrode positions of the common electrode (Com electrode) and pixel electrode (Pixel electrode). If the array substrate is applied to an ADS type touch display, the first electrode can be called the common electrode, and the first electrode line can be called the common electrode line; if the array substrate is applied to an HADS type liquid crystal touch display, the first electrode can be called the pixel electrode, and the first electrode line can be called the pixel electrode line. Taking ADS type as an example, in related ADS type array substrates, the common electrode is generally a single electrode of the same size as the substrate. However, in the array substrate provided in this application, the first electrode of each sub-pixel is independently set, and multiple first electrodes belonging to the same touch unit are electrically connected.

[0103] The size of the array substrate is not limited, and the array substrate can be applied to a UHD (Ultra High Definition) display device or a HD (High Definition) display device with a large size or an ultra-large size (for example, 86 inches), or a UHD display device or a HD display device with a small size (for example, 23.6 inches).

[0104] The isolation insulating part insulates the parts of the driving electrode line respectively located in the regions of two adjacent touch units. The material of the isolation insulating part is not limited.

[0105] The driving electrode line includes the first electrode line and / or the second electrode line. Since the first electrode line and / or the second electrode line are provided with at least one break, if the driving electrode line with the break is directly formed, the precision of the mask is required to be high, and static electricity is easily generated, the film forming quality is reduced, and finally, the product yield is reduced. In the present application, the driving electrode line provided continuously is first formed, and then the isolation via and the isolation insulating part are provided to make the driving electrode line break at the junction of two adjacent touch units arranged along the driving electrode line. In this way, the mask with low precision can be used to form the driving electrode line, so that the static electricity is avoided, the film forming quality is improved, and the product yield is improved. The array substrate provided in the present application has high yield and low production cost.

[0106] In one or more embodiments, the driving electrode line includes a first electrode line; the isolation via includes a first via; the isolation insulating part includes a first insulating part; and the first electrode line is electrically connected to the first via. Figures 1-4 The array substrate includes the following structures as shown in FIGS. 1, 6 and 7.

[0107] A substrate 20; the material of the substrate is not limited, and for example, the substrate can be a rigid material such as glass.

[0108] A plurality of touch units 1 arranged in an array on the substrate 20; each touch unit includes a plurality of sub-pixels arranged in an array. Figure 1 The sub-pixel includes a first electrode 3; the first electrodes of all the sub-pixels in each touch unit are electrically connected; the first electrode is configured to serve as a driving electrode in a display stage and serve as a touch sensing electrode in a touch stage. Figure 2 The sub-pixel includes a first electrode 3; the first electrodes of all the sub-pixels in each touch unit are electrically connected; the first electrode is configured to serve as a driving electrode in a display stage and serve as a touch sensing electrode in a touch stage.

[0109] A plurality of first electrode lines 4 arranged along a first direction (OA direction) as shown in FIG. 1; the first electrode lines 4 are parallel to a row of first electrodes 3 arranged along a second direction (OB direction) as shown in FIG. 1. Figure 2 The first electrode line 4 is parallel to a row of first electrodes 3 arranged along a second direction (OB direction) as shown in FIG. 1; at least a part of the orthogonal projection of the first electrode line 4 on the substrate is arranged in the first direction (OA direction) as shown in FIG. 1. Figure 2 The first electrode line 4 is parallel to a row of first electrodes 3 arranged along a second direction (OB direction) as shown in FIG. 1; at least a part of the orthogonal projection of the first electrode line 4 on the substrate is arranged in the first direction (OA direction) as shown in FIG. 1. Figure 2 The first electrode line 4 is parallel to a row of first electrodes 3 arranged along a second direction (OB direction) as shown in FIG. 1; at least a part of the orthogonal projection of the first electrode line 4 on the substrate is arranged in the first direction (OA direction) as shown in FIG. 1. Figure 2The first electrode line is arranged in the OA direction (as shown) between the orthographic projections of two adjacent rows of first electrodes 3 onto the substrate, and electrically connected to the first electrodes 3 in the same row; the first electrode line includes multiple breaks, and the breaks of the first electrode line are located at the junction of any two adjacent touch units arranged along the second direction; that is, the first electrode line 4 is located along the second direction (… Figure 2 The boundary between any two adjacent touch units arranged in the OB direction (as shown) Figure 2 (Marked as S1) Disconnected; the second direction intersects the first direction; the first electrode line is configured to transmit a drive signal during the display phase and a touch signal during the touch phase.

[0110] Multiple such as Figure 4 Chinese C diagram and Figure 7 The first via 5 shown in Figure C, combined with Figure 3 and Figure 4 The middle C diagram or combination Figure 6 and Figure 7 As shown in Figure c, the first via 5 is located along the second direction ( Figure 3 The junction of two adjacent touch units arranged in the OB direction (as shown) and the break point of the first electrode line 4 exposed. Figure 4 Figure C shows the route along Figure 3 A schematic diagram of the cross-section of E1E2. Figure 7 Figure C shows the route along Figure 6 A schematic diagram of the cross-section of E1E2.

[0111] Multiple such as Figure 4 The middle d diagram and Figure 7 The first insulating part 6 shown in the middle d figure is disposed in the first through hole 5 and fills the first through hole 5.

[0112] It should be noted that along the first direction (e.g.) Figure 1 The multiple touch units 1 arranged in the OA direction (as shown) can be the same size or different sizes; no limitation is made here. For ease of wiring, along the second direction (e.g., Figure 1 The multiple touch units arranged in the OB direction shown are of the same size. Figure 1 In the illustration, the size of the touch unit located in the middle along the first direction is different from the size of the touch units located on the top and bottom sides. The specific number of sub-pixels included in the above touch units is not limited and can be selected according to the actual situation.

[0113] The aforementioned first electrode line is electrically connected to the first electrodes in the same row. The specific implementation of this electrical connection is not limited here; it is merely an example. Figure 3 and Figure 4As shown in Figure d, the first electrode line 4 and the first electrodes 3 in the same row can be electrically connected through direct contact; or, the first electrode line and the first electrodes in the same row can be electrically connected through multiple connection units; the specific connection can be determined according to the design structure.

[0114] refer to Figure 2 As shown, the first electrode line 4 described above is along the second direction ( Figure 2 The boundary between any two adjacent touch units arranged in the OB direction (as shown) Figure 2 The first electrode line is disconnected (marked as S1), meaning that the first electrode line is discontinuous as a whole, while the part located in the area where the touch unit is located is continuous. Figure 2 The illustration is based on an example that includes four touch units: Sensor1, Sensor2, Sensor3, and Sensor4.

[0115] The first electrode described above can be configured as a strip electrode, and the first direction can be as follows: Figure 2 As shown in the OA direction (i.e., the direction of the long side of the first electrode), the second direction can be as follows: Figure 2 The OB direction shown (i.e., the direction of the short side of the first electrode). Alternatively, the first direction can also be as follows: Figure 2 As shown in the OB direction (i.e., the direction of the short side of the first electrode), the second direction can be as follows: Figure 2 The OA direction is shown (i.e., the direction of the long side of the first electrode). This is not limited here. Figures 1-3 The illustrations are all based on the example of the first direction being the OA direction and the second direction being the OB direction.

[0116] The first via corresponds to the break point of the first electrode line; the film layer traversed by the first via is not limited here, and needs to be determined based on the design structure. For example, refer to... Figure 4 As shown in Figure C, the first via 5 can penetrate the second passivation layer 22, the first passivation layer 21, the gate insulating layer (GI layer) 19 and the first electrode line 4, thereby exposing the break in the first electrode line.

[0117] The aforementioned first insulating portion keeps the portions of the first electrode line located in the areas of two adjacent touch units insulated. The material of the first insulating portion is not limited here. Figure 4 The middle d diagram and Figure 7 Figures d and d show the structure of a first insulating part.

[0118] To ensure touch functionality, the first electrode line is disconnected at the junction of any two adjacent touch units arranged along the second direction. In related technologies, this is combined with... Figure 9 and Figure 11As shown, the Vcom line is discontinuous, so the array substrate including this structure cannot normally load test signals during detection, thereby failing to detect related traces (e.g., gate lines, data lines, etc.), and further failing to detect a series of defects such as GCS (gate line and electrode short circuit defect), DCS (data line and electrode short circuit defect), TCS (touch control line and electrode short circuit defect), TTS (touch control line and touch control line short circuit defect), TOP (touch control line and electrode open circuit defect), and TGS (touch control line and gate line short circuit defect), thereby failing to repair the defects, further reducing product yield, causing a large waste of materials, production capacity, and manpower, and sharply increasing production cost.

[0119] The array substrate provided in the present application can be prepared as follows during preparation: Figure 13 As shown, the first electrode line 4 is first formed in a continuous manner, and after detection and repair of related traces (e.g., gate lines, data lines, and touch control lines) are completed, the first electrode line is disconnected at the junction of any two adjacent touch control units arranged in the second direction by arranging a plurality of first vias and a plurality of first insulating portions. This can ensure detection and repair of defects and also ensure implementation of touch control functions. The array substrate provided in the present application has high yield and low production cost.

[0120] The specific structure of the first insulating portion is described below.

[0121] The present application provides a specific structure of the first insulating portion, in order to reduce the difficulty of manufacturing and simplify the structure, with reference to Figure 4 As shown in FIG. d, the array substrate further includes an alignment layer 7 covering a plurality of touch control units; and the alignment layer 7 and the first insulating portion 6 are integrated. It should be noted that the liquid crystal display panel can include an array substrate, a color film substrate, and a liquid crystal layer arranged between the array substrate and the color film substrate. When the above array substrate is applied to the liquid crystal display panel, the liquid crystal has fluidity, and in order to ensure that the initial orientation of the liquid crystal is consistent, alignment layers are arranged on both sides of the liquid crystal layer. Therefore, the above array substrate can further include an alignment layer.

[0122] The materials of the above alignment layer and the first insulating portion are not limited, and for example, both can include PI (polyimide). In this structure, the material of the first insulating portion is the same as that of the alignment layer. Of course, the first insulating portion and the alignment layer can also be made of different materials and be separately manufactured; considering simplifying the manufacturing process, the alignment layer and the first insulating portion can be integrated, in which case the same material is used.

[0123] The present application provides another specific structure of the first insulating portion, in order to reduce the difficulty of manufacturing and simplify the structure, with reference to Figure 7As shown in FIG. 1D, the array substrate further comprises an alignment layer 7, which is disposed on the side of the touch control unit away from the substrate and covers the plurality of touch control units.

[0124] Reference is made to Figure 7 As shown in FIG. 1D, the first insulating part 6 comprises a first insulating sub-part 11 and a second insulating sub-part 12, the first insulating sub-part 11 is located at the broken part of the first electrode line 4, and the second insulating sub-part 12 is disposed on the side of the first insulating sub-part 11 away from the substrate 20; wherein the alignment layer 7 and the second insulating sub-part 12 are an integral structure.

[0125] The materials of the alignment layer and the first insulating sub-part are not limited, for example, both of them can comprise PI (polyimide). The material of the second insulating sub-part is not limited, for example, the material of the second insulating sub-part comprises a metal oxide chelate, such as a copper oxide chelate, which has the characteristics of high impedance and non-conductivity. In this structure, the material of the first insulating sub-part is the same as that of the alignment layer, and the material of the second insulating sub-part is different from that of the first insulating sub-part.

[0126] Of course, the first insulating sub-part and the alignment layer can also be made of different materials and be separately manufactured. Considering the simplification of the manufacturing process, the alignment layer and the first insulating sub-part can be an integral structure, in which case the same material is used.

[0127] In one or more embodiments, the driving electrode line comprises a second electrode line; the isolation via comprises a second via; the isolation insulating part comprises a second insulating part; and the array substrate further comprises:

[0128] a plurality of second electrode lines 4 arranged along a second direction (OB direction) as shown in FIG. 1D, with reference to Figure 1 As shown in FIG. 1D, the array substrate further comprises an alignment layer 7, which is disposed on the side of the touch control unit away from the substrate and covers the plurality of touch control units. Figure 1 Figure 3 As shown in FIG. 1D, the array substrate further comprises an alignment layer 7, which is disposed on the side of the touch control unit away from the substrate and covers the plurality of touch control units. Figure 6 As shown in FIG. 1D, the array substrate further comprises an alignment layer 7, which is disposed on the side of the touch control unit away from the substrate and covers the plurality of touch control units. Figure 3 As shown in FIG. 1D, the array substrate further comprises an alignment layer 7, which is disposed on the side of the touch control unit away from the substrate and covers the plurality of touch control units. Figure 6 As shown in FIG. 1D, the array substrate further comprises an alignment layer 7, which is disposed on the side of the touch control unit away from the substrate and covers the plurality of touch control units.

[0129] a plurality of second electrode lines 4 arranged along a second direction (OB direction) as shown in FIG. 1D, with reference to Figure 5 As shown in FIG. 1D, the array substrate further comprises an alignment layer 7, which is disposed on the side of the touch control unit away from the substrate and covers the plurality of touch control units. Figure 8 As shown in FIG. 1D, the array substrate further comprises an alignment layer 7, which is disposed on the side of the touch control unit away from the substrate and covers the plurality of touch control units. Figure 3 As shown in FIG. 1D, the array substrate further comprises an alignment layer 7, which is disposed on the side of the touch control unit away from the substrate and covers the plurality of touch control units.​Figure 5 As shown in Figure d or in combination Figure 6 and Figure 8 As shown in Figure d, the second via 9 is located at the junction of two adjacent touch units arranged along the first direction (OA direction) and exposes the break in the second electrode line 8; the second via and the first via do not overlap in the direction perpendicular to the plane of the substrate.

[0130] Multiple such as Figure 5 China e-graph and Figure 8 The second insulating part 10 shown in Figure e is disposed within the second through hole 9 and fills the second through hole 9.

[0131] To meet the touch functionality requirements, refer to Figure 1 As shown, the aforementioned multiple second electrode lines 4 are electrically connected to multiple touch units 1 in a one-to-one correspondence. When this array substrate is applied to a liquid crystal touch display screen, the multiple touch units are equivalent to multiple touch sensing electrode blocks (Touch Sensors), as shown in the reference. Figure 1 As shown, each touch unit 1 can be electrically connected to the first driver chip 23 via the second electrode line 4. The first driver chip may include a TDDI COF (Touch Display Driver Chip). The TDDI COF can provide data signals to the second electrode line during the display phase, receive touch signals transmitted by the second electrode line during the touch phase, and then locate the coordinates of the touch occurrence through the Touch MCU (Touch Microprocessor), and perform corresponding processing actions according to the touch commands issued by the user.

[0132] The specific number of first electrodes electrically connected to the second electrode line is not limited. To improve reliability and simplify the design, the second electrode line can be electrically connected to two first electrodes belonging to the same touch unit. Furthermore, the specific implementation method of the electrical connection between the second electrode line and the first electrode is not limited here. For example, the second electrode line and the first electrode can be electrically connected through connecting electrodes; the specific method can be determined according to the design structure.

[0133] The aforementioned second electrode line is interrupted at the junction of two adjacent touch units arranged along the first direction, meaning the second electrode line is discontinuous overall, but the portion within the touch unit area is continuous. The number of second electrode lines between two adjacent rows of first electrodes arranged along the second direction is not limited and can be determined based on the number of touch units. Figure 3 and Figure 6 The example shown is a second electrode line between two adjacent rows of first electrodes arranged along the second direction.

[0134] In order to balance the touch performance and cost, the second electrode line can be provided with a break; in order to facilitate the split screen driving, the breaks of the plurality of second electrode lines are arranged along the second direction, and the break is located at the middle position of the array substrate (i.e. the substrate is divided into Figure 1 two regions of L1 and L2 as shown), so as to realize the up-down split screen control along the first direction (i.e. the OA direction) as shown. Figure 1

[0135] The second via hole corresponds to the break of the second electrode line; here, the film layer through which the second via hole penetrates is not limited, and is determined according to the design structure. For example, as shown in Figure 5 , the second via hole 9 can penetrate the second passivation layer 22 and the second electrode line 8, so as to expose the break of the second electrode line 8.

[0136] The second insulating part makes the parts of the second electrode line respectively located in the regions of the adjacent two touch units remain insulated, and the material of the second insulating part is not limited. Figure 5 , and Figure 8 respectively show the structure of a second insulating part.

[0137] The second electrode line transmits the touch signal in the touch stage, and therefore, the second electrode line can also be called a touch line (Touch Line), abbreviated as TX line. In a large-size liquid crystal touch screen, in order to realize the timely response of touch, the split screen control technology is usually used, and then the second electrode line is required to be broken at the boundary of the adjacent two touch units arranged along the first direction. In the related technology, as shown in Figure 10 and Figure 12 , the TX line is discontinuous, and then in the detection process of the array substrate including this structure, the test signal of the second electrode line is difficult to be detected, so that the abnormal sub-pixel can be detected, but the feedback of the detection signal is the abnormality of the touch unit to which the abnormal sub-pixel belongs, and then it is difficult to accurately locate the defect, so that the defect cannot be repaired, further reducing the product yield and increasing the production cost.

[0138] The array substrate provided in the present application can be combined with Figure 13 and 14 in the preparation process.As shown, the first electrode line 4 and the second electrode line 8 are formed in succession, and after the detection and maintenance of the second electrode line are completed, the first electrode line is disconnected at the junction of any two adjacent touch control units arranged along the second direction by arranging a plurality of first vias, a plurality of second vias, a plurality of first insulating portions and a plurality of second insulating portions, and the second electrode line is disconnected at the junction of two adjacent touch control units arranged along the first direction; in this way, on the one hand, the detection of defects and accurate positioning and maintenance can be ensured, and on the other hand, the realization of touch control function and split-screen control can be ensured. The array substrate provided by the present application has fast touch response speed, high yield and low production cost.

[0139] The specific structure of the second insulating portion will be described below.

[0140] The present application provides a structure of the second insulating portion, in order to reduce the difficulty of manufacturing and simplify the structure, referring to Figure 5 As shown in FIG. 1e, the array substrate further comprises an alignment layer 7 covering a plurality of touch control units; wherein the alignment layer 7 and the second insulating portion 10 are an integral structure.

[0141] The materials of the alignment layer and the second insulating portion are not limited, and for example, both can comprise PI (polyimide). In this structure, the material of the second insulating portion is the same as that of the alignment layer.

[0142] It should be noted that the first insulating portion and the alignment layer are an integral structure, and the alignment layer and the second insulating portion are an integral structure, that is, the first insulating portion, the second insulating portion and the alignment layer are an integral structure. Of course, the second insulating portion and the alignment layer can also be made of different materials and be made separately; considering the simplification of the manufacturing process, the alignment layer and the second insulating portion can be an integral structure, and in this case, the same material is used.

[0143] The present application provides another structure of the second insulating portion, in order to reduce the difficulty of manufacturing and simplify the structure, referring to Figure 5 As shown in FIG. 1e, the array substrate further comprises an alignment layer 7 arranged on the side of the touch control unit away from the substrate and covering a plurality of touch control units.

[0144] Referring to Figure 5 As shown in FIG. 1e, the second insulating portion 10 comprises a third insulating sub-portion 13 and a fourth insulating sub-portion 14, the third insulating sub-portion 13 is located at the disconnected position of the second electrode line 8, and the fourth insulating sub-portion 14 is arranged on the side of the third insulating sub-portion 13 away from the substrate 20; wherein the alignment layer 7 and the fourth insulating sub-portion 22 are an integral structure.

[0145] The materials of the alignment layer and the fourth insulator are not limited; for example, both may include PI (polyimide). The material of the third insulator is not limited; for example, the material of the third insulator includes a metal oxide chelate, such as a copper oxide chelate, which has high impedance and is non-conductive. In this structure, the material of the fourth insulator is the same as the material of the alignment layer, while the material of the third insulator is different from the material of the fourth insulator.

[0146] Of course, the fourth insulator and the alignment layer can also be made of different materials and manufactured separately; to simplify the manufacturing process, the alignment layer and the fourth insulator can be integrated into one structure, in which case the same material is used for both.

[0147] It should be noted that the second insulator section and the alignment layer are an integral structure, and the alignment layer and the fourth insulator section are an integral structure; that is, the second insulator section, the fourth insulator section, and the alignment layer are all integrated into a single structure. The materials of the third insulator section and the first insulator section can be the same or different; there is no limitation here. To reduce manufacturing difficulty, the former is chosen.

[0148] In one or more embodiments, in order to balance touch performance and cost, the second electrode line is provided with a break point; at the same time, in order to facilitate split-screen driving, the break points of multiple second electrode lines are arranged along the second direction, and multiple second vias are arranged along the second direction.

[0149] The break in the second electrode line can be located in the middle of the array substrate (i.e., the substrate is divided into sections). Figure 1 (as shown in regions L1 and L2), thus achieving the following Figure 1 The above-mentioned vertical split-screen control is shown along the first direction (i.e., the OA direction); of course, the break point of the second electrode line can also be located at other positions on the array substrate, which is not limited here.

[0150] In one or more embodiments, reference is made to Figure 3 and Figure 6 As shown, the sub-pixel also includes a transistor 15 and a second electrode 16; wherein, the transistor 15, along a direction perpendicular to the plane of the substrate, does not overlap with the first electrode line 4, the first electrode 3, and the second electrode line 8; the transistor includes a gate, a first electrode, and a second electrode.

[0151] The orthographic projection of the second electrode 16 on the substrate at least partially overlaps with the orthographic projection of the first electrode 3 on the substrate; the second electrode 16 is electrically connected to the first electrode 151 and is configured to form an electric field with the first electrode during the display phase.

[0152] The transistor includes a gate, a source and a drain, one of the source and the drain is referred to as a first electrode, and the other is referred to as a second electrode. The transistor can be a P-type thin film transistor or an N-type thin film transistor, which is not limited herein. Of course, the transistor can also include an active layer, and the material of the active layer can be single crystal silicon, or amorphous silicon, or polycrystalline silicon, for example, LTPS (Low Temperature Poly-silicon), or an oxide semiconductor material, for example, IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IZO (Indium Zinc Oxide), etc.

[0153] According to the positional relationship of the electrodes, the transistor can be divided into two categories: one is that the gate is located below the source and the drain, which is referred to as a bottom-gate transistor; and the other is that the gate is located above the source and the drain, which is referred to as a top-gate transistor. The transistor in the present application can be a bottom-gate transistor or a top-gate transistor. When the array substrate is applied to a liquid crystal touch screen, since the liquid crystal itself cannot emit light, the liquid crystal touch screen also includes a backlight module, and the light emitted by the backlight module is emitted to the liquid crystal through the array substrate, and the number of light emitted is controlled by adjusting the deflection angle of the liquid crystal, and finally different pictures are displayed. Since the active layer of the transistor is easily affected by light, if a bottom-gate transistor is used, the gate can block the light emitted to the active layer, thereby protecting the active layer to some extent, and thereby improving the performance of the transistor. Figure 3 and Figure 6 The bottom-gate transistor is taken as an example for illustration.

[0154] If the array substrate is applied to an ADS type touch display screen, the first electrode can be referred to as a common electrode, and the second electrode can be referred to as a pixel electrode; if the array substrate is applied to an HADS type liquid crystal touch display screen, the first electrode can be referred to as a pixel electrode, and the second electrode can be referred to as a common electrode.

[0155] In the display stage, the voltage of the second electrode can be controlled by the transistor, and thereby the size of the electric field between the first electrode and the second electrode is controlled. When the array substrate is applied to a liquid crystal touch display screen, the electric field generated by the first electrode and the second electrode can cause the liquid crystal to deflect, and by changing the size of the electric field, the deflection angle of the liquid crystal is changed, thereby controlling the number of light emitted, and finally different pictures are displayed.

[0156] Optionally, referring to Figure 3 and Figure 6As shown, the array substrate further comprises: a plurality of gate lines 17 arranged along the first direction (OA direction), the orthogonal projection of the gate line 17 on the substrate is arranged between the orthogonal projections of the first electrodes 3 in two adjacent rows arranged along the first direction on the substrate, and is electrically connected with the gate of the transistor in the same row; the gate line 17 and the first electrode line 4 do not overlap in the direction perpendicular to the plane where the substrate is located.

[0157] The above-mentioned gate line and the second electrode line overlap in the direction perpendicular to the plane where the substrate is located, so that a parasitic capacitance is generated between the overlapping parts of the two, thereby affecting the signal quality. In order to reduce the parasitic capacitance, a hollow area H as shown can be arranged in the gate line, that is, some areas of the part of the gate line overlapping with the second electrode line are hollowed out, so as to reduce the overlapping area of the two, and thereby reduce the parasitic capacitance. Figure 13

[0158] The above-mentioned gate of the transistor can be the part of the gate line overlapping with the active layer of the transistor in the direction perpendicular to the plane where the substrate is located; or it can also be arranged separately; in order to save space and improve the aperture ratio, the former can be selected. Figure 3 Figure 6 The former is taken as an example for illustration.

[0159] The array substrate can control the voltage of the gate of the transistor in the same row through the gate line, and thereby control whether the transistor in the same row is turned on or off, so as to control the voltage of the second electrode.

[0160] Optionally, as shown in Figure 3 Figure 6 As shown, the array substrate further comprises: a plurality of data lines 18 arranged along the second direction (OB direction), the orthogonal projection of the data line 18 on the substrate is arranged between the orthogonal projections of the first electrodes 3 in two adjacent rows arranged along the second direction on the substrate, and is electrically connected with the second electrode 152 of the transistor in the same row; the data line and the second electrode line do not overlap in the direction perpendicular to the plane where the substrate is located.

[0161] The above-mentioned data line, the first electrode and the second electrode of the transistor can be arranged in the same layer, or can also be arranged separately, which is not limited here. In order to save the number of patterning processes and reduce the production cost, the former can be selected.

[0162] The array substrate can provide a data voltage to the second electrode of the transistor in the same row through the data line, and thereby provide a voltage to the second electrode.

[0163] Optionally, in order to save the number of patterning processes and reduce the production cost, the gate line and the first electrode line are arranged in the same layer; the data line, the first electrode and the second electrode are arranged in the same layer.

[0164] ​​​The aforementioned single-layer setup refers to a process using a single patterning process. A single patterning process refers to the process of forming the required layer structure through a single exposure. A single patterning process includes processes such as masking, exposure, development, etching, and stripping.

[0165] Optionally, the transistor is a bottom-gate transistor; the first electrode line overlaps with one side of the first electrode in the same row.

[0166] refer to Figure 4 As shown in Figure c, the array substrate also includes a gate insulating layer 19, a first passivation layer 21, and a second passivation layer 22; combined with Figure 4 Chinese C diagram and Figure 5 As shown in Figure c, the gate insulating layer 19 covers the gate line 17, the first electrode line 4, and the portion of the first electrode 3 not covered by the first electrode line 4; the first passivation layer 21 covers the data line 18 and the gate insulating layer 19; and the second passivation layer 22 covers the second electrode line 8 and the first passivation layer 21.

[0167] refer to Figure 4 As shown in Figure c, the first via 5 penetrates the first electrode line 4, the gate insulating layer 19, the first passivation layer 21, and the second passivation layer 22; (Reference) Figure 5 As shown in Figure d, the second via 9 passes through the second electrode line 8 and the second passivation layer 22.

[0168] refer to Figure 4 As shown in Figure c, the first electrode line 4 is in direct contact with one side of the first electrode 3 in the same row, thereby achieving electrical connection between the two.

[0169] The relative positional relationship between the first electrode line and the first electrode is not limited. For example, the first electrode line is farther away from the substrate relative to the first electrode; or the first electrode line is closer to the substrate relative to the first electrode. Figure 4 The former is used as an example to illustrate the diagram in Figure c.

[0170] The aforementioned transistor comprises a gate, an active layer, and an electrode layer stacked sequentially. The electrode layer includes a first electrode and a second electrode. To prevent the active layer and the gate from interfering with each other, a gate insulating layer is also disposed between the active layer and the gate. The aforementioned first passivation layer (also known as the PVX1 layer) may also cover the first electrode and the second electrode. The aforementioned second passivation layer (also known as the PVX2 layer) may be made of the same material as the first passivation layer, or it may be made of a different material. To save costs, it may be made of the same material, such as silicon nitride, silicon oxide, or silicon oxynitride. Silicon nitride is generally chosen.

[0171] The array substrate has a simple structure and is easy to implement.

[0172] Optionally, the first electrode includes, for example, Figure 2 The plate-shaped electrode shown, the second electrode includes, as... Figure 3The strip electrodes are shown, so that a multi-dimensional electric field can be formed between the first electrode and the second electrode, and the liquid crystal deflection is more conducive to control.

[0173] Reference is made to Figure 3 As shown, the second electrode 16 can include a plurality of parallel strip electrodes, and the adjacent strip electrodes have a slit therebetween, and the same end of all the strip electrodes are connected together.

[0174] In one or more embodiments, reference is made to Figure 2 As shown, the sub-pixel further includes a plurality of connection electrodes 30, and the connection electrodes are arranged in the same layer as the second electrode.

[0175] The plurality of first electrode lines are divided into a first group and a second group, and the first electrode lines of the first group and the first electrode lines of the second group are arranged alternately along the first direction; and the connection electrodes are configured to electrically connect the first electrodes connected with the first electrode lines of the first group and the first electrode lines of the second group adjacent to the first group.

[0176] Here, the number of the connection electrodes is not limited, for example, the adjacent two rows of the first electrodes can be electrically connected through one connection electrode; in order to improve the reliability, reference is made to Figure 2 As shown, the adjacent two rows of the first electrodes can also be electrically connected through two connection electrodes.

[0177] The connection electrodes are arranged in the same layer as the second electrode, reference is made to Figure 2 As shown, the connection electrodes 30 can be electrically connected with the first electrodes 3 through first connection vias (the small black dots 31 shown in the figure overlap with the first electrodes), and are connected with the first electrode lines 4 through second connection vias (the small black dots 32 shown in the figure overlap with the first electrode lines). Figure 1 Figure 1 It should be noted that the adjacent two touch units arranged along the first direction are independent of each other and do not have an electrical connection relationship. In actual production, the connection electrodes are correspondingly arranged between any adjacent two rows of the first electrodes arranged along the first direction; in order to avoid the electrical connection of the first electrodes of the adjacent two touch units, only the first connection vias can be arranged, or only the second connection vias 32 are arranged in the S2 region shown in the figure, so that the connection electrodes corresponding to the region between the adjacent two touch units are disabled.

[0178] It should be noted that the adjacent two touch units arranged along the first direction are independent of each other and do not have an electrical connection relationship. In actual production, the connection electrodes are correspondingly arranged between any adjacent two rows of the first electrodes arranged along the first direction; in order to avoid the electrical connection of the first electrodes of the adjacent two touch units, only the first connection vias can be arranged, or only the second connection vias 32 are arranged in the S2 region shown in the figure, so that the connection electrodes corresponding to the region between the adjacent two touch units are disabled. Figure 2

[0179] In the array substrate, the adjacent two rows of the first electrodes are electrically connected through the connection electrodes, so that the first electrodes of all the sub-pixels in the touch unit are electrically connected. This structure is simple and easy to implement, and is also conducive to saving space and increasing the aperture ratio.

[0180] The embodiments of the present application also provide a display panel including the array substrate. ​​

[0181] The display panel can be an ADS type or HADS type liquid crystal touch display panel, and any product or component with display function such as a television, a digital camera, a mobile phone, a tablet computer, etc. comprising the display panel. The display panel has the characteristics of high yield, fast response speed, low cost, excellent display picture, etc.

[0182] Embodiments of the present application further provide a preparation method of an array substrate, the structure of which can refer to Figure 3 and Figure 6 The method comprises the following steps:

[0183] S01, as shown in Figure 13 a plurality of first electrodes 3 arranged in an array are formed on a substrate.

[0184] The material of the first electrode can comprise a transparent metal oxide, for example, ITO (Indium Tin Oxide, Indium Tin Oxide). The material of the substrate can be a rigid material, for example, glass.

[0185] S02, a plurality of driving electrode lines are formed.

[0186] The driving electrode lines can comprise first electrode lines and / or second electrode lines.

[0187] The driving electrode lines formed by step S02 are continuously arranged without being disconnected; the material thereof can comprise a metal, for example, copper, aluminum or silver, etc.

[0188] S03, a plurality of to-be-detected lines are formed, the to-be-detected lines comprising gate lines and / or data lines.

[0189] The to-be-detected lines can comprise gate lines; or, the to-be-detected lines can comprise data lines; or, the to-be-detected lines can comprise gate lines and data lines.

[0190] S04, the to-be-detected lines are detected.

[0191] It should be noted that if the to-be-detected lines comprise gate lines, step S04 means detecting the gate lines. Since the driving electrode lines are continuously arranged, the test signal can be normally loaded, so the detection of the gate lines can be realized, and GCS type defects can be detected, so that the defects can be repaired and the product yield can be improved.

[0192] If the to-be-detected lines comprise data lines, step S04 means detecting the data lines. Since the driving electrode lines are continuously arranged, the test signal can be normally loaded, so the detection of the data lines can be realized, and DCS type defects can be detected, so that the defects can be repaired and the product yield can be improved.

[0193] If the to-be-detected lines include the gate lines and the data lines, step S04 refers to detecting the gate lines and the data lines. Since the driving electrode lines are continuously arranged, the test signals can be normally loaded, so that the detection of the gate lines and the data lines can be realized, and the GCS type and DCS type defects can be detected, so that the defects can be repaired and the product yield can be improved. It should be noted that the gate lines and the data lines generally need to be formed by two processes, and step S04 can include two detections. For example, if the gate lines are formed first and then the data lines are formed, the gate lines can be detected after the gate lines are formed. Then, the data lines are formed, and the data lines are detected after the data lines are formed.

[0194] S05, in the case that the detection state of the to-be-detected lines is normal, forming a plurality of isolation vias and a plurality of isolation insulation parts; wherein the isolation via is arranged at the junction of the adjacent two touch control units arranged along the driving electrode line direction, and the driving electrode line is disconnected at the position of the isolation via; the isolation insulation part is arranged in the isolation via and fills the isolation via.

[0195] It should be noted that if the to-be-detected lines include the gate lines, step S05 is executed in the case that the detection state of the gate lines is normal; if the to-be-detected lines include the data lines, step S05 is executed in the case that the detection state of the data lines is normal; if the to-be-detected lines include the gate lines and the data lines, step S05 is executed in the case that the detection state of the gate lines and the data lines is normal.

[0196] The execution order of the above steps S01-S03 is not limited, for example, it can be executed in the order of step S01, step S02, and step S03; or it can also be executed in the order of step S02, step S01, and step S03; or it can also be executed in the order of step S03, step S01, and step S02; of course, other execution orders are also possible, which will not be listed here.

[0197] The above step S04 can be executed only after steps S01-S03 are all executed. The above step S05 can be executed only after step S04 is executed. In addition, after step S04, if a defect occurs, the method can further include S041, repairing the defect; S042, detecting again after the repair; repeatedly S041 and S042 until the detection state of the to-be-detected lines is normal, and then continue to execute the subsequent steps.

[0198] Here, the specific method of forming the isolation via and the isolation insulation part is not limited.

[0199] By performing S01-S05, on one hand, the GCS and / or DCS bad can be guaranteed to be detected and repaired, so as to improve product yield and reduce production cost; on the other hand, the touch function can be guaranteed to be realized. The method is simple and easy to implement, and is conducive to mass production.

[0200] It should be noted that, in the above preparation method, the structure of the array substrate is described, which can be referred to the foregoing embodiments, and will not be described here.

[0201] The following provides a specific preparation method of the first via and the first insulating portion.

[0202] In one or more embodiments, S02, forming the plurality of drive electrode lines comprises: S021, referring to FIG. 2, forming the plurality of first electrode lines 4 arranged along the first direction. Figure 13 As shown in FIG. 2, the plurality of first electrode lines 4 arranged along the first direction are formed.

[0203] S05, in the case that the detection state of the to-be-detected line is normal, forming the plurality of isolation vias and the plurality of isolation insulating portions comprises:

[0204] S051, using an etching process to remove the film layer at the junction of the two adjacent touch units arranged along the second direction, and exposing the part of the first electrode line to be disconnected.

[0205] Specifically, a wet etching process or a dry etching process can be used, which is not limited here.

[0206] S052, using a wet etching process to remove the part of the first electrode line to be disconnected, and forming the first via; wherein the first via is arranged at the junction of the two adjacent touch units arranged along the second direction, and the first electrode line is disconnected at the position of the first via.

[0207] S053, using a one-time patterning process to form the first insulating portion and the alignment layer; wherein the first insulating portion is arranged in the first via and fills the first via.

[0208] By performing S051-S053, the first insulating portion and the alignment layer are formed as an integrated structure; at the same time, the first via is formed by two etching processes.

[0209] The following provides another specific preparation method of the first via and the first insulating portion.

[0210] In one or more embodiments, S02, forming the plurality of drive electrode lines comprises: S021, referring to FIG. 2, forming the plurality of first electrode lines 4 arranged along the first direction. Figure 13 As shown in FIG. 2, the plurality of first electrode lines 4 arranged along the first direction are formed.

[0211] S05, in the case that the detection state of the to-be-detected line is normal, forming the plurality of isolation vias and the plurality of isolation insulating portions comprises:

[0212] S055, removing the film layer at the junction of the two adjacent touch control units arranged along the second direction by using an etching process, and exposing the part of the first electrode line that needs to be disconnected.

[0213] S056, removing the part of the first electrode line that needs to be disconnected by using an oxygen-containing gas etching, and forming a first via and a first insulating sub.

[0214] Specifically, an etching gas with high oxygen content (for example: SF6 / O2) can be used for etching, and the first electrode line is made of metal such as copper, which will react with the above-mentioned etching gas to form a metal oxide chelate (for example: copper oxide chelate), which has the characteristics of high impedance and non-conductivity. The metal chelate can form the first insulating sub.

[0215] S057, forming a second insulating sub and an alignment layer by using a one-time patterning process.

[0216] By performing S055-S057, the first insulating part formed includes a first insulating sub and a second insulating sub, the first insulating sub is located at the disconnected part of the first electrode line, the second insulating sub is arranged on the side of the first insulating sub away from the substrate, the second insulating sub and the alignment layer are an integral structure; at the same time, the first via is formed by two etching processes.

[0217] In one or more embodiments, S02, forming a plurality of driving electrode lines further comprises: S06, forming a plurality of second electrode lines arranged along the second direction.

[0218] The preparation method of the above-mentioned array substrate further comprises: S07, detecting the second electrode line under the condition that the first electrode line is continuously arranged.

[0219] It should be noted that step S05 can be executed only after step S07 is executed, that is, when the second electrode line is detected, it is necessary to ensure that the first electrode line is in a continuous arrangement and not disconnected state. In this way, the series of TCS, TTS, TOP, TGS and other malfunctions can be detected and accurately positioned for repair.

[0220] In addition, after step S07, if a malfunction occurs, the method can further comprise S071, repairing the malfunction; S072, detecting again after repair; repeatedly S071 and S072 until the detection state of the second electrode line is normal, and then continue to execute the subsequent steps.

[0221] S08, forming a plurality of second vias and a plurality of second insulating portions in the case that the detection state of the second electrode line is normal; wherein the second via is arranged at the junction of the adjacent two touch control units arranged along the first direction and makes the second electrode line disconnected at the position of the second via; the second via and the first via do not overlap along the direction perpendicular to the plane where the substrate is located; and the second insulating portion is arranged in the second via and fills the second via.

[0222] It should be noted that the execution sequence of steps S06, S01, S03, S04 and S021 is not limited, for example, after the execution of steps S01, S03, S04 and S021 is completed, steps S06, S07, S05 and S08 are executed in sequence; or, after the execution of steps S01, S03, S04 and S021 is completed, steps S06, S07, S08 and S05 are executed in sequence; of course, other execution sequences are also possible, which will not be listed one by one here.

[0223] By executing steps S06-S08, on the one hand, the detection and accurate positioning of TCS, TTS, TOP, TGS and other series of malfunctions can be guaranteed, and on the other hand, the realization of touch function and split screen control can be guaranteed. The method is simple and easy to implement, and is conducive to mass production.

[0224] A specific preparation method of the second via and the second insulating portion is provided below.

[0225] S08, forming a plurality of second vias and a plurality of second insulating portions in the case that the detection state of the second electrode line is normal; wherein the second via is arranged at the junction of the adjacent two touch control units arranged along the first direction and makes the second electrode line disconnected at the position of the second via; the second via and the first via do not overlap along the direction perpendicular to the plane where the substrate is located; and the second insulating portion is arranged in the second via and fills the second via.

[0226] S081, using an etching process to remove the film layer at the junction of the adjacent two touch control units arranged along the first direction, and exposing the part of the second electrode line that needs to be disconnected.

[0227] Specifically, a wet etching process or a dry etching process can be used, which is not limited here.

[0228] S082, using a wet etching process to remove the part of the second electrode line that needs to be disconnected and form the second via.

[0229] S083, using a one-time patterning process to form the second insulating portion and the alignment layer.

[0230] By executing steps S081-S083, the second insulating portion and the alignment layer are formed as an integrated structure; at the same time, the second via is formed by two etching processes.

[0231] Another specific preparation method of the second via and the second insulating portion is provided below.

[0232] S08, in the case that the detection state of the second electrode line is normal, forming the plurality of second vias and the plurality of second insulating portions comprises:

[0233] S085, using an etching process to remove the film layer at the junction of the adjacent two touch control units arranged along the first direction, and expose the part of the second electrode line that needs to be disconnected.

[0234] Specifically, a wet etching process or a dry etching process can be used, which is not limited here.

[0235] S086, using oxygen-containing gas etching to remove the part of the second electrode line that needs to be disconnected, and form the second via and the third insulating sub-portion.

[0236] Specifically, an etching gas with high oxygen content (for example: SF6 / O2) can be used for etching, and the second electrode line is made of copper or other metals. The metal reacts with the above-mentioned etching gas to form a metal oxide chelate (for example: copper oxide chelate), which has the characteristics of high impedance and non-conductivity. The metal chelate can form the third insulating sub-portion.

[0237] S087, using a one-time patterning process to form the fourth insulating sub-portion and the alignment layer.

[0238] By performing steps S085-S087, the second insulating portion formed includes the third insulating sub-portion and the fourth insulating sub-portion, the third insulating sub-portion is located at the disconnected part of the first electrode line, the fourth insulating sub-portion is arranged on the side of the third insulating sub-portion away from the substrate, and the fourth insulating sub-portion and the alignment layer are integrated; at the same time, the second via is formed by twice etching.

[0239] Next, the structure shown in Figure 3 and Figure 6 is taken as an example to specifically explain the preparation method. The method comprises:

[0240] S100, referring to Figure 13 , forming a plurality of first electrodes 3 arranged in an array on the substrate.

[0241] Specifically, a layer of ITO film can be deposited on the substrate first, then a mask is arranged, then etching is performed, and finally the mask is stripped, so that the patterning is completed and the plurality of first electrodes arranged in an array is formed.

[0242] S101, referring to Figure 13 , forming a plurality of gate lines 17 arranged along the first direction and a plurality of first electrode lines 4 arranged along the first direction.

[0243] Specifically, the gate lines and the first electrode lines can be formed by a one-time patterning process, i.e., a metal film is deposited first, a mask is then arranged, etching is then performed, and finally the mask is peeled off, so as to complete the patterning and form a plurality of gate lines and a plurality of first electrode lines. The first electrode lines are parallel to a row of first electrodes arranged along the second direction, at least part of the orthographic projection of the first electrode lines on the substrate is arranged between the orthographic projections of the adjacent two rows of first electrodes on the substrate along the first direction, and the first electrode lines are overlapped with one side of the same row of first electrodes, i.e., the first electrode lines are electrically connected with the same row of first electrodes through direct contact. The orthographic projection of the gate lines on the substrate is arranged between the orthographic projections of the adjacent two rows of first electrodes on the substrate along the first direction, and the gate lines and the first electrode lines do not overlap along the direction perpendicular to the plane where the substrate is located.

[0244] The first electrode lines formed by step S101 are arranged continuously.

[0245] S102, detecting the gate lines.

[0246] Since the first electrode lines formed by step S101 are arranged continuously, the test signal can be normally loaded, and thus the GCS type defects can be detected, so that the defects can be repaired and the product yield can be improved.

[0247] S103, forming a gate insulating layer in the case where the detection state of the gate lines is normal.

[0248] Specifically, the gate insulating layer can be deposited, which covers the gate lines, the first electrode lines, and the portions of the first electrodes not covered by the first electrode lines.

[0249] S104, forming an active layer.

[0250] Specifically, the active layer is formed above the gate lines; for example, an amorphous silicon film and an ohmic contact film (wherein the ohmic contact film is an amorphous silicon film doped with N+ material) can be sequentially deposited, a mask is then arranged, etching is then performed, and finally the mask is peeled off, so as to form an amorphous silicon semiconductor layer and an ohmic contact layer, which are taken as an example to be described herein. The portion of the gate lines overlapped with the active layer along the direction perpendicular to the plane where the substrate is located is used as a gate electrode.

[0251] S105, forming a first electrode, a second electrode, and a data line.

[0252] Specifically, a metal film can be deposited first, a mask is then arranged, etching is then performed on the metal film, etching is then performed on the ohmic contact layer, and finally the mask is peeled off, so as to form the first electrode, the second electrode, and the data line; wherein the ohmic contact layer is arranged between the first electrode and the amorphous silicon semiconductor layer, the ohmic contact layer is also arranged between the second electrode and the amorphous silicon semiconductor layer, and the ohmic contact layers below the two are arranged separately.Figure 1 As shown, the data line is directly connected with the second pole of the U-shaped structure, realizing electrical connection.

[0253] S106, detecting the data line.

[0254] Since the first electrode line formed in step S101 is continuously arranged, the test signal can be normally loaded, and the DCS type defect can be detected, so that the gate insulating layer is formed in the case that the detection state of the gate line is normal. The defect is repaired, and the product yield is improved.

[0255] S107, forming a first passivation layer in the case that the detection state of the data line is normal.

[0256] Specifically, a silicon nitride material can be deposited to form the first passivation layer. The first passivation layer covers the data line, the gate insulating layer, the first pole and the second pole.

[0257] S108, forming a second electrode line.

[0258] The second electrode line formed in step S108 is continuously arranged, and the orthographic projection of the second electrode line on the substrate is arranged between the orthographic projections of the adjacent two rows of first electrodes arranged along the second direction on the substrate, and is electrically connected with at least one first electrode belonging to the same touch control unit.

[0259] S109, detecting the second electrode line.

[0260] Since the second electrode line formed in step S108 is continuously arranged, and the first electrode line formed in step S101 is continuously arranged, the test signal can be normally loaded, so that the TCS, TTS, TOP, TGS and other series of defects can be detected, and accurate positioning repair can be realized.

[0261] S110, forming a second passivation layer in the case that the detection state of the second electrode line is normal, so as to form the structure as shown in FIG. a of Figure 4 and FIG. a of Figure 5 or the structure as shown in FIG. a of Figure 7 and FIG. a of Figure 8 .

[0262] The second planar layer formed in step S110 covers the second electrode line and the first planar layer.

[0263] S111, forming a plurality of first vias, a plurality of second vias, a plurality of first insulating portions, a plurality of second insulating portions, a pixel electrode and an alignment layer.

[0264] A specific preparation method of step S111 is provided below. In the case that the first insulating portion and the second insulating portion each include only one layer structure, refer to Figure 4 andFigure 5 As shown, step S111 includes:

[0265] S121, Reference Figure 4 As shown in Figure b, an etching process is used to remove the second passivation layer 22, the first passivation layer 21, and the gate insulating layer 19 at the junction of two adjacent touch units arranged along the second direction, exposing the part of the first electrode line 4 that needs to be disconnected.

[0266] Specifically, either wet etching or dry etching can be used; no particular method is specified here.

[0267] S122, Reference Figure 5 As shown in Figure b, the second passivation layer 22 at the junction of two adjacent touch units arranged along the first direction is removed by an etching process, exposing the part of the second electrode line 8 that needs to be disconnected.

[0268] Specifically, either wet etching or dry etching can be used; no particular method is specified here.

[0269] S123, Reference Figure 4 Chinese C diagram and Figure 5 As shown in Figure c, wet etching is used to remove the parts of the first electrode line 4 and the second electrode line 8 that need to be disconnected, and to form the first via 5 and the second via 9.

[0270] It should be noted that after forming the first and second vias, other connecting vias can also be formed, such as: a first connecting via and a second connecting via, or... Figure 3 or Figure 6 The second electrode via 33 is shown.

[0271] S124, Reference Figure 5 As shown in Figure d, a second electrode 16 is formed; wherein the orthogonal projection of the second electrode on the substrate is within the orthogonal projection of the first electrode on the substrate, and its material can be ITO; the second electrode is electrically connected to the first electrode of the transistor through a second electrode via.

[0272] It should be noted that in step S124, a connecting electrode can also be formed simultaneously. The connecting electrode connects two adjacent rows of first electrodes through the first connecting via and the second connecting via, thereby realizing the electrical connection of the first electrodes of all sub-pixels in the touch unit.

[0273] S125, Reference Figure 4 The middle d diagram and Figure 5 As shown in Figure e, a first insulating portion 6, a second insulating portion 10, and an alignment layer 7 are formed using a single patterning process; wherein, the first insulating portion is disposed within a first via and fills the first via; the second insulating portion is disposed within a second via and fills the second via; and the alignment layer covers the second electrode and the second passivation layer.

[0274] The execution order of steps S121 and S122 is not limited. For example, step S121 can be executed first, followed by step S122; or step S122 can be executed first, followed by step S121; or step S121 may include etching the second passivation layer first, followed by etching the first passivation layer and the gate insulating layer. In step S121, the etching of the second passivation layer can be performed simultaneously with step S122. Of course, other execution orders are also possible, which will not be listed here.

[0275] The following provides another specific preparation method for step S111, in the case where the first insulating part includes a first insulator part and a second insulator part, and the second insulating part includes a third insulator part and a fourth insulator part, refer to... Figure 7 and Figure 8 As shown, step S111 includes:

[0276] S221, Reference Figure 7 As shown in Figure b, an etching process is used to remove the second passivation layer 22, the first passivation layer 21, and the gate insulating layer 19 at the junction of two adjacent touch units arranged along the second direction, exposing the part of the first electrode line 4 that needs to be disconnected.

[0277] Specifically, either wet etching or dry etching can be used; no particular method is specified here.

[0278] S222, Reference Figure 8 As shown in Figure b, the second passivation layer 22 at the junction of two adjacent touch units arranged along the first direction is removed by an etching process, exposing the part of the second electrode line 8 that needs to be disconnected.

[0279] Specifically, either wet etching or dry etching can be used; no particular method is specified here.

[0280] S223, Reference Figure 7 Chinese C diagram and Figure 8 As shown in Figure c, oxygen-containing gas etching is used to remove the parts of the first electrode line 4 and the second electrode line 8 that need to be disconnected, and to form the first via 5, the first insulator part 11, the second via 9 and the third insulator part 13.

[0281] Specifically, etching can be performed using an etching gas with a high oxygen content (e.g., SF6 / O2). The first and second electrode lines can be made of metals such as copper. The metal reacts with the etching gas to form a metal oxide chelate (e.g., copper oxide chelate). This metal chelate has high impedance and non-conductive properties. This metal chelate can then form the first and third insulator sections, respectively.

[0282] It should be noted that after forming the first and second vias, other connecting vias can also be formed, such as: a first connecting via and a second connecting via, or... Figure 3 or Figure 6 The second electrode via 33 is shown.

[0283] S224, Reference Figure 8 As shown in Figure d, a second electrode 16 is formed; wherein the orthogonal projection of the second electrode on the substrate is within the orthogonal projection of the first electrode on the substrate, and its material can be ITO; the second electrode is electrically connected to the first electrode of the transistor through a via.

[0284] It should be noted that in step S224, a connecting electrode can also be formed simultaneously. The connecting electrode connects two adjacent rows of first electrodes through the first connecting via and the second connecting via, thereby realizing the first electrode electrical connection of all sub-pixels in the touch unit.

[0285] S225, Reference Figure 7 The middle d diagram and Figure 8 As shown in Figure e, the second insulator portion 12, the fourth insulator portion 14, and the alignment layer 7 are formed using a single patterning process; wherein, the second insulator portion is disposed in the first via and fills the first via together with the first insulator portion; the fourth insulator portion is disposed in the second via and fills the second via together with the third insulator portion; the alignment layer covers the second electrode and the second passivation layer.

[0286] The execution order of steps S221 and S222 is not limited. For example, step S221 can be executed first, followed by step S222; or step S222 can be executed first, followed by step S221; or step S221 may include etching the second passivation layer first, followed by etching the first passivation layer and the gate insulating layer. In step S221, the etching of the second passivation layer can be performed simultaneously with step S222. Of course, other execution orders are also possible, which will not be listed here.

[0287] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0288] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0289] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the same; although the present application has been described in detail with reference to the foregoing examples, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, comprising: Substrate; Multiple touch units arranged in an array on the substrate, each touch unit comprising multiple sub-pixels arranged in an array; The sub-pixel includes a first electrode; the first electrodes of all the sub-pixels in each of the touch units are electrically connected; The first electrode is configured to function as a driving electrode during the display phase and as a touch sensing electrode during the touch phase; Multiple driving electrode lines, wherein at least a portion of the orthographic projection of the driving electrode lines on the substrate is disposed between the orthographic projections of two adjacent rows of the first electrodes on the substrate, and is electrically connected to at least one of the first electrodes; In the two adjacent rows of first electrodes, each row of first electrodes is arranged along the direction of the driving electrode line; the driving electrode line includes at least one break, and the break of the driving electrode line is located at the junction of two adjacent touch units arranged along the direction of the driving electrode line. The driving electrode lines are configured to transmit driving signals during the display phase and touch signals during the touch phase; At least one isolation via is disposed at the junction of two adjacent touch units arranged along the direction of the drive electrode line and exposes the break in the drive electrode line; At least one insulating portion is disposed within the insulating via and fills the insulating via.

2. The array substrate according to claim 1, wherein the driving electrode line includes a first electrode line; the isolation via includes a first via; and the isolation insulating portion includes a first insulating portion; Multiple first electrode lines are arranged along a first direction, and the first electrode lines are parallel to a row of first electrodes arranged along a second direction. At least a portion of the orthographic projection of the first electrode lines on the substrate is disposed between the orthographic projections of two adjacent rows of first electrodes arranged along the first direction on the substrate, and is electrically connected to the same row of first electrodes. The first electrode lines include multiple breaks, and the breaks of the first electrode lines are located at the junction of any two adjacent touch units arranged along the second direction. The second direction intersects the first direction. The first via is disposed at the junction of two adjacent touch units arranged along the second direction and exposes the break in the first electrode line; The first insulating part is disposed in the first through hole and fills the first through hole.

3. The array substrate according to claim 2, wherein the array substrate further comprises an alignment layer, the alignment layer covering the plurality of touch units; in, The alignment layer and the first insulating portion are an integral structure.

4. The array substrate according to claim 2, wherein the array substrate further comprises an alignment layer, the alignment layer being disposed on the side of the touch unit away from the substrate and covering the plurality of touch units; The first insulating portion includes a first insulator portion and a second insulator portion, the first insulator portion being located at the break of the first electrode wire, and the second insulator portion being disposed on the side of the first insulator portion away from the substrate; in, The alignment layer and the second insulator are an integral structure.

5. The array substrate according to any one of claims 1-4, wherein the driving electrode line includes a second electrode line; the isolation via includes a second via; and the isolation insulating portion includes a second insulating portion; Multiple second electrode lines are arranged along a second direction, and the orthographic projection of the second electrode lines on the substrate is disposed between the orthographic projections of two adjacent rows of first electrodes arranged along the second direction on the substrate, and is electrically connected to at least one first electrode belonging to the same touch unit. The second electrode line includes a break point located at the junction of two adjacent touch units arranged along the first direction; The second via is disposed at the junction of two adjacent touch units arranged along the first direction and exposes the break in the second electrode line; the second via and the first via do not overlap in the direction perpendicular to the plane of the substrate. The second insulating portion is disposed within the second via and fills the second via.

6. The array substrate according to claim 5, wherein the array substrate further comprises an alignment layer, the alignment layer covering the plurality of the touch units; in, The alignment layer and the second insulating portion are an integral structure.

7. The array substrate according to claim 5, wherein the array substrate further comprises a substrate and an alignment layer, the alignment layer being disposed on the side of the touch unit away from the substrate and covering the plurality of touch units; The second insulating portion includes a third insulator portion and a fourth insulator portion, the third insulator portion being located at the break in the second electrode wire, and the fourth insulator portion being disposed on the side of the third insulator portion away from the substrate; in, The alignment layer and the fourth insulator are an integral structure.

8. The array substrate according to claim 5, wherein the breaks of the plurality of second electrode lines are arranged along the second direction, and the plurality of second vias are arranged along the second direction.

9. The array substrate according to claim 5, wherein the sub-pixel further comprises a transistor and a second electrode; in, The transistor, along a direction perpendicular to the plane of the substrate, does not overlap with the first electrode line, the first electrode, or the second electrode line; the transistor includes a gate, a first electrode, and a second electrode. The orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the first electrode on the substrate; the second electrode is electrically connected to the first electrode and is configured to form an electric field with the first electrode during the display phase.

10. The array substrate according to claim 9, further comprising: Multiple gate lines are arranged along the first direction, and the orthogonal projection of the gate lines on the substrate is disposed between the orthogonal projections of two adjacent rows of the first electrodes arranged along the first direction on the substrate, and is electrically connected to the gate of the transistors in the same row; the gate lines and the first electrode lines do not overlap in a direction perpendicular to the plane of the substrate.

11. The array substrate according to claim 10, further comprising: Multiple data lines are arranged along the second direction, and the orthographic projection of the data lines on the substrate is positioned between the orthographic projections of two adjacent rows of the first electrodes arranged along the second direction on the substrate, and is electrically connected to the second electrode of the transistors in the same row; the data lines and the second electrode lines do not overlap in a direction perpendicular to the plane of the substrate.

12. The array substrate according to claim 11, wherein the gate line and the first electrode line are disposed on the same layer; the data line, the first electrode and the second electrode are disposed on the same layer.

13. The array substrate according to claim 12, wherein the transistor is a bottom-gate transistor; the first electrode line overlaps with one side of the first electrode in the same row; The array substrate further includes a gate insulating layer, a first passivation layer, and a second passivation layer; the gate insulating layer covers the gate line, the first electrode line, and the portion of the first electrode not covered by the first electrode line; the first passivation layer covers the data line and the gate insulating layer; The second passivation layer covers the second electrode line and the first passivation layer; The first via penetrates the first electrode line, the gate insulating layer, the first passivation layer, and the second passivation layer; the second via penetrates the second electrode line and the second passivation layer.

14. The array substrate according to claim 9, wherein the sub-pixel further comprises a plurality of connecting electrodes, the connecting electrodes being disposed on the same layer as the second electrode; The multiple first electrode lines are divided into a first group and a second group, and the first electrode lines of the first group and the first electrode lines of the second group are alternately arranged along the first direction; The connecting electrode is configured to electrically connect the first electrode, which is electrically connected to the first electrode line of the first group, and the first electrode line of the second group adjacent to the first group.

15. A display panel comprising an array substrate as described in any one of claims 1-14.

16. A method for fabricating an array substrate as described in any one of claims 11-13, comprising: Multiple first electrodes are arranged in an array; Multiple driving electrode lines are formed; Multiple lines to be tested are formed, including gate lines and / or data lines; The line to be tested is then tested; When the detection status of the line to be tested is normal, multiple isolation vias and multiple isolation insulation portions are formed; wherein, the isolation vias are disposed at the junction of two adjacent touch units arranged along the direction of the driving electrode line, and the driving electrode line is disconnected at the location of the isolation via; the isolation insulation portions are disposed in the isolation vias and fill the isolation vias.

17. The method according to claim 16, The formation of multiple driving electrode lines includes: Multiple first electrode lines are formed and arranged along a first direction; When the detection status of the line under test is normal, forming multiple isolation vias and multiple isolation insulation portions includes: An etching process is used to remove the film layer at the junction of two adjacent touch units arranged along the second direction, exposing the portion of the first electrode line that needs to be disconnected. The portion of the first electrode line that needs to be disconnected is removed by wet etching, and a first via is formed; The first insulating part and the alignment layer are formed using a single patterning process.

18. The method of claim 16, wherein forming the plurality of driving electrode lines comprises: Multiple first electrode lines are formed and arranged along a first direction; When the detection status of the line under test is normal, forming multiple isolation vias and multiple isolation insulation portions includes: An etching process is used to remove the film layer at the junction of two adjacent touch units arranged along the second direction, exposing the portion of the first electrode line that needs to be disconnected. Oxygen gas etching is used to remove the portion of the first electrode line that needs to be disconnected, and to form the first via and the first insulator portion; The second insulator part and the alignment layer are formed using a single patterning process.

19. The method according to claim 17 or 18, wherein forming the plurality of driving electrode lines further comprises: Multiple second electrode lines are formed along the second direction; The method further includes: With the first electrode lines continuously arranged, the second electrode lines are detected; When the detection state of the second electrode line is normal, a plurality of second vias and a plurality of second insulating portions are formed; wherein, the second vias are disposed at the junction of two adjacent touch units arranged along the first direction, and the second electrode line is disconnected at the location of the second via; the second vias and the first vias do not overlap in a direction perpendicular to the plane of the substrate; the second insulating portions are disposed in the second vias and fill the second vias.

20. The method according to claim 19, wherein forming a plurality of second vias and a plurality of second insulating portions when the detection state of the second electrode line is normal comprises: An etching process is used to remove the film layer at the junction of two adjacent touch units arranged along the first direction, exposing the portion of the second electrode line that needs to be disconnected. The portion of the second electrode line that needs to be disconnected is removed by wet etching, and a second via is formed; The second insulating layer and alignment layer are formed using a single patterning process. Alternatively, when the detection state of the second electrode line is normal, forming a plurality of second vias and a plurality of second insulating portions includes: An etching process is used to remove the film layer at the junction of two adjacent touch units arranged along the first direction, exposing the portion of the second electrode line that needs to be disconnected. Oxygen gas etching is used to remove the portion of the second electrode line that needs to be disconnected, and to form a second via and a third insulator portion; The fourth insulator part and the alignment layer are formed using a single patterning process.

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