Amorphous silicon thin film transistor and preparation method thereof, display panel

Abstract

The application discloses an amorphous silicon thin film transistor and a preparation method thereof and a display panel, and relates to the technical field of display. The amorphous silicon semiconductor layer of the amorphous silicon thin film transistor comprises ions doped by an ion implantation process in a region close to a source electrode and a drain electrode, and the concentration of the ions in a surface region close to the source electrode and the drain electrode in the amorphous silicon semiconductor layer is greater than or equal to 5*10 20 atoms / cc. Therefore, a better ohmic contact can be formed between the amorphous silicon semiconductor layer and the source electrode and the drain electrode, so that the on-state current of the amorphous silicon thin film transistor can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to an amorphous silicon thin-film transistor, a preparation method thereof and a display panel. BACKGROUND

[0002] Thin-film transistors (TFTs) as switching devices play an important application in display panels.

[0003] In the related art, a thin-film transistor generally includes a gate, a gate insulating layer, an active layer and a source-drain layer stacked in sequence in a direction away from a substrate, and the source-drain layer includes a source and a drain. The material of the active layer can be amorphous silicon (a-Si).

[0004] However, the ohmic contact performance between the active layer and the source-drain layer in the related art is poor. SUMMARY

[0005] The present application provides an amorphous silicon thin-film transistor, a preparation method thereof and a display panel, which can solve the problem of poor switching characteristics of the thin-film transistor in the related art. The technical solution is as follows:

[0006] In one aspect, an amorphous silicon thin-film transistor is provided, which includes:

[0007] an amorphous silicon semiconductor layer, a source and a drain which are sequentially arranged on a substrate;

[0008] The region of the amorphous silicon semiconductor layer close to the source and the drain contains ions doped by an ion implantation process, and the concentration of the ions in the surface region of the amorphous silicon semiconductor layer close to the source and the drain is greater than or equal to 5x10 20 ions per cubic centimeter.

[0009] Optionally, a certain depth of the surface region of the amorphous silicon semiconductor layer close to the source and the drain has the ions doped by the ion implantation process, and the concentration of the ions decreases as the distance from the surface region increases.

[0010] Optionally, a certain depth of the surface region of the amorphous silicon semiconductor layer close to the source and the drain has the ions doped by the ion implantation process, and the concentration of the ions increases first and then decreases as the distance from the surface region increases.

[0011] The thickness of the region where the concentration of the ions increases as the distance from the surface region increases is less than the thickness of the region where the concentration of the ions decreases as the distance from the surface region increases.

[0012] Optionally, the concentration of the ions in a first depth of a surface region of the amorphous silicon semiconductor layer near the source and the drain is greater than or equal to 3 x 1019 ions / cm3. 20 ions / cm3;

[0013] The first depth is between 0 and 50 Angstroms.

[0014] Optionally, the concentration of the ions in a second depth of a surface region of the amorphous silicon semiconductor layer near the source and the drain is greater than or equal to 5 x 1019 ions / cm3. 20 ions / cm3;

[0015] The second depth is between 0 and 20 Angstroms.

[0016] The concentration of the ions in a third depth of a surface region of the amorphous silicon semiconductor layer near the source and the drain is less than or equal to 5 x 1019 ions / cm3. 19 ions / cm3;

[0017] The third depth is between 600 and 1300 Angstroms.

[0018] The concentration of the ions in a fourth depth of a surface region of the amorphous silicon semiconductor layer near the source and the drain is less than or equal to 3 x 1019 ions / cm3. 19 ions / cm3;

[0019] The fourth depth is greater than or equal to 1300 Angstroms.

[0020] Optionally, the amorphous silicon semiconductor layer includes a source contact region, a drain contact region, and a channel region between the source contact region and the drain contact region.

[0021] The ions are distributed in the source contact region and the drain contact region.

[0022] Optionally, the concentration of the ions in a region of the source contact region and the drain contact region near the substrate is less than or equal to 3 x 1019 ions / cm3. 19 ions / cm3.

[0023] Optionally, the concentration of the ions in the channel region is less than or equal to 3 x 1019 ions / cm3. 19 ions / cm3;

[0024] The channel region and the regions of the source contact region and the drain contact region near the substrate have a thickness between 500 and 1000 Angstroms.

[0025] Optionally, the ions include phosphorus ions.

[0026] Optionally, the amorphous silicon semiconductor layer comprises a first amorphous silicon semiconductor layer and a second amorphous silicon semiconductor layer stacked along a side away from the substrate.

[0027] The thickness of the first amorphous silicon semiconductor layer is less than the thickness of the second amorphous silicon semiconductor layer, and the density of the first semiconductor layer is greater than the density of the second semiconductor layer.

[0028] Optionally, the ratio of the thickness of the first amorphous silicon semiconductor layer to the thickness of the second amorphous silicon semiconductor layer ranges from 0.1 to 0.5.

[0029] Optionally, the amorphous silicon semiconductor layer is obtained by ion implantation, wet etching and one-time patterning process on an amorphous silicon thin film.

[0030] In another aspect, a method for manufacturing an amorphous silicon thin film transistor is provided, the method comprising:

[0031] forming an amorphous silicon semiconductor layer, a source electrode and a drain electrode on a substrate in sequence;

[0032] Before forming the source electrode and the drain electrode, the forming of the amorphous silicon semiconductor layer comprises:

[0033] depositing an unpatterned amorphous silicon thin film and a buffer layer on the substrate in sequence, the material of the buffer layer being an oxide of silicon, a nitride of silicon or a silicon oxynitride;

[0034] using an ion implantation process to implant ions into the surface of the buffer layer away from the substrate, the ions diffusing from the buffer layer to the amorphous silicon thin film layer;

[0035] using a wet etching process to etch the buffer layer doped with the ions and the amorphous silicon thin film doped with the ions, to obtain an amorphous silicon semiconductor layer, the concentration of the ions in the surface region of the amorphous silicon semiconductor layer close to the source electrode and the drain electrode being greater than or equal to 5×10 20 ions / cubic centimeter.

[0036] Optionally, the using of the wet etching process to etch the buffer layer doped with the ions and the amorphous silicon thin film doped with the ions to obtain an amorphous silicon semiconductor layer comprises:

[0037] using the wet etching process to completely etch away the buffer layer and the amorphous silicon thin film outside the active layer region;

[0038] using the wet etching process to completely etch away the buffer layer of the active layer region and retain the amorphous silicon thin film implanted with the ions;

[0039] etching a channel region between the source contact region and the drain contact region of the remaining amorphous silicon thin film, and retaining an ion concentration of the channel region less than or equal to 3×1018 ions / cm3. 19 ions / cm3.

[0040] Optionally, the thickness of the buffer layer is less than the thickness of the amorphous silicon thin film.

[0041] Optionally, the thickness of the buffer layer is between 200-300 angstroms.

[0042] The thickness of the amorphous silicon thin film is between 1400-2000 angstroms.

[0043] The etching thickness of the wet etching process is between 20-30 angstroms.

[0044] Optionally, the etching solution used in the wet etching process is an acidic etching solution.

[0045] Optionally, the etching thickness of the etching of the channel region between the source contact region and the drain contact region of the remaining amorphous silicon thin film is greater than or equal to 500 angstroms.

[0046] Optionally, the atmosphere used in the ion implantation process includes phosphine, an ion dosage greater than or equal to 1×1016 ions / cm2, and an acceleration voltage greater than or equal to 20 kilovolts and less than or equal to 30 kilovolts. 15

[0047] Optionally, the forming of the amorphous silicon thin film on the substrate includes:

[0048] depositing a first amorphous silicon thin film on the substrate according to a first film deposition rate;

[0049] depositing a second amorphous silicon thin film on a side of the first amorphous silicon thin film away from the substrate according to a second film deposition rate;

[0050] Optionally, the first film deposition rate is between 4-8 angstroms per second.

[0051] Optionally, the second film deposition rate is between 30-50 angstroms per second.

[0052] In another aspect, a display panel is provided, including a substrate and a plurality of amorphous silicon thin film transistors as described above on the substrate.

[0053] The technical solutions provided by the present application have at least the following beneficial effects:

[0054] ​The application provides an amorphous silicon thin film transistor, wherein the amorphous silicon semiconductor layer of the amorphous silicon thin film transistor contains ions doped by an ion implantation process in the region close to the source and the drain, and the concentration of the ions in the surface region of the amorphous silicon semiconductor layer close to the source and the drain is greater than or equal to 5*10 20 atoms / cc. Thus, the amorphous silicon semiconductor layer and the source and the drain can form a better ohmic contact, so that the on-state current of the amorphous silicon thin film transistor can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0056] Figure 1 is a structural schematic diagram of a display panel using an amorphous silicon thin film transistor;

[0057] Figure 2 is a diagram showing the distribution of the concentration of doped ions in an amorphous silicon semiconductor layer with the implantation depth;

[0058] Figure 3 is a structural schematic diagram of a display panel using an amorphous silicon thin film transistor provided by the embodiments of the present application;

[0059] Figure 4 is a structural schematic diagram of another display panel using an amorphous silicon thin film transistor provided by the embodiments of the present application;

[0060] Figure 5 is a structural schematic diagram of another display panel using an amorphous silicon thin film transistor provided by the embodiments of the present application;

[0061] Figure 6 is a flowchart of another preparation method of an amorphous silicon thin film transistor provided by the embodiments of the present application;

[0062] Figure 7 is a structural schematic diagram of a substrate provided by the embodiments of the present application;

[0063] Figure 8 is a diagram showing the change relationship between the ion concentration and the depth in the buffer layer and the amorphous silicon thin film provided by the embodiments of the present application;

[0064] Figure 9 is a diagram showing the change relationship between the ion concentration and the depth in the amorphous silicon semiconductor layer provided by the embodiments of the present application;

[0065] Figure 10FIG. 1 is a switching characteristic comparison diagram of an amorphous silicon thin film transistor prepared by an embodiment of the present application and an amorphous silicon thin film transistor prepared by a related art technology;

[0066] Figure 11 FIG. 2 is a flowchart of a method for preparing an amorphous silicon thin film transistor according to an embodiment of the present application;

[0067] Figure 12 FIG. 3 is a structural diagram of a substrate according to an embodiment of the present application;

[0068] Figure 13 FIG. 4 is a structural diagram of another substrate according to an embodiment of the present application. DETAILED DESCRIPTION

[0069] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0070] As shown in FIG. 1, Figure 1 Figure 1 is a structural diagram of a display panel using an amorphous silicon thin film transistor. Referring to FIG. 1, Figure 1 It can be seen that the amorphous silicon thin film transistor 10 in the display panel 01 can include a gate 101, a gate insulator (GI) 102, an amorphous silicon semiconductor layer 103, a source 104 and a drain 105 which are sequentially arranged on a substrate 11. The amorphous silicon semiconductor layer 103 is doped with ions. The N-type doped amorphous silicon semiconductor layer 103 can be generally formed by uniformly doping phosphine (PH3) gas in the process of chemical vapor deposition (CVD) of amorphous silicon semiconductor material. By doping ions in the amorphous silicon semiconductor layer 103, good ohmic contact between the amorphous silicon semiconductor layer 103 and the source 104 and the drain 105 can be achieved. Thus, the amorphous silicon thin film transistor can have a high on-current and a small off-current, i.e., the switching characteristic of the amorphous silicon thin film transistor is good.

[0071] ​A production line of low temperature poly-silicon (LTPS) thin film transistor (TFT) usually uses ion implantation process to dope ions in a semiconductor. The ion implantation process is a process of injecting an ion beam accelerated to a certain high energy into a surface layer of a semiconductor material to change the physical and chemical properties of the surface layer, for example, injecting boron, phosphorus or arsenic into silicon can change the conductivity of the silicon surface. The depth and concentration of ion implantation can be accurately controlled by the ion implantation process. Based on this, a new amorphous silicon TFT preparation process can be developed using the production line equipment of the low temperature poly-silicon TFT, and an amorphous silicon TFT device doped by the ion implantation process can be produced, which is beneficial to product diversification and process integration of the production line.

[0072] Generally, the deposition equipment on the production line of the low temperature poly-silicon TFT is not provided with a doping gas pipeline. Figure 2 FIG. 1 is a schematic diagram of the distribution of the concentration of doped ions in an amorphous silicon semiconductor layer with the depth of the amorphous silicon semiconductor layer. The horizontal axis represents the concentration of the doped ions in the amorphous silicon semiconductor layer, and the unit is atoms per cubic centimeter (atoms / cc). The vertical axis represents the depth of the amorphous silicon semiconductor layer, and the unit is angstrom. The concentration of the doped ions in the amorphous silicon semiconductor layer can be detected by a detection device. The detection device can be a transmission electron microscope or a secondary ion mass spectroscopy (SIMS) analyzer.

[0073] Please refer to Figure 2 By the ion implantation process, the distribution of the doped ions in the thickness direction of the amorphous silicon semiconductor layer is approximately normal distribution. The concentration of the doped ions in the surface layer of the amorphous silicon semiconductor layer close to the source and drain is low, and the ohmic contact performance between the amorphous silicon semiconductor layer and the source and drain layer is poor, thereby causing poor switching characteristics of the thin film transistor. For example, the switching current of the amorphous silicon thin film transistor prepared by the above ion implantation process is small (for example, the switching current ratio is less than 10 5 ). Further, the preparation processes of the low temperature poly-silicon thin film transistor and the amorphous silicon thin film transistor cannot be integrated into the same production line.

[0074] The above technical problems can be optimized by the limited embodiments described below.

[0075] The amorphous silicon thin film transistor provided by the embodiments of the present application can be used in the display area of a display panel.

[0076] The amorphous silicon thin film transistor provided by the embodiments of the present application can be applied to small-size mobile devices (Mobile), notebook computers (NB), tablet computers (iPAD), small-to-medium-size monitors (MNT), medium-to-large-size televisions (TV) and medium-to-large-size MNT, etc.

[0077] The amorphous silicon thin film transistor provided by the embodiments of the present application can be used in the display field or the chip field, and the display field can be the technical field of liquid crystal display (LCD) display panels, organic light-emitting diode (OLED) display panels, quantum dot light emitting diode (QLED) display panels, micro light emitting diode (Micro LED) display panels and sensors, etc. The amorphous silicon thin film transistor provided by the embodiments of the present application can be used as a switching thin film transistor in a pixel.

[0078] Figure 3 is a structural schematic diagram of a display panel using the amorphous silicon thin film transistor provided by the embodiments of the present application. Referring to Figure 3 It can be seen that the amorphous silicon thin film transistor 20 in the display panel 02 can include an amorphous silicon semiconductor layer 201, a source electrode 202 and a drain electrode 203 which are sequentially arranged on a substrate 21.

[0079] Referring to Figure 3 The source electrode 202 and the drain electrode 203 are located in the same layer and can be prepared by using the same one-time patterning process. The source electrode 202 and the drain electrode 203 are both electrically connected to the amorphous silicon semiconductor layer 201.

[0080] The region of the amorphous silicon semiconductor layer 201 close to the source electrode 202 and the drain electrode 203 contains ions 201X doped by an ion implantation process, and the concentration of the ions in the surface region of the amorphous silicon semiconductor layer 201 close to the source electrode 202 and the drain electrode 203 is greater than or equal to 5x10 20 atoms per cubic centimeter (atoms / cc).

[0081] Since the concentration of the doped ions 201X in the unit volume in the surface region of the amorphous silicon semiconductor layer 201 is high (i.e., the number of ions in the unit volume is high), the amorphous silicon semiconductor layer 201 can achieve good ohmic contact with the source electrode 202 and the drain electrode 203, and thus the amorphous silicon thin film transistor 20 can have a large on-state current.

[0082] In summary, the embodiment of the present application provides an amorphous silicon thin film transistor. The region close to the source and the drain in the amorphous silicon semiconductor layer contains ions doped by ion implantation process. The concentration of the ions in the surface region close to the source and the drain in the amorphous silicon semiconductor layer is greater than or equal to 5x1019 atoms / cc. In this way, a better ohmic contact can be formed between the amorphous silicon semiconductor layer and the source and the drain, so as to improve the on-state current of the amorphous silicon thin film transistor. 20 atoms / cc. In this way, a better ohmic contact can be formed between the amorphous silicon semiconductor layer and the source and the drain, so as to improve the on-state current of the amorphous silicon thin film transistor.

[0083] Optionally, please refer to Figure 3 The certain depth of the surface region close to the source 202 and the drain 203 in the amorphous silicon semiconductor 201 has ions 201X doped by ion implantation process. The concentration of the ions 201X decreases with the distance from the surface region. In the embodiment of the present application, the number of the doped ions 201X in the unit volume in the region of the amorphous silicon semiconductor layer 201 far from the source 202 and the drain 203 is small or even zero. In this way, the leakage current of the part of the amorphous silicon semiconductor layer 201 far from the source 202 and the drain 203 is small, and the off-state current of the amorphous silicon thin film transistor 20 can be reduced. Based on the above analysis, the amorphous silicon thin film transistor provided by the embodiment of the present application has a higher on-off current ratio, and has a better switching characteristic.

[0084] In an optional embodiment, the certain depth of the surface region close to the source 202 and the drain 203 in the amorphous silicon semiconductor 201 has ions 201X doped by ion implantation process. The concentration of the ions 201X increases first and then decreases with the distance from the surface region. The thickness of the region where the concentration of the ions 201X increases with the distance from the surface region is less than the thickness of the region where the concentration of the ions 201X decreases with the distance from the surface region. In this way, the number of the doped ions 201X in the unit volume in the region of the amorphous silicon semiconductor layer 201 far from the source 202 and the drain 203 is small or even zero. In this way, the leakage current of the part of the amorphous silicon semiconductor layer 201 far from the source 202 and the drain 203 is small, and the off-state current of the amorphous silicon thin film transistor 20 can be reduced. Based on the above analysis, the amorphous silicon thin film transistor provided by the embodiment of the present application has a higher on-off current ratio, and has a better switching characteristic.

[0085] Optionally, the concentration of the ions 201X at the first depth of the surface region close to the source 202 and the drain 203 in the amorphous silicon semiconductor layer 201 is greater than or equal to 3x1019 atoms / cc. 20atoms / cc. The initial depth is between 0 and 50 angstroms. This allows for better ohmic contacts between the amorphous silicon semiconductor layer and both the source and drain electrodes, thereby improving the on-state current of the amorphous silicon thin-film transistor.

[0086] Optionally, in this embodiment, the concentration of ions 201X at a second depth in the amorphous silicon semiconductor layer 201, near the surface region of the source electrode 201 and drain electrode 203, is greater than or equal to 5 × 10⁻⁶. 20 atoms / cc. The second depth is between 0 and 20 angstroms.

[0087] At a third depth in the surface region near the source 202 and drain 203 of the amorphous silicon semiconductor layer 201, the concentration of ions 201X is less than or equal to 5 × 10⁻⁶. 19 atoms / cc; the third depth is between 600 and 1300 angstroms.

[0088] At a fourth depth in the surface region near the source 202 and drain 203 of the amorphous silicon semiconductor layer 201, the concentration of ions 201X is less than or equal to 3 × 10⁻⁶. 19 atoms / cc; fourth depth greater than or equal to 1300 angstroms.

[0089] Optional, such as Figure 4 As shown, Figure 4 This is a schematic diagram of another display panel using amorphous silicon thin-film transistors provided in an embodiment of this application. The amorphous silicon semiconductor layer 201 includes a source contact region 2011, a drain contact region 2012, and a channel region 2013 located between the source contact region 2011 and the drain contact region 2012. The source contact region 2011 is electrically connected to the source 202, the drain contact region 2012 is electrically connected to the drain 203, and the channel region 2013 has no direct contact with either the source 202 or the drain 203.

[0090] Both the source contact region 2011 and the drain contact region 2012 are doped with ions 201X, while the channel region 2013 can be doped with very few ions 201X. This results in a smaller leakage current in the channel region 2013, and consequently, a smaller leakage current in the amorphous silicon thin-film transistor.

[0091] Optionally, the concentration of doped ions 201X in the source contact region 2011 and the drain contact region 2012 near the substrate 21 is less than or equal to 3 × 10⁻⁶. 19 atoms / cc. In this way, the leakage current in the source contact region 2011 and the drain contact region 2012 near the substrate 21 can be reduced, thereby reducing the leakage current in the amorphous silicon thin film transistor.

[0092] Optionally, the concentration of the doping ions 201X in the channel region 2013 is less than or equal to 3x1018atoms / cc. 19 The thickness D1 of the channel region 2013 and the source contact region 2011 and the drain contact region 2012 near the substrate 21 is between 500-1000 angstroms. On one hand, the small thickness of the channel region 2013 can ensure that the number of the doping ions 201X in the channel region 2013 is small, so that the leakage current in the channel region 2013 is small. On the other hand, the small thickness of the channel region 2013 can avoid over-etching when the patterning process is performed on the side of the channel region 2013 far from the substrate 21, which can affect the performance of the amorphous silicon thin film transistor.

[0093] Please refer to Figure 4 , the thickness D2 of the source contact region 2011 and the drain contact region 2012 is equal, which can make the conductive properties of the source contact region 2011 and the drain contact region 2012 substantially the same, and thus can make the performance of the amorphous silicon thin film transistor more stable.

[0094] In addition, the difference between the thickness of the source contact region 2011 and the drain contact region 2012 and the thickness of the channel region 2013 can be greater than or equal to 500 angstroms. Since the depth of the part with a large ion 201X doping concentration in the source contact region 2011 and the drain contact region 2012 in the thickness direction perpendicular to the substrate 21 is usually less than or equal to 500 angstroms. Therefore, the difference between the thickness of the source contact region 2011 and the drain contact region 2012 and the thickness of the channel region 2013 being greater than or equal to 500 angstroms can make the source contact region 2011 and the drain contact region 2012 have ions 201X, and at the same time, avoid the channel region 2013 having ions 201X. Thus, a better ohmic contact between the source contact region 2011 and the source 202, and the drain contact region 2012 and the drain 203 can be achieved while reducing the leakage current in the channel 2013. In this way, the switching characteristics of the amorphous silicon thin film transistor can be improved.

[0095] Optionally, the ions 201X include phosphorus ions. By doping the source contact region 2011 and the drain contact region 2012 in the amorphous silicon semiconductor layer 201 with phosphorus ions (P + ), a better ohmic contact between the source 202 and the drain 203 and the amorphous silicon semiconductor layer 201 can be formed, which is beneficial to improve the on-state current and improve the conductive capacity of the amorphous silicon thin film transistor in the on-state.

[0096] Optionally, as shown in Figure 5 , the thickness of the source contact region 2011 and the drain contact region 2012 is greater than the thickness of the channel region 2013. Figure 5is another structure diagram of a display panel using amorphous silicon thin film transistor shown in the embodiments of the present application. The amorphous silicon semiconductor layer includes a first amorphous silicon semiconductor layer 201a and a second amorphous silicon semiconductor layer 201b which are arranged in a stack along the side away from the substrate 21. The thickness of the first amorphous silicon semiconductor layer 201a is less than the thickness of the second amorphous silicon semiconductor layer 201b, and the deposition rate of the film layer when forming the first amorphous silicon semiconductor layer 201a is less than the deposition rate of the film layer when forming the second amorphous silicon semiconductor layer 201b. The density of the film layer can be negatively correlated with the deposition rate of the film layer. That is, the greater the deposition rate of the film layer, the smaller the density of the film layer; the smaller the deposition rate of the film layer, the greater the density of the film layer. Therefore, the deposition rate of the film layer of the second amorphous silicon semiconductor layer 201b can be greater than the deposition rate of the film layer of the first amorphous silicon semiconductor layer 201a, so that the density of the first amorphous silicon semiconductor layer 201a is greater than the density of the second amorphous silicon semiconductor layer 201b.

[0097] When forming the first amorphous silicon semiconductor layer 201a with a relatively thin thickness, a smaller deposition rate of the film layer is used, so that the density of the first amorphous silicon semiconductor layer 201a is greater, the defects are fewer, and the first amorphous silicon semiconductor layer 201a is more closely attached to the gate insulating layer 205, thereby ensuring the performance of the amorphous silicon thin film transistor. When forming the second amorphous silicon semiconductor layer 201b with a relatively thick thickness, the deposition rate of the film layer can be appropriately increased to improve the preparation efficiency of the amorphous silicon semiconductor layer 201.

[0098] Optionally, the ratio of the thickness of the first amorphous silicon semiconductor layer 201a to the thickness of the second amorphous silicon semiconductor layer 201b is in the range of 0.1 to 0.5. Within this range, the preparation efficiency of the amorphous silicon semiconductor layer 201 can be effectively improved while ensuring the performance of the amorphous silicon semiconductor layer 201.

[0099] Optionally, the amorphous silicon semiconductor layer is obtained by ion implantation, wet etching and one-time patterning process on the amorphous silicon film in sequence. When ion implantation is performed, the depth and quantity of the implanted ions in the amorphous silicon semiconductor layer can be accurately controlled by controlling the energy and dose of ion implantation. The energy of ion implantation can determine the implantation depth of the ions in the amorphous silicon semiconductor layer, and the ion dose can determine the quantity of the implanted ions in the amorphous silicon semiconductor layer. It should be noted that the energy and dose of ion implantation can be set according to the actual production needs, and the embodiments of the present application do not limit this.

[0100] The wet etching process can accurately control the etching thickness of the amorphous silicon film, and thus the etching degree of the amorphous silicon film can be uniform to ensure the stability of the prepared amorphous silicon thin film transistor.

[0101] The one-time patterning process can realize the patterning of the amorphous silicon thin film to form an amorphous silicon semiconductor layer with a source contact region, a drain contact region and a channel region.

[0102] As shown in Figure 5 The amorphous silicon thin film transistor 20 also includes a gate 204 and a gate insulating layer 205 which are sequentially stacked on the side of the amorphous silicon semiconductor layer 201 close to the substrate 21. The material of the gate insulating layer 205 can include silicon dioxide (SiO2), silicon nitride (Si3N4) or a mixture of silicon dioxide and silicon nitride. It should be noted that Figure 5 The amorphous silicon thin film transistor is shown in a bottom gate structure. The amorphous silicon thin film transistor in the embodiments of the present application can also be in a top gate structure, which is not limited in the embodiments of the present application.

[0103] In summary, the amorphous silicon thin film transistor provided in the embodiments of the present application includes ions doped by an ion implantation process in the region close to the source and the drain in the amorphous silicon semiconductor layer, and the concentration of the ions in the surface region close to the source and the drain in the amorphous silicon semiconductor layer is greater than or equal to 5×10 20 atoms / cc. Thus, a better ohmic contact can be formed between the amorphous silicon semiconductor layer and the source and the drain, thereby improving the on-state current of the amorphous silicon thin film transistor.

[0104] The embodiments of the present application provide a preparation method of an amorphous silicon thin film transistor. The method can be used to prepare the amorphous silicon thin film transistor 20 shown in Figure 3 The method can include sequentially forming an amorphous silicon semiconductor layer 201, a source 202 and a drain 203 on a substrate 21.

[0105] Before the source 202 and the drain 203 are formed, the amorphous silicon semiconductor layer 201 is formed, which includes:

[0106] The unpatterned amorphous silicon thin film and the buffer layer are sequentially deposited on the substrate 21. The material of the buffer layer is an oxide of silicon, a nitride of silicon or an oxynitride of silicon.

[0107] The ion implantation process is used to implant ions on the surface of the buffer layer away from the substrate. The ions diffuse from the buffer layer to the amorphous silicon thin film layer.

[0108] The wet etching process is used to etch the buffer layer doped with ions and the amorphous silicon thin film doped with ions to obtain an amorphous silicon semiconductor layer 201. The concentration of the ions 201X in the surface region close to the source 202 and the drain 203 in the amorphous silicon semiconductor layer 201 is greater than or equal to 5×10 20 atoms / cc.

[0109] Thus, the contact resistance between the source 202 and the drain 203 and the amorphous silicon semiconductor layer 201 can be reduced. The amorphous silicon semiconductor layer 201 can achieve good ohmic contact with the source 202 and the drain 203, and thus the amorphous silicon thin film transistor 20 can have a large on-state current. Thus, the amorphous silicon thin film transistor 20 can have a high on-off current ratio.

[0110] In summary, the embodiment of the present application provides a preparation method of an amorphous silicon thin film transistor. The amorphous silicon semiconductor layer of the amorphous silicon thin film transistor prepared by the method contains ions doped by an ion implantation process near the source and the drain, and the concentration of the ions in the surface region of the amorphous silicon semiconductor layer near the source and the drain is greater than or equal to 5x1019 atoms / cc. Thus, the amorphous silicon semiconductor layer can form good ohmic contact with the source and the drain, and thus the on-state current of the amorphous silicon thin film transistor can be improved. 20 atoms / cc. Thus, the amorphous silicon semiconductor layer can form good ohmic contact with the source and the drain, and thus the on-state current of the amorphous silicon thin film transistor can be improved.

[0111] Figure 6 is a flowchart of another preparation method of an amorphous silicon thin film transistor provided by the embodiment of the present application. The method can be used to prepare the amorphous silicon thin film transistor shown in Figure 3 , for example. Referring to Figure 6 , the method can include the following steps.

[0112] Step 501: sequentially depositing an unpatterned amorphous silicon thin film and a buffer layer on a substrate.

[0113] The material of the buffer layer can be an oxide of silicon, a nitride of silicon, or a silicon oxynitride.

[0114] In the embodiment of the present application, a substrate 21 can be obtained first, and then a first amorphous silicon sub-film can be deposited on the substrate 21 on one side of the substrate 21 according to a first film deposition rate, and a second amorphous silicon semiconductor sub-film can be deposited on the side of the first amorphous silicon sub-film away from the substrate 21 according to a second film deposition rate. Thus, an amorphous silicon thin film can be formed on the substrate 21, and the amorphous silicon thin film can cover the substrate 21 as a whole.

[0115] The second film deposition rate can be greater than the first film deposition rate, for example, the first film deposition rate can be between 4 and 8 angstroms per second, and the second film deposition rate can be between 30 and 50 angstroms per second.

[0116] Optionally, the thickness of the amorphous silicon thin film can be greater than or equal to 1600 angstroms and less than or equal to 2300 angstroms. Specifically, the thickness of the first amorphous silicon sub-film can be greater than or equal to 300 angstroms and less than or equal to 600 angstroms, and the thickness of the second amorphous silicon sub-film can be greater than or equal to 1300 angstroms and less than or equal to 1700 angstroms.

[0117] The substrate 21 may be made of materials such as glass or polyimide.

[0118] The thickness of the buffer layer can be less than the thickness of the amorphous silicon film. For example, the thickness of the amorphous silicon film can be between 1400 and 2000 angstroms; the thickness of the buffer layer can be between 200 and 300 angstroms.

[0119] Step 502: Ions are implanted on the surface of the buffer layer away from the substrate using an ion implantation process. The ions diffuse from the buffer layer to the amorphous silicon thin film layer.

[0120] In this embodiment, the atmosphere used in the ion implantation process may include phosphine, and the phosphorus ions in the phosphine can be implanted into the buffer layer and the amorphous silicon thin film. In the ion implantation process, the ion dose can be greater than or equal to e. 15 The acceleration voltage can be greater than or equal to 20 kV and less than or equal to 30 kV per square centimeter.

[0121] Please refer to Figure 7 , Figure 7 This is a schematic diagram of a substrate structure at the end of step 502, in which a buffer layer 601 and an amorphous silicon thin film 602, doped with ions 201X by ion implantation, are formed on the substrate 21.

[0122] It should be understood that, in the embodiments of this application, the material used for the buffer layer is a material with similar ion permeability to amorphous silicon. For example, the material of the buffer layer may include at least silicon oxide. Alternatively, the material of the buffer layer may also include silicon nitride.

[0123] Based on this, after doping ions into the buffer layer and amorphous silicon thin film through ion implantation, such as Figure 8 As shown, Figure 8 This describes the relationship between ion concentration and depth in the buffer layer and amorphous silicon thin film after step 502. The horizontal axis represents depth, and the unit is angstroms. The vertical axis represents ion concentration, with units of atoms per cubic centimeter (atoms / cc). The distribution of ions in the buffer layer and the amorphous silicon film along the thickness direction approximates a normal distribution. Furthermore, due to the relatively small thickness of the buffer layer, the concentration of ions implanted into the buffer layer gradually increases along its thickness direction, while the concentration of ions implanted into the amorphous silicon film initially increases gradually and then gradually decreases along its thickness direction.

[0124] It should also be understood that since the depth of ion implantation is related to the energy of ion implantation, the thickness of the buffer layer formed in step 501 can be determined based on the energy of ion implantation to ensure that after ion implantation of the buffer layer and the amorphous silicon film, the ion concentration in the buffer layer gradually increases in the thickness direction of the buffer layer, and the ion concentration in the amorphous silicon film first gradually increases and then gradually decreases in the thickness direction of the amorphous silicon film, that is, the part with the highest ion concentration is located in the amorphous silicon film.

[0125] Step 503, using a wet etching process, etching the buffer layer doped with ions and the amorphous silicon film doped with ions to obtain an amorphous silicon semiconductor layer.

[0126] Among them, the concentration of ions in the surface region of the amorphous silicon semiconductor layer close to the source and the drain is greater than or equal to 5x10 20 atoms / cc.

[0127] Step 503 can include the following three steps 5031, 5032 and 5033:

[0128] 5031, using a wet etching process, completely etching away the buffer layer and the amorphous silicon film outside the active layer region.

[0129] The active layer region can refer to the region of the amorphous silicon film to be formed into an amorphous silicon semiconductor layer.

[0130] 5032, using a wet etching process, completely etching away the buffer layer of the active layer region and retaining the amorphous silicon film doped with ions.

[0131] That is, the buffer layer on the active layer region is completely etched away. Retaining the amorphous silicon film doped with ions can be understood as not etching or only etching part of the amorphous silicon film doped with ions. When only etching part of the amorphous silicon film doped with ions, the etching thickness of the wet etching process is between 20-30 angstroms.

[0132] Please refer to Figure 7 and Figure 8 It can be understood that: the buffer layer 601 has a fifth surface away from the substrate 21, and the amorphous silicon film 602 has a sixth surface close to the substrate 21. In the direction from the fifth surface to the sixth surface, the number of ions doped in a unit volume of the buffer layer 601 and the amorphous silicon film 602 first gradually increases and then gradually decreases.

[0133] In this embodiment, to ensure a good ohmic contact between the final amorphous silicon semiconductor layer and the source and drain electrodes, a wet etching process can be used to etch away the portion of the surface layer with smaller ion counts (201X) per unit volume in the buffer layer 601 and the amorphous silicon thin film 602. This maximizes the number of ions (201X) per unit volume on the side of the etched amorphous silicon thin film furthest from the substrate 21. The etching solution used in the wet etching process can be an acidic etching solution, or more specifically, a hydrogen fluoride solution.

[0134] The portion of the buffer layer 601 and the amorphous silicon thin film 602 with smaller ions per unit volume can refer to the film layer in which the number of doped ions per unit volume gradually increases in the direction from the fifth surface to the sixth surface.

[0135] It should be noted that the etching thickness of this wet etching process is related to the implantation energy of the ion implantation process. Generally, the higher the ion implantation energy, the greater the ion implantation depth, and correspondingly, the greater the etching thickness of the wet etching process, to ensure that the entire buffer layer 601 and the portion of the amorphous silicon thin film 602 with smaller ion density per unit volume are etched away. For example, the etching solution used in the wet etching process is a hydrogen fluoride solution. The etching thickness of the wet etching process is greater than or equal to 220 angstroms and less than or equal to 330 angstroms. Specifically, the etching thickness of the wet etching process on the side of the ion-doped amorphous silicon thin film 602 away from the substrate is greater than or equal to 20 angstroms and less than or equal to 30 angstroms.

[0136] If the etching solution used in the wet etching process is a hydrogen fluoride solution, then the ratio of the etching rate of the hydrogen fluoride solution on the buffer layer 601 to the etching rate on the amorphous silicon thin film 602 is greater than or equal to 10. For example, the etching rate of hydrogen fluoride on the buffer layer 601 ranges from 5 Å / s to 20 Å / s. The etching rate of hydrogen fluoride on the amorphous silicon thin film 602 ranges from 0.5 Å / s to 2 Å / s.

[0137] Since the etching rate of the hydrogen fluoride solution on the buffer layer 601 is much greater than that on the amorphous silicon thin film 602, the fabrication efficiency of the amorphous silicon thin film transistor can be improved on the one hand, and the etching thickness of the buffer layer 601 and the amorphous silicon thin film 602 can be controlled more precisely according to the ratio of the etching rates of the buffer layer 601 and the amorphous silicon thin film 602.

[0138] 5033. Etch the channel region located between the source contact region and the drain contact region in the retained amorphous silicon thin film, while maintaining an ion concentration in the channel region of less than or equal to 3 × 10⁻⁶. 19 The atoms / cc part.

[0139] The etching thickness of etching the channel region between the source contact region and the drain contact region in the reserved amorphous silicon thin film is greater than or equal to 500 angstroms.

[0140] The amorphous silicon semiconductor layer can be obtained by etching the part with a higher ion concentration in the channel region. Referring to Figure 4 The final amorphous silicon semiconductor layer 201 includes a source contact region 2011, a drain contact region 2012, and a channel region 2013 between the source contact region 2011 and the drain contact region 2012, the source contact region 2011 and the drain contact region 2012 are doped with ions 201X, and the channel region 2013 has a lower concentration of the ions 201X.

[0141] Step 504: Forming the source and the drain on the side of the etched amorphous silicon thin film away from the substrate.

[0142] A metal thin film can be formed on the side of the etched amorphous silicon thin film away from the substrate 21. The metal thin film can cover the substrate 21 entirely. Then, a patterning process is performed on the metal thin film to obtain the source 202 and the drain 203. The source contact region 2011 is in contact with the source 202, and the drain contact region 2012 is in contact with the drain 203. The structure of the substrate at the end of step 504 can also be referred to Figure 9 .

[0143] Figure 9 is the relationship between the ion concentration and the depth in the amorphous silicon semiconductor layer provided by the embodiments of the present application. Please refer to Figure 9 , wherein the abscissa is the depth, and the unit is angstrom The ordinate is the ion concentration, and the unit is atoms / cc. The amorphous silicon semiconductor layer 201 obtained in the embodiments of the present application has a concentration of the ions 201X greater than or equal to 5x10 20 atoms / cc in the surface region close to the source 202 and the drain 203.

[0144] In this way, the contact resistance between the source 202 and the drain 203 and the amorphous silicon semiconductor layer 201 can be reduced. The amorphous silicon semiconductor layer 201 can achieve good ohmic contact with the source 202 and the drain 203, so that the amorphous silicon thin film transistor 20 has a larger on-state current. In addition, the leakage current in the region close to the substrate 21 in the source contact region 2011 and the drain contact region 2012 can be small, so that the leakage current in the amorphous silicon thin film transistor is small. Thus, the amorphous silicon thin film transistor 20 has a higher on-off current ratio.

[0145] As Figure 10 shown, Figure 10 is a comparison chart of switching characteristics of the amorphous silicon thin film transistor prepared in the embodiment of the present application and the amorphous silicon thin film transistor prepared by the related art. The horizontal axis is voltage, and the unit is volt (V). The vertical axis is current, and the unit is ampere (A). Figure 13 The curve C1 in the figure is a curve of drain current of the amorphous silicon thin film transistor in the embodiment of the present application varying with gate voltage. The curve C2 is a curve of drain current of the amorphous silicon thin film transistor prepared by using deposition doping in the related art varying with gate voltage. The curve C3 is a curve of drain current of the amorphous silicon thin film transistor prepared by using ion implantation process and without etching the amorphous silicon semiconductor layer varying with gate voltage.

[0146] From Figure 10 it can be seen that when the gate voltage of the amorphous silicon thin film transistor is positive and the amorphous silicon thin film transistor is in the open state, the amorphous silicon thin film transistor prepared in the embodiment of the present application has a larger on-state current compared with the amorphous silicon thin film transistor prepared by the related art. When the gate voltage of the amorphous silicon thin film transistor is negative and the amorphous silicon thin film transistor is in the closed state, the amorphous silicon thin film transistor prepared in the embodiment of the present application has a smaller off-state current compared with the amorphous silicon thin film transistor prepared by the related art, that is, the switching current of the amorphous silicon thin film transistor prepared in the embodiment of the present application is larger. It is tested that the switching current ratio of the amorphous silicon thin film transistor in the embodiment of the present application can be greater than or equal to 10 6 .

[0147] In summary, the embodiment of the present application provides a preparation method of an amorphous silicon thin film transistor. The amorphous silicon semiconductor layer of the amorphous silicon thin film transistor prepared by the method contains ions doped by ion implantation process near the source and the drain, and the concentration of the ions in the surface region of the amorphous silicon semiconductor layer near the source and the drain is greater than or equal to 5×10 20 atoms / cc. Thus, a better ohmic contact can be formed between the amorphous silicon semiconductor layer and the source and the drain, so as to improve the on-state current of the amorphous silicon thin film transistor.

[0148] Figure 11 is a flow chart of a preparation method of an amorphous silicon thin film transistor provided in the embodiment of the present application. The method can be used to prepare the amorphous silicon thin film transistor provided in the above embodiment, for example, the amorphous silicon thin film transistor shown in Figure 3 . Referring to Figure 11 , the method can include the following steps.

[0149] Step 401, forming an amorphous silicon thin film on a substrate.

[0150] In the embodiment of the present application, a substrate 21 can be obtained first, and then a first amorphous silicon sub-film can be deposited on the substrate 21 according to a first film deposition rate, and a second amorphous silicon semiconductor sub-film can be deposited on the first amorphous silicon sub-film away from the substrate 21 according to a second film deposition rate. Thus, an amorphous silicon film can be formed on the substrate 21, and the amorphous silicon film can cover the substrate 21 integrally.

[0151] The second film deposition rate can be greater than the first film deposition rate. For example, the first film deposition rate can be greater than or equal to 4 angstroms per second and less than or equal to 8 angstroms per second, and the second film deposition rate can be greater than or equal to 30 angstroms per second and less than or equal to 50 angstroms per second.

[0152] Optionally, the thickness of the amorphous silicon film can be greater than or equal to 1600 angstroms and less than or equal to 2300 angstroms. The thickness of the first amorphous silicon sub-film can be greater than or equal to 300 angstroms and less than or equal to 600 angstroms, and the thickness of the second amorphous silicon sub-film can be greater than or equal to 1300 angstroms and less than or equal to 1700 angstroms.

[0153] The material of the substrate 21 can include glass or polyimide, etc.

[0154] In step 402, ions are doped into the amorphous silicon film by using an ion implantation process.

[0155] The ion implantation process can be used to dope ions 201X into the amorphous silicon film, so that the depth and quantity (i.e., concentration) of the ions 201X doped into the amorphous silicon film can be controlled more accurately.

[0156] The atmosphere used in the ion implantation process can include phosphine (PH), i.e., the ions 201X can be phosphorus ions. The ion dose used in the ion implantation process can be greater than or equal to e 15 / square centimeter, and the acceleration voltage can be greater than or equal to 20 kilovolts and less than or equal to 30 kilovolts.

[0157] During the ion implantation process, the phosphorus ions in the phosphine can be implanted into the amorphous silicon film, and the phosphorus ions implanted into the amorphous silicon film can increase the conductivity of the amorphous silicon film.

[0158] As shown in FIG. 3B, Figure 12 Figure 12 is a structural schematic diagram of another substrate at the end of step 302, and the amorphous silicon film 301 on the substrate 21 has ions 201X doped by using the ion implantation process.

[0159] In step 403, a wet etching process can be used to etch the side of the amorphous silicon film doped with the ions away from the substrate 21.​

[0160] Please refer to Figure 12 , the ion 201X is implanted into the amorphous silicon thin film 301 by an ion implantation process, and the distribution of the ion 201X in the thickness direction of the amorphous silicon thin film 301 is approximately normal distribution. Alternatively, it can be understood that the amorphous silicon thin film 301 has a third surface and a fourth surface opposite to each other, the third surface is a surface away from the substrate 21, and the second surface is a surface close to the substrate 21. In the direction from the third surface to the fourth surface, the number of ions doped in unit volume in the amorphous silicon thin film 301 first gradually increases and then gradually decreases.

[0161] In the embodiment of the present application, in order to form a better ohmic contact between the finally formed amorphous silicon semiconductor layer and the source and the drain, a wet etching process can be used to etch the surface layer of the amorphous silicon thin film 301 with a smaller number of ions 201X in unit volume, so that the number of ions 201X in unit volume on the side of the etched amorphous silicon thin film away from the substrate 21 is the largest. The etching solution used in the above-mentioned wet etching process can be hydrogen fluoride solution.

[0162] The surface layer of the amorphous silicon thin film 301 with a smaller number of ions in unit volume can refer to the part of the amorphous silicon thin film 301 in which the number of ions doped in unit volume gradually increases in the direction from the third surface to the fourth surface of the amorphous silicon thin film 301.

[0163] It should be noted that the etching thickness of the wet etching process is related to the implantation energy of the ion implantation process. Generally, the greater the ion implantation energy, the greater the ion implantation depth, and correspondingly, the greater the etching thickness of the wet etching process, so as to ensure that the surface layer of the amorphous silicon thin film 301 with a smaller number of ions 201X in unit volume can be etched. For example, the etching thickness of the wet etching process can be greater than or equal to 220 angstroms and less than or equal to 330 angstroms.

[0164] Step 404, forming the source and the drain on the side of the etched amorphous silicon thin film away from the substrate.

[0165] Firstly, a patterning process is performed on the etched amorphous silicon thin film to obtain a patterned amorphous silicon thin film. The orthographic projection of the patterned amorphous silicon thin film on the substrate can cover the orthographic projection of the gate on the substrate.

[0166] Secondly, a metal thin film can be formed on the side of the patterned amorphous silicon thin film away from the substrate 21. The metal thin film can cover the substrate 21 as a whole. Then, a patterning process is performed on the metal thin film to obtain the source 202 and the drain 203.

[0167] As shown in Figure 13 ,Figure 13 is the structure diagram of another substrate at the end of step 404, and the source 202 and the drain 203 are formed on the etched amorphous silicon film 302.

[0168] The orthogonal projection of the source 202 on the substrate 21 overlaps with the orthogonal projection of the etched amorphous silicon film 302 on the substrate 20. The orthogonal projection of the drain 105 on the substrate 20 overlaps with the orthogonal projection of the etched amorphous silicon film 302 on the substrate 20.

[0169] Step 405: performing a first patterning process on the etched amorphous silicon film to obtain an amorphous silicon semiconductor layer.

[0170] Please refer to Figure 4 In the embodiments of the present application, the first patterning process on the etched amorphous silicon film can include: taking the source 202 and the drain 203 as a mask, and etching the surface layer of the region where the channel is located of the amorphous silicon film by using an etching process, so as to etch away the part of the surface layer doped with ions, to obtain the amorphous silicon semiconductor layer (201a and 201b). Please refer to Figure 4 The finally formed amorphous silicon semiconductor layer 201 includes a source contact region 2011, a drain contact region 2012, and a channel region 2013 located between the source contact region 2011 and the drain contact region 2012, the source contact region 2011 and the drain contact region 2012 are both doped with ions 201X, and the channel region 2013 is not doped with ions. The source contact region 2011 is in contact with the source 202, and the drain contact region 2012 is in contact with the drain 203.

[0171] In the above-mentioned first patterning process, the etching thickness of the etching process can be greater than or equal to 500 angstroms. In this way, it can be ensured that the channel region of the amorphous silicon semiconductor layer 201 obtained by etching is not doped with ions or has a small ion concentration, so as to make the drain current of the amorphous silicon thin film transistor small, thereby having a small off-state current.

[0172] In the above-mentioned step 406, since the etched amorphous silicon film can be etched again by taking the source 202 and the drain 203 as a mask, the manufacturing process of the amorphous silicon thin film transistor can be simplified.

[0173] In summary, the embodiments of the present application provide a preparation method of an amorphous silicon thin film transistor. The amorphous silicon semiconductor layer of the amorphous silicon thin film transistor prepared by the method contains ions doped by an ion implantation process in the regions close to the source and the drain, and the concentration of the ions in the surface regions close to the source and the drain of the amorphous silicon semiconductor layer is greater than or equal to 5×10 20atoms / cc. Thus, a good ohmic contact can be formed between the amorphous silicon semiconductor layer and the source and the drain, thereby improving the on-state current of the amorphous silicon thin film transistor.

[0174] The embodiment of the present application further provides a display panel. Figure 3 The display panel 02 can comprise a substrate 21 and a plurality of amorphous silicon thin film transistors 20 provided on the substrate 21. Figure 3 An amorphous silicon thin film transistor 20 is shown on the substrate 21, and the substrate 21 can simultaneously have the amorphous silicon thin film transistor 20 and a low-temperature polysilicon thin film transistor. Figure 3 Or Figure 5 The amorphous silicon thin film transistor 20 shown in the embodiment of the present application.

[0175] Optionally, the substrate has a display area and a peripheral area, and the amorphous silicon thin film transistor is located in the display area; the display panel can further comprise a plurality of low-temperature polysilicon (LTPS) thin film transistors located in the peripheral area.

[0176] The amorphous silicon thin film transistor and the low-temperature polysilicon thin film transistor can be prepared by ion implantation process on the same production line.

[0177] The embodiment of the present application further provides a display device. The display device can comprise a power supply component and the display panel provided in the above embodiment. The power supply component is used to supply power to the display panel.

[0178] Optionally, the display device can be a liquid crystal display device, an organic light-emitting diode (OLED) display device (for example, an active-matrix organic light-emitting diode (AMOLED)), an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator, or any product or component having a display function and a fingerprint recognition function.

[0179] The above description is only optional embodiments of the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An amorphous silicon thin-film transistor, characterized in that, include: An amorphous silicon semiconductor layer, a source electrode, and a drain electrode are sequentially disposed on a substrate. The amorphous silicon semiconductor layer contains ions doped by ion implantation in the regions near the source and drain electrodes, and the concentration of these ions in the surface regions near the source and drain electrodes of the amorphous silicon semiconductor layer is greater than or equal to 5 × 10⁻⁶. 20 ions / cubic centimeter; The amorphous silicon semiconductor layer contains ions at a certain depth in the surface region near the source and drain electrodes, which are doped by the ion implantation process. The concentration of the ions first increases and then decreases with increasing distance from the surface region. The thickness of the region where the ion concentration increases with distance from the surface region is smaller than the thickness of the region where the ion concentration decreases with distance from the surface region.

2. The amorphous silicon thin-film transistor according to claim 1, characterized in that, In the amorphous silicon semiconductor layer, at a first depth in the surface region near the source and drain electrodes, the concentration of the ions is greater than or equal to 3 × 10⁻⁶. 20 ions / cubic centimeter; The first depth is between 0 and 50 angstroms.

3. The amorphous silicon thin-film transistor according to claim 2, characterized in that, At a second depth in the amorphous silicon semiconductor layer near the surface regions of the source and drain electrodes, the concentration of the ions is greater than or equal to 5 × 10⁻⁶. 20 ions / cubic centimeter; The second depth is between 0 and 20 angstroms; In the amorphous silicon semiconductor layer, at a third depth near the surface region of the source and drain electrodes, the concentration of the ions is less than or equal to 5 × 10⁻⁶. 19 ions / cubic centimeter; The third depth is between 600 and 1300 angstroms; At a fourth depth in the surface region near the source and drain electrodes of the amorphous silicon semiconductor layer, the concentration of the ions is less than or equal to 3 × 10⁻⁶. 19 ions / cubic centimeter; The fourth depth is greater than or equal to 1300 angstroms.

4. The amorphous silicon thin-film transistor according to claim 1, characterized in that, The amorphous silicon semiconductor layer includes a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region; The ions are distributed in the source contact region and the drain contact region.

5. The amorphous silicon thin-film transistor according to claim 4, characterized in that, The concentration of the doped ions in the source and drain contact regions near the substrate is less than or equal to 3 × 10⁻⁶. 19 Ions per cubic centimeter.

6. The amorphous silicon thin-film transistor according to claim 4, characterized in that, The concentration of the doped ions in the channel region is less than or equal to 3 × 10⁻⁶. 19 ions / cubic centimeter; The thickness of the channel region, the source contact region, and the drain contact region near the substrate is between 500 and 1000 angstroms.

7. The amorphous silicon thin-film transistor according to claim 1, characterized in that, The ions include phosphate ions.

8. The amorphous silicon thin-film transistor according to claim 1, characterized in that, The amorphous silicon semiconductor layer includes a first amorphous silicon semiconductor layer and a second amorphous silicon semiconductor layer stacked along the side away from the substrate. Wherein, the thickness of the first amorphous silicon semiconductor layer is less than the thickness of the second amorphous silicon semiconductor layer, and the density of the first amorphous silicon semiconductor layer is greater than the density of the second amorphous silicon semiconductor layer.

9. The amorphous silicon thin-film transistor according to claim 8, characterized in that, The ratio of the thickness of the first amorphous silicon semiconductor layer to the thickness of the second amorphous silicon semiconductor layer ranges from 0.1 to 0.

5.

10. The amorphous silicon thin-film transistor according to claim 1, characterized in that, The amorphous silicon semiconductor layer is obtained by sequentially performing ion implantation, wet etching, and a single patterning process on an amorphous silicon thin film.

11. A method for fabricating an amorphous silicon thin-film transistor, characterized in that, The method includes: An amorphous silicon semiconductor layer, a source electrode, and a drain electrode are sequentially formed on a substrate. Before forming the source and the drain, forming the amorphous silicon semiconductor layer includes: An unpatterned amorphous silicon thin film and a buffer layer are sequentially deposited on the substrate, wherein the material of the buffer layer is silicon oxide, silicon nitride, or silicon oxynitride. Ions are implanted onto the surface of the buffer layer on the side away from the substrate using an ion implantation process, and the ions diffuse from the buffer layer to the amorphous silicon thin film. A wet etching process is used to etch the buffer layer doped with the ions and the amorphous silicon thin film doped with the ions to obtain an amorphous silicon semiconductor layer. The concentration of the ions in the surface region near the source and drain electrodes of the amorphous silicon semiconductor layer is greater than or equal to 5 × 10⁻⁶. 20 ions / cubic centimeter; In this embodiment, a certain depth of the surface region of the amorphous silicon semiconductor layer near the source and drain electrodes contains ions doped by an ion implantation process, and the concentration of the ions first increases and then decreases as the distance from the surface region increases. The thickness of the region where the ion concentration increases with distance from the surface region is smaller than the thickness of the region where the ion concentration decreases with distance from the surface region.

12. The method according to claim 11, characterized in that, The process employs a wet etching technique to etch a buffer layer doped with the ions and an amorphous silicon thin film doped with the ions to obtain an amorphous silicon semiconductor layer, comprising: Wet etching process is used to completely etch away the buffer layer and amorphous silicon film outside the active layer region; A wet etching process is used to completely etch away the buffer layer of the active layer region, while retaining the amorphous silicon thin film implanted with the ions; The channel region located between the source contact region and the drain contact region in the retained amorphous silicon thin film is etched, and the ion concentration in the channel region is retained to be less than or equal to 3 × 10⁻⁶. 19 The portion of ions per cubic centimeter.

13. The method according to claim 11, characterized in that, The thickness of the buffer layer is less than the thickness of the amorphous silicon film.

14. The method according to claim 13, characterized in that, The thickness of the buffer layer is between 200 and 300 angstroms; The thickness of the amorphous silicon thin film is between 1400 and 2000 angstroms; The etching thickness of the wet etching process is between 20 and 30 angstroms.

15. The method according to any one of claims 11 to 14, characterized in that, The etching solution used in the wet etching process is an acidic etching solution.

16. The method according to claim 12, characterized in that, The etching thickness of the channel region located between the source contact region and the drain contact region in the retained amorphous silicon thin film is greater than or equal to 500 angstroms.

17. The method according to any one of claims 11 to 14, characterized in that, The atmosphere used in the ion implantation process includes phosphine, and the ion dose is greater than or equal to e 15 Units per square centimeter, accelerating voltage greater than or equal to 20 kV and less than or equal to 30 kV.

18. The method according to any one of claims 11 to 14, characterized in that, The formation of the amorphous silicon thin film on the substrate includes: A first amorphous silicon thin film is deposited on the substrate at a first film deposition rate. A second amorphous silicon semiconductor film is deposited on the side of the first amorphous silicon film away from the substrate at a second film deposition rate. The deposition rate of the first film layer is between 4 and 8 angstroms per second; The deposition rate of the second film layer is between 30 and 50 angstroms per second.

19. A display panel, characterized in that, The display panel includes: a substrate, and a plurality of amorphous silicon thin-film transistors as described in any one of claims 1 to 10 located on the substrate; The substrate simultaneously contains the amorphous silicon thin-film transistor and the low-temperature polycrystalline silicon thin-film crystal.

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