Ferroelectric memory and storage device

Abstract

The application provides a ferroelectric memory and a storage device, which are used for improving the integration and micro ability of a storage unit, and thus reducing the area of the ferroelectric memory. The ferroelectric memory comprises at least one basic unit, and a basic unit in the at least one basic unit comprises a plurality of ferroelectric capacitors and a first transistor; wherein the first transistor comprises a first gate, a first channel, and a first source and a first drain located at two ends of the first channel, and one pole of the plurality of ferroelectric capacitors is formed on the first gate.

Description

Technical Field

[0001] The present application relates to the technical field of data storage, and in particular to a ferroelectric memory and a storage device. Background Art

[0002] Currently, dynamic random access memory (DRAM) has become an essential memory for high-performance computing, and the market demand for DRAM capacity is growing exponentially each year. However, DRAM technology can only be scaled down to the 14nm node. For larger storage capacities, multiple DRAM chips must be stacked, resulting in significant issues with overall memory area, cost, and power consumption. Therefore, ferroelectric random access memory (FRAM) has emerged. FRAM, also known as ferroelectric memory, utilizes the principle that ferroelectric materials change their polarization direction under the influence of an electric field. It offers advantages such as fast read and write speeds, low power consumption, and a small footprint.

[0003] In the prior art, such as Figure 1 As shown, the storage unit in the ferroelectric memory usually adopts a structure in which a ferroelectric capacitor is connected in series with the drain (drain, D) of the transistor, that is, a 1T1C (1 transistor-1 capacity) structure. Figure 1 In the figure, S stands for source, G for gate, and FE for ferroelectric. While this structure offers the advantages of high durability and low operating voltage, its scaling capabilities are limited, making it difficult to adapt to process nodes below 14nm. Summary of the Invention

[0004] The present application provides a ferroelectric memory and a storage device, which are used to improve the integration and miniaturization capability of a storage unit, thereby reducing the area of ​​the ferroelectric memory.

[0005] To achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect, a ferroelectric memory is provided, which includes at least one basic unit, a basic unit of the at least one basic unit including a plurality of ferroelectric capacitors and a first transistor, the first transistor being a full-gate transistor, such as a vertical nanowire transistor; wherein the first transistor includes a first gate, a first channel, and a first source and a first drain located at two ends of the first channel, the first gate can be in a floating state, i.e., the first gate is in a suspended state without a wire externally leading out, the first channel CH1 can be columnar, and one pole of the plurality of ferroelectric capacitors is formed on the first gate.

[0007] In the above technical solution, each basic unit of the ferroelectric memory includes a first transistor and a plurality of ferroelectric capacitors, the first transistor includes a first gate, a first channel, and a first source and a first drain located at two ends of the first channel, and one pole of the plurality of ferroelectric capacitors is formed on the first gate included by the first transistor, so that each ferroelectric capacitor can be equivalent to a storage unit, that is, a plurality of storage units can be integrated on one first transistor, thereby improving the integration and miniaturization capability of the plurality of storage units, and further reducing the area of the ferroelectric memory.

[0008] In a possible implementation manner of the first aspect, the ferroelectric memory further includes a bit line, a source line, and a plurality of word lines, the first source is connected to the source line, the first drain is connected to the bit line, and the other poles of the plurality of ferroelectric capacitors are respectively connected to the plurality of word lines. In the above possible implementation manner, by respectively applying different voltages on the bit line, the source line, and the word lines, the reading and writing of the storage units formed by the plurality of ferroelectric capacitors can be realized.

[0009] In a possible implementation manner of the first aspect, the ferroelectric memory further includes a first voltage line, a second voltage line, and a plurality of third voltage lines, the first source is connected to the first voltage line, the first drain is connected to the second voltage line, and the other poles of the plurality of ferroelectric capacitors are respectively connected to the plurality of third voltage lines. In the above possible implementation manner, by respectively applying different voltages on the first voltage line, the second voltage line, and the plurality of third voltage lines, the reading and writing of the storage units formed by the plurality of ferroelectric capacitors can be realized.

[0010] In a possible implementation manner of the first aspect, the one pole of the plurality of ferroelectric capacitors is the first gate, that is, the first gate is directly used as the one pole of the plurality of ferroelectric capacitors. In the above possible implementation manner, by directly using the first gate as the one pole of the plurality of ferroelectric capacitors, the miniaturization capability of the storage units formed by the plurality of ferroelectric capacitors can be further reduced.

[0011] In a possible implementation of the first aspect, the plurality of ferroelectric capacitors comprises at least one first capacitor and at least one second capacitor, and the at least one first capacitor and the at least one second capacitor are respectively formed on two opposite surfaces of the first gate, for example, the at least one first capacitor is formed on a surface of the first gate close to the first source, and the at least one second capacitor is formed on a surface of the first gate away from the first source. In the possible implementation, by respectively forming the plurality of ferroelectric capacitors on the two opposite surfaces of the first gate, more ferroelectric capacitors can be integrated on the first transistor, that is, more storage units can be integrated on one first transistor, thereby further improving the integration of the plurality of storage units.

[0012] In a possible implementation of the first aspect, the plurality of ferroelectric capacitors and the first transistor are disposed in a metal wiring layer, that is, the ferroelectric memory is formed by a post-process, so that the ferroelectric memory and various controllers can be formed by the same process. In the possible implementation, the process of forming the ferroelectric memory can be simplified, better integration with the memory can be achieved, and the area of the ferroelectric memory can be reduced.

[0013] In a possible implementation of the first aspect, the ferroelectric memory further comprises a second transistor; wherein the second transistor comprises a second gate, a second channel, and a second source and a second drain located at two ends of the second channel, the second source is connected to the first gate, the second drain is connected to the first drain, and the second gate is configured to receive a control signal. In the possible implementation, when reading data from the storage units formed by the plurality of ferroelectric capacitors, the second transistor can be turned on by controlling the control signal to precharge the second gate of the second transistor.

[0014] In a possible implementation of the first aspect, the at least one basic unit comprises a first basic unit and a second basic unit, and the first basic unit and the second basic unit are located in the same layer. For example, when the first basic unit and the second basic unit are located in the same layer, the source line SL and the bit line BL of the first basic unit can be connected to the source line SL and the bit line BL of the second basic unit respectively, or the source line SL and the bit line BL of the first basic unit can be connected to the source line SL and the bit line BL of the second basic unit respectively. In the possible implementation, the above-mentioned sharing of the source line SL or the bit line BL can reduce the number of connections of the source line SL or the bit line BL, ensure a small layout area overhead, and reduce the manufacturing cost by sharing the source line SL or the bit line BL, but the read-write bandwidth is determined by the single-layer storage unit array and cannot be expanded by a multi-layer stacking manner.

[0015] In a possible implementation of the first aspect, the at least one base cell includes a first base cell and a second base cell, and the first base cell and the second base cell can be arranged in different layers by stacking; for example, when the first base cell and the second base cell are arranged in layers, the source line SL of the first base cell and the source line SL of the second base cell can be multiplexed, or the ferroelectric memory further includes an isolation layer arranged between the first base cell and the second base cell. In the possible implementation, by arranging in layers, the layout area overhead can be ensured to be small, and by arranging in layers with the isolation layer, the read-write bandwidth can be further expanded, and the read-write bandwidth can be proportional to the number of layers.

[0016] In a possible implementation of the first aspect, the plurality of ferroelectric capacitors correspond to a plurality of storage units, when writing data into a target storage unit in the plurality of storage units, the voltage difference between the first source and the first drain is equal to 0, and the absolute value of the voltage difference between the other pole of the ferroelectric capacitor corresponding to the target storage unit and the first drain is equal to a first specified voltage. In the possible implementation, the writing data of the target storage unit can be implemented, and when the voltage difference between the first source and the first drain is equal to 0, the leakage current of the write operation can be suppressed.

[0017] In a possible implementation of the first aspect, the other pole of the ferroelectric capacitor corresponding to the target storage unit in the plurality of ferroelectric capacitors, except the target storage unit, is in a floating state or the absolute value of the voltage difference between the two is less than one-half of the first specified voltage or. In the possible implementation, the state of the unselected storage unit can be ensured to be unaffected during the writing data process.

[0018] In a possible implementation of the first aspect, the plurality of ferroelectric capacitors form a plurality of storage units, when reading data from a target storage unit in the plurality of storage units, the bias voltage of the first source is 0, the bias voltage of the first drain is a second specified voltage, and the bias voltage of the other pole of the ferroelectric capacitor corresponding to the target storage unit is a third specified voltage; optionally, the data of the target storage unit can be written back after reading the data. In the possible implementation, the reading data of the target storage unit can be implemented, and the data in the target storage unit can be ensured to be consistent before and after the reading operation after the reading data is completed.

[0019] In a possible implementation of the first aspect, the other pole of the ferroelectric capacitor corresponding to the storage unit in the plurality of storage units, except the target storage unit, is in a floating state or grounded. In the possible implementation, the state of the storage unit in the unselected base cell can be ensured to be unaffected during the reading data process.

[0020] In a second aspect, a ferroelectric memory is provided, which includes at least one basic unit, and a basic unit in the at least one basic unit includes a plurality of ferroelectric capacitors and a first transistor, and the first transistor can be a full-gate transistor, such as a vertical nanowire transistor; wherein the first transistor includes a first gate, a first channel, and a first source and a first drain located at two ends of the first channel, the first gate can be in a floating state, that is, the first gate is in a suspended state without external wires, the first channel CH1 can be columnar, and one pole of the plurality of ferroelectric capacitors is formed on one of the first source or the first drain. In the above technical solution, by forming one pole of the plurality of ferroelectric capacitors on one of the first source or the first drain, each ferroelectric capacitor can be equivalent to a storage unit, that is, a plurality of storage units can be integrated on one first transistor, thereby improving the integration and miniaturization capability of the plurality of storage units, and further reducing the area of the ferroelectric memory.

[0021] In a possible implementation manner of the second aspect, the other poles of the plurality of ferroelectric capacitors are respectively coupled to a plurality of source lines or a plurality of bit lines; for example, if one pole of the plurality of ferroelectric capacitors is formed on the first source, the ferroelectric memory further includes a plurality of source lines, a bit line, and a word line, the first gate is connected to the word line, the first drain is connected to the bit line, and the other poles of the plurality of ferroelectric capacitors are respectively coupled to the plurality of source lines; or, if one pole of the plurality of ferroelectric capacitors is formed on the first drain, the ferroelectric memory further includes a plurality of bit lines, a source line, and a word line, the first gate is connected to the word line, the first source is connected to the source line, and the other poles of the plurality of ferroelectric capacitors are respectively coupled to the plurality of bit lines. In the above possible implementation manner, by respectively applying different voltages on the bit lines, the source lines, and the word lines, the reading and writing of the storage units formed by the plurality of ferroelectric capacitors can be realized.

[0022] In a possible implementation manner of the second aspect, one pole of the plurality of ferroelectric capacitors is the first source, that is, the first source is directly used as one pole of the plurality of ferroelectric capacitors; or one pole of the plurality of ferroelectric capacitors is the first drain, that is, the first drain is directly used as one pole of the plurality of ferroelectric capacitors. In the above possible implementation manner, by directly using the first source or the first drain as one pole of the plurality of ferroelectric capacitors, the miniaturization capability of the storage units formed by the plurality of ferroelectric capacitors can be further reduced.

[0023] In a third aspect, a storage device is provided, which includes a circuit board and a ferroelectric memory connected to the circuit board, and the ferroelectric memory is the ferroelectric memory provided in the first aspect, any possible implementation manner of the first aspect, or the second aspect.

[0024] In a fourth aspect, a storage device is provided, comprising a controller and a ferroelectric memory, the controller being configured to control reading and writing of the ferroelectric memory, the ferroelectric memory being the ferroelectric memory provided in the first aspect, any one of the possible implementation manners of the first aspect, or the second aspect.

[0025] It can be understood that the storage device and the non-transitory computer readable storage medium used with the computer provided in any one of the above aspects comprise the same or corresponding features of the ferroelectric memory provided above, and thus the beneficial effects achieved thereby can refer to the beneficial effects of the corresponding integrated circuit provided above, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A structural schematic diagram of a storage unit provided in the prior art;

[0027] Figure 2 A structural schematic diagram of a storage device provided in an embodiment of the present application;

[0028] Figure 3 A structural schematic diagram of a ferroelectric memory provided in an embodiment of the present application;

[0029] Figure 4 A structural schematic diagram of another ferroelectric memory provided in an embodiment of the present application;

[0030] Figure 5 A structural schematic diagram of another ferroelectric memory provided in an embodiment of the present application;

[0031] Figure 6 A structural schematic diagram of another ferroelectric memory provided in an embodiment of the present application;

[0032] Figure 7 A structural schematic diagram of another ferroelectric memory provided in an embodiment of the present application;

[0033] Figure 8 A structural schematic diagram of another ferroelectric memory provided in an embodiment of the present application;

[0034] Figure 9 A structural schematic diagram of another ferroelectric memory provided in an embodiment of the present application;

[0035] Figure 10 A structural schematic diagram of another ferroelectric memory provided in an embodiment of the present application;

[0036] Figure 11 A connection schematic diagram of a control circuit provided in an embodiment of the present application;

[0037] Figure 12A charge diagram when reading data is provided for an embodiment of the present application;

[0038] Figure 13 Another charge diagram when reading data is provided for an embodiment of the present application;

[0039] Figure 14 Yet another charge diagram when reading data is provided for an embodiment of the present application;

[0040] Figure 15 A pre-charge diagram is provided for an embodiment of the present application;

[0041] Figure 16 Another structure diagram of a ferroelectric memory is provided for an embodiment of the present application;

[0042] Figure 17 A diagram of applied voltages when reading and writing data is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0043] The making and using of various embodiments are discussed in detail below. It should be appreciated that the specific embodiments discussed are merely illustrative of the many suitable applications of the present application. Thus, the scope of the present application should not be limited to the specific embodiments discussed, but should be given the full scope of the appended claims.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.

[0045] Circuits or other components can be described as or said to be "configured to" perform a task or tasks. In such contexts, "configured to" is used to connote structure by indicating that the circuits / components include structure (e.g., circuitry) that performs the task or tasks during operation. As such, the circuit / component can be said to be configured to perform the task even when the specified circuit / component is not currently operational (e.g., is not on). Structured circuits / components referred to as being "configured to" perform one or more tasks are appropriate in instances where the task is performed via the specified structure alone, where the task is performed via the specified structure in combination with information and / or instructions, and where the task is performed by the specified structure using a combination of hardware and software.

[0046] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" means one or more, and "multiple" means two or more. The association relationship of the associated objects is described by "and / or", which means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single item or multiple items. For example, at least one of a, b or c can represent a, b, c, a and b, a and c, b and c, or a, b and c, where a, b and c can be single or multiple. In addition, in the embodiments of the present application, "first", "second", etc. do not limit the quantity and order.

[0047] It should be noted that in the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of the words "exemplary" or "for example" is intended to present the relevant concept in a specific manner.

[0048] The technical solutions of the present application can be applied to various storage systems using ferroelectric memories, for example, the technical solutions of the present application can be applied to computers, and can also be applied to storage systems including memories or storage systems including processors and memories, where the processor can be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor, and a neural network processor, etc. Exemplarily, Figure 2 A structural schematic diagram of a storage system provided by the embodiments of the present application is shown, which can include a ferroelectric memory. Optionally, the storage system can also include a CPU, a cache, a controller, etc. Wherein, the CPU, the cache, the controller and the ferroelectric memory can be integrated together, the ferroelectric memory can be coupled with the cache through the controller, and coupled with the CPU through the cache and the controller.

[0049] Figure 3A structure schematic diagram of a ferroelectric memory is provided in the embodiments of the present application, the ferroelectric memory comprises at least one basic unit, each of the at least one basic unit comprises a first transistor T1 and a plurality of ferroelectric capacitors C, the number of the plurality of ferroelectric capacitors C can be n, n is a positive integer. In the embodiments of the present application, the first transistor T1 comprises a first gate G1, a first channel CH1, and a first source 1 and a first drain 2 located at two ends of the first channel CH1, and one pole a of the plurality of ferroelectric capacitors C is formed on the first gate G1. Figure 3 The number n of the plurality of ferroelectric capacitors C is taken as an example of 4, and the structure of each basic unit can also be referred to as a 1TnC structure.

[0050] In the embodiments of the present application, the first transistor T1 can be a gate-all-around (GAA) transistor, the first gate G1 can be in a floating state, that is, the first gate G1 is in a suspended state without an external wire, and the first channel CH1 can be columnar. In actual applications, the first transistor T1 can also be a transistor of other structures or types, and the embodiments of the present application do not make specific limitations in this regard. In the embodiments of the present application, only the first transistor T1 is taken as an example of a GAA transistor.

[0051] In addition, each of the plurality of ferroelectric capacitors C comprises two poles (one pole is a and the other pole is b), and a ferroelectric dielectric c located between the two poles a and b, the ferroelectric dielectric c can adopt a ferroelectric material, for example, the ferroelectric material can be hafnium zirconate (HfZrO2) and the like. The one pole a of the plurality of ferroelectric capacitors C being formed on the first gate G1 can mean that the first gate G1 is directly used as the one pole a of the plurality of ferroelectric capacitors C, or a metal plate is formed on the first gate G1, and the metal plate is used as the one pole a of the plurality of ferroelectric capacitors C.

[0052] In the embodiments of the present application, each basic unit of the ferroelectric memory comprises a first transistor T1 and a plurality of ferroelectric capacitors C, the first transistor T1 comprises a first gate G1, a first channel CH1, and a first source 1 and a first drain 2 located at two ends of the first channel CH1, and one pole a of the plurality of ferroelectric capacitors C is formed on the first gate G1 included in the first transistor T1, so that each ferroelectric capacitor can be equivalent to a storage unit, that is, a plurality of storage units can be integrated on one first transistor T1, thereby improving the integration and miniaturization capability of the plurality of storage units, and further reducing the area of the ferroelectric memory.

[0053] Optionally, as Figure 4As shown, the multiple ferroelectric capacitors C may include at least one first capacitor C1 and at least one second capacitor C2, and the at least one first capacitor C1 and the at least one second capacitor C2 are respectively formed on two opposite surfaces of the first gate G1. For example, the at least one first capacitor C1 is formed on the surface of the first gate G1 close to the first source 1, and the at least one second capacitor C2 is formed on the surface of the first gate G1 away from the first source 1. Figure 4 In the description, an example is given in which the number n of the multiple ferroelectric capacitors C is equal to 8. By forming the multiple ferroelectric capacitors C on two opposite surfaces of the first gate G1, a greater number of ferroelectric capacitors can be integrated on the first transistor T1. In other words, a greater number of memory cells can be integrated on one first transistor T1, thereby further improving the integration density of the multiple memory cells.

[0054] Further, such as Figure 5 As shown in (a), each basic unit in at least one basic unit may further include a first voltage line L1, a second voltage line L2 and a plurality of third voltage lines L3. The first source 1 is connected to the first voltage line L1, the first drain 2 is connected to the second voltage line L2, and the other poles b of the plurality of ferroelectric capacitors C are respectively connected to the plurality of third voltage lines L3, that is, the other pole b of a ferroelectric capacitor is connected to a third voltage line L3. Optionally, the first voltage line L1 is parallel to the second voltage line L2, and the second voltage line L2 is perpendicular to the plurality of third voltage lines L3. It should be noted that, Figure 5 In the description, the case where multiple ferroelectric capacitors C are formed on one surface of the first gate G1 is taken as an example. The same is applicable to the case where multiple ferroelectric capacitors C are formed on two opposite surfaces of the first gate G1.

[0055] In one example, Figure 5 As shown in (a), the first voltage line L1 can be a source line (SL), the second voltage line L2 can be a bit line (BL), and the third voltage line L3 can be a word line (WL). The first voltage line L1 and the third voltage line L3 do not contact each other. For example, the first voltage line L1 and the third voltage line L3 can be located in different layers. The following description uses the example of the first voltage line L1 being the source line SL, the second voltage line L2 being the bit line BL, and the third voltage line L3 being the word line WL. Figure 5 (b) is an equivalent circuit diagram of a basic unit provided in an embodiment of the present application, where a plurality of word lines WL are respectively represented as WL1 to WLn.

[0056] It should be noted that the source line SL here can be understood as another bit line BL, that is, the function of the source line SL is similar to that of the bit line BL, and multiple storage cells connected to a source line SL and a bit line BL can be selected through the source line SL and the bit line BL.

[0057] Furthermore, when at least one basic unit includes multiple basic units, these multiple basic units can be located in the same layer or stacked in different layers. The following description will be made using an example where at least one basic unit includes a first basic unit and a second basic unit.

[0058] In the first embodiment, when the first basic unit and the second basic unit are located in the same layer, as shown in FIG. Figure 6 As shown, the source line SL and the bit line BL of the first basic unit can be connected to the source line SL and the bit line BL of the second basic unit respectively; or, when the first basic unit and the second basic unit are located in the same layer, as shown Figure 7 As shown, the multiple word lines WL of the first basic unit can be connected to the multiple word lines WL of the second basic unit respectively. Further, when at least one basic unit includes more than two basic units, as shown in FIG. Figure 8 As shown, a ferroelectric memory including a memory cell array can be formed by the two methods described above. The memory cell array can include memory cells in multiple rows and columns.

[0059] In the second embodiment, Figure 9 As shown, when the first basic unit and the second basic unit are stacked in different layers, the source line SL of the first basic unit and the source line SL of the second basic unit can be reused, that is, the first basic unit and the second basic unit share the same source line SL, or the first basic unit and the second basic unit can share the same bit line BL; or Figure 10 As shown, when the first basic cell and the second basic cell are stacked in different layers, the ferroelectric memory further includes an isolation layer disposed between the first basic cell and the second basic cell, so that each basic cell has an independent source line SL, bit line BL, and word line WL. The aforementioned method of sharing the source line SL or bit line BL can reduce the number of connections to the source line SL or bit line BL, ensuring a low layout area overhead. Sharing the source line SL or bit line BL can also reduce manufacturing costs. However, the read and write bandwidth is determined by a single-layer memory cell array and cannot be expanded through multi-layer stacking. The aforementioned method of providing an isolation layer can also ensure a low layout area overhead and expand the read and write bandwidth through stacking, with the read and write bandwidth being proportional to the number of stacked layers.

[0060] Further, when the at least one basic cell includes a plurality of basic cells, by combining the combination manners of different basic cells in the above two embodiments, a multi-layer storage cell array arranged in a stack manner can be obtained, so as to further improve the integration and miniaturization of the plurality of storage cells in the ferroelectric memory and reduce the area of the ferroelectric memory. Through actual measurement, the storage cell array provided in the ferroelectric memory can realize a minimum storage cell area of 4F 2 , and the ferroelectric memory based on the stack structure can realize a miniaturized equivalent storage cell area of 2F 2 , 1.33F 2 or 1F 2 , etc.

[0061] Further, as shown in (a) and (b) of Figure 11 , when the ferroelectric memory in a three-dimensional stack manner is formed by a stack manner, the BLs (such as BL0 and BL1) of the basic cells in different layers can be connected to the same BL controller and sensitive amplifier, etc., the SLs (such as SL0 and SL1) of the basic cells in different layers can be connected to the same SL controller, such as the connection of the SLs and the BLs in different layers is realized by metal wiring and through holes. In addition, the WLs in different layers can be independent of each other, such as the WLs (such as WL0 and WL1) in different layers are connected to the WL control circuit with a gating function. In addition, the ferroelectric memory can be located in a metal wiring layer, that is, the ferroelectric memory is formed by a back-end process, so that the ferroelectric memory and various controllers can be formed by the same process.

[0062] For the above several different ferroelectric memories, different voltages can be applied on the source lines SL, the bit lines BL and the plurality of word lines WL by the corresponding controllers (or the other poles b of the plurality of ferroelectric capacitors C and the first source 1 and the first drain 2), that is, different voltages can be applied on the first source 1, the first drain 2 and the plurality of ferroelectric capacitors C, so as to realize the read and write of the plurality of storage cells composed of the plurality of ferroelectric capacitors C, that is, write data to the plurality of storage cells or read data from the plurality of storage cells.

[0063] Specifically, when data is written to a target storage cell in the plurality of storage cells formed by a basic cell, the SL and the BL in the basic cell can be set to the same potential, that is, the voltage difference between the SL and the BL is 0 (such as the same voltage is applied on the SL and the BL), so as to suppress the leakage current of the write operation; at the same time, a voltage is applied on the WL corresponding to the target storage cell, so that the absolute value of the voltage difference between the WL corresponding to the target storage cell and the BL is equal to a first specified voltage Vw. As shown in (a) of Figure 12 , if the voltage difference between the WL corresponding to the target storage cell and the BL is equal to Vw (such as 0 potential is applied on the SL and the BL, and V W), the ferroelectric medium c in the target memory cell is positively polarized, and the target memory cell is written to the "0" state; Figure 12 As shown in (b), if the voltage difference between WL and BL corresponding to the target memory cell is equal to -Vw (for example, V is applied to SL and BL respectively), W , applying 0 potential to the WL corresponding to the target memory cell), the ferroelectric dielectric c in the target memory cell is negatively polarized, and the target memory cell is written to the "1" state.

[0064] Furthermore, during the data writing process, for other memory cells in the plurality of memory cells in the basic unit, excluding the target memory cell, the absolute value of the voltage difference between the WL and BL corresponding to the other memory cells can be set to less than 1 / 2 Vw, thereby ensuring that the states of the other memory cells remain unchanged. For other memory cells in at least one basic unit that do not require data writing, the SL, BL, and multiple WLs in the other memory cells can all be set to 1 / 2 Vw, or the SL, BL, and multiple WLs in the other memory cells can be placed in a floating state, thereby preventing erroneous writing to unselected memory cells.

[0065] Specifically, when reading data from a target memory cell among a plurality of memory cells formed by a basic unit, it is necessary to precharge the first gate G1 before reading the data, that is, to charge the first gate G1 to a certain potential, and then perform the data reading operation, that is, to set the SL in the basic unit to 0 potential and the BL to the second specified voltage V BLR , set the WL corresponding to the target storage unit to V WLR .

[0066] like Figure 13 As shown in (a), if the data in the target memory cell is "0", the positive polarization of the ferroelectric dielectric c in the target memory cell is strengthened. At this time, the first gate G1 near the ferroelectric dielectric c attracts some positive charges, and a small amount of negative charges is induced at the first gate G1 near the first channel CH1, thereby inducing a small amount of positive charges on the surface of the first channel CH1, and then reading a low current, that is, reading the data "0". Figure 13 (b) is a schematic diagram of the polarization state of the ferroelectric medium c corresponding to the reading of data "0", V represents the applied voltage on WL corresponding to the target storage unit, P represents the polarization strength of the corresponding ferroelectric medium c, and Q0 represents the change in polarization charge.

[0067] like Figure 14As shown in (a), if the data in the target memory cell is "1", the negative polarization of the ferroelectric dielectric c in the target memory cell is weakened or converted to a positive polarization state. At this time, a large amount of negative charges bound by the negatively polarized ferroelectric in the first gate G1 are released, and a large amount of negative charges are induced at the first gate G1 near the first channel CH1, thereby inducing a large amount of positive charges on the surface of the first channel CH1, and then reading a high current, that is, reading the data "1". Figure 14 (b) is a schematic diagram of the polarization state of the ferroelectric medium c corresponding to the reading of data "1", where V represents the applied voltage on WL corresponding to the target storage unit, P represents the polarization strength of the corresponding ferroelectric medium c, and Q1 represents the change in polarization charge.

[0068] Furthermore, during the data reading process, for other memory cells in the plurality of memory cells in the basic unit, excluding the target memory cell, the WL corresponding to the other memory cells can be grounded or set to a floating state, thereby ensuring that the states of the other memory cells remain unchanged. For other basic cells in the at least one basic unit for which data reading is not required, the SL and BL in the other basic cells can be set to 0 potential, thereby ensuring that no leakage current is generated in the unselected basic cells.

[0069] It should be noted that the data reading process described above is achieved by destroying the polarization state of the ferroelectric element to modulate the potential of the first gate G1, thereby modulating the read current of the first transistor T1. Therefore, it is a destructive read. After reading the data from the target memory cell, the data in the corresponding target memory cell can be restored by writing data, that is, the storage state in the target memory cell is not lost through data write-back.

[0070] Furthermore, precharging the first gate G1 may include the following different methods, which are described in detail below.

[0071] The first one, such as Figure 15 As shown in (a), each basic unit further includes a second transistor T2, which includes a second gate G2, a second source 3, and a second drain 4. The second source 3 is connected to the first gate G1, and the second drain 4 is connected to the first drain 2. The second gate G2 is used to receive a control signal, which turns on the second transistor T2 to pre-charge the first gate G1. The second transistor T2 can have the same structure as the first transistor T1. For example, the second transistor T2 can also be a GAA transistor, which is not specifically limited in this embodiment of the present application.

[0072] The second type, such as Figure 15As shown in (b), during the data writing process, by setting SL and BL to different potentials, that is, SL and BL are not equal to each other, the first transistor T1 generates a leakage current, thereby precharging the first gate G1 through the leakage current.

[0073] The third type, such as Figure 15 As shown in (c), the electrical neutrality of the first gate G1 is achieved through the auxiliary bit, which is equivalent to the pre-charging of the first gate G1, that is, each storage unit (referred to as a storage bit) is correspondingly provided with a corresponding auxiliary storage unit (referred to as an auxiliary bit), and the storage states of the two are opposite. For example, if data "1" is stored in a storage unit, the corresponding auxiliary storage unit stores data "1", and if data "0" is stored in a storage unit, the corresponding auxiliary storage unit stores data "0".

[0074] The fourth type, such as Figure 15 As shown in (d), a nonlinear two-terminal selector (eg, a switch or a diode) is connected in series to the first gate G1, and the first gate G1 is precharged by connecting the two-terminal selector (eg, closing the switch or turning on the diode).

[0075] For example, when each basic unit further includes a second transistor T2 in the first pre-charging mode, the structure of the basic unit can be called a 2TnC structure. Figure 16 As shown, by combining the basic units of the 2TnC structure, a three-dimensional stacked ferroelectric memory can also be obtained. In addition, in the three-dimensional stacked ferroelectric memory, all SLs in the same layer can be connected together, and all second gates G2 in the same layer can be connected together via the same control line CTL. It should be noted that the method of combining the basic units of the 2TnC structure is similar to the method of combining the basic units of the 1TnC structure described above, and the embodiments of this application will not be repeated here.

[0076] Specifically, such as Figure 17 As shown, for a basic cell of a 2TnC structure, when writing data to a target memory cell among the multiple memory cells formed by the basic cell, a certain voltage is applied to CTL, turning on the second transistor T2 to transfer the potential on BL to the first gate G1. At this time, SL can be set to 1 / 2Vw. If the potential on BL is -1 / 2Vw and the voltage of WL corresponding to the target memory cell is a positive voltage (for example, 1 / 2Vw), data "0" can be written; if the potential on BL is 1 / 2Vw and the voltage of WL corresponding to the target memory cell is a negative voltage (for example, -1 / 2Vw), data "1" can be written. When writing data "0" or "1", the second transistor T2 is always in the off state. Figure 17BL0 and G10 respectively represent the voltages of BL and G1 corresponding to writing data "0", BL1 and G11 respectively represent the voltages of BL and G1 corresponding to writing data "1", Vdd represents a fixed power supply voltage, and Vth represents the threshold voltage of the second transistor T2.

[0077] Specifically, such as Figure 17 As shown, for a basic cell of a 2TnC structure, before reading data from a target memory cell among the multiple memory cells formed by the basic cell, when precharging the first gate G1, a certain voltage can be applied to CTL, turning on the second transistor T2 to transfer the potential on BL (i.e., the threshold voltage Vth of the second transistor T2) to the first gate G1. The potentials on SL and WL corresponding to the target memory cell are also set to Vth. At this time, the potential of the first gate G1 can be pulled up to Vth through the precharging operation.

[0078] like Figure 17 As shown, when reading data from a target memory cell among the multiple memory cells formed by the basic unit, the second transistor T2 is turned off. In addition, the potential of SL is set to VR_SL, and the potential of WL corresponding to the target memory cell is set to VR_WL. If the data stored in the target memory cell at this time is "0", the ferroelectric polarization state does not reverse, the second transistor T2 is turned on, and the potential on BL gradually rises from Vth to a certain potential; if the data stored in the target memory cell at this time is "1", the ferroelectric polarization state is reversed, the second transistor T2 is turned off, and the potential on BL still remains at Vth. In this way, the corresponding data "0" and "1" can be read according to the high and low BL potentials corresponding to the data "0" and "1". VR_SL: "0" represents the voltage of BL when reading data. The above reading process is also a destructive reading. After reading the data, the read target memory cell can be rewritten to ensure that the storage state in the target memory cell does not change.

[0079] In the ferroelectric memory provided in the embodiment of the present application, in the above-mentioned method for reading and writing the storage cells in the ferroelectric memory, if the selected target storage cells are multiple storage cells with the same WL or the same BL, the above-mentioned reading and writing method can also be used to achieve parallel writing or reading of data for multiple storage cells with the same WL or the same BL, thereby greatly improving the reading and writing efficiency of the ferroelectric memory.

[0080] In addition, the ferroelectric memory in the above embodiments includes a structure in which one electrode a of a plurality of capacitors C is formed on the first gate G1 of the first transistor T1. Figure 1The one pole a of the plurality of capacitors C can also be formed on the first source 1 or the first drain 2 of the first transistor T1 in the structure of the first transistor T1. For example, the ferroelectric memory includes at least one basic unit, and each of the at least one basic unit includes a first transistor and a plurality of ferroelectric capacitors, and the number of the plurality of ferroelectric capacitors can be n, where n is a positive integer. In the embodiment of the present application, the first transistor includes a first gate, a first channel, and a first source and a first drain located at two ends of the first channel. The one pole of the plurality of ferroelectric capacitors is formed on the first source or the first drain. In other words, in the embodiment of the present application, the first gate or the first source of the first transistor in the basic unit of the ferroelectric memory is formed with a plurality of ferroelectric capacitors in a similar manner as described in the above embodiment, and the other pole of each ferroelectric capacitor is connected to a bit line or a source line. Thus, the structure of the source or the drain of a transistor in a basic unit coupled to a plurality of bit lines or source lines through a ferroelectric capacitor is formed.

[0081] In the embodiment of the present application, the plurality of ferroelectric capacitors are formed on the first source or the first drain, the connection mode of the basic unit to the source line, the bit line and the word line, and the combination mode between a plurality of basic units in this mode are similar to the plurality of ferroelectric capacitors formed on the first gate, the connection mode of the basic unit to the source line, the bit line and the word line, and the combination mode between a plurality of basic units described above. For details, refer to the above embodiment or set based on requirements.

[0082] Based on this, the embodiment of the present application also provides a storage device, which includes a circuit board and a ferroelectric memory connected to the circuit board, and the ferroelectric memory can be any one of the ferroelectric memories provided above. Wherein, the circuit board can be a printed circuit board (PCB), and of course the circuit board can also be a flexible circuit board (FPC), etc., and the embodiment does not limit the circuit board. Optionally, the storage device is a computer, a mobile phone, a tablet computer, a wearable device, a vehicle-mounted device and different types of user equipment or terminal equipment such as a base station and a network device.

[0083] Optionally, the storage device further includes a packaging substrate fixed to the printed circuit board PCB by solder balls, and the ferroelectric memory is fixed to the packaging substrate by solder balls.

[0084] Based on this, the embodiment of the present application also provides a storage device, which includes a controller and a ferroelectric memory, and the controller is used to control reading and writing in the ferroelectric memory, and the ferroelectric memory can be any one of the ferroelectric memories provided above.

[0085] It should be noted that the description of the three-dimensional ferroelectric memory can refer to the description of the ferroelectric memory in the above Figures 2-11 and will not be repeated here.

[0086] Finally, it should be noted that the above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any change or replacement within the technical scope disclosed in the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A ferroelectric memory, characterized by, The ferroelectric memory comprises at least one basic unit, the at least one basic unit comprises a first basic unit and a second basic unit, the first basic unit and the second basic unit are arranged in a stack, and an isolation layer is arranged between the first basic unit and the second basic unit, each basic unit in the at least one basic unit comprises a plurality of ferroelectric capacitors and a first transistor; The first transistor comprises a first gate, a first channel, and a first source and a first drain located at two ends of the first channel, the first transistor is a full-ring gate transistor, the first channel is columnar, the first gate is arranged with a spacing at two ends of the first channel and surrounds the periphery of the first channel, and the first gate is strip-shaped and the length direction is perpendicular to the axial direction of the first channel; One pole of the plurality of ferroelectric capacitors is formed on the first gate, and the other poles of the plurality of ferroelectric capacitors are independent of each other, and the plurality of ferroelectric capacitors correspond to form a plurality of storage units.

2. The ferroelectric memory of claim 1, wherein, The ferroelectric memory further comprises a bit line, a source line and a plurality of word lines, the first source is connected to the source line, the first drain is connected to the bit line, and the other poles of the plurality of ferroelectric capacitors are respectively connected to the plurality of word lines.

3. The ferroelectric memory of claim 1, wherein, The ferroelectric memory further comprises a first voltage line, a second voltage line and a plurality of third voltage lines, the first source is connected to the first voltage line, the first drain is connected to the second voltage line, and the other poles of the plurality of ferroelectric capacitors are respectively connected to the plurality of third voltage lines.

4. The ferroelectric memory of claim 1, wherein, The one pole of the plurality of ferroelectric capacitors is the first gate.

5. The ferroelectric memory of claim 1, wherein, The plurality of ferroelectric capacitors comprises at least one first capacitor and at least one second capacitor, the at least one first capacitor is formed on a surface of the first gate close to the first source, and the at least one second capacitor is formed on a surface of the first gate away from the first source.

6. The ferroelectric memory of claim 1, wherein, The plurality of ferroelectric capacitors and the first transistor are arranged in a metal wiring layer.

7. The ferroelectric memory of claim 1, wherein, The ferroelectric memory further comprises a second transistor; The second transistor comprises a second gate, a second channel, and a second source and a second drain located at two ends of the second channel, the second source is connected to the first gate, the second drain is connected to the first drain, and the second gate is used to receive a control signal.

8. The ferroelectric memory of any one of claims 1-7, wherein, When writing data into a target storage unit in the plurality of storage units, the voltage difference between the first source and the first drain is equal to 0, and the absolute value of the voltage difference between the other pole of the ferroelectric capacitor corresponding to the target storage unit and the first drain is equal to a first specified voltage.

9. The ferroelectric memory of claim 8, wherein, The other pole of the ferroelectric capacitor corresponding to a target storage unit other than the target storage unit in the plurality of ferroelectric capacitors and the first drain are in a floating state or the absolute value of the voltage difference therebetween is less than one-half of the first specified voltage.

10. The ferroelectric memory of any one of claims 1-7, wherein, When reading data from a target storage unit in the plurality of storage units, the bias voltage of the first source is 0, the bias voltage of the first drain is a second specified voltage, and the bias voltage of the other pole of the ferroelectric capacitor corresponding to the target storage unit is a third specified voltage.

11. The ferroelectric memory of claim 10, wherein, Another pole of the ferroelectric capacitor corresponding to the storage unit other than the target storage unit among the plurality of storage units is in a floating state or is grounded.

12. A ferroelectric memory, comprising: The ferroelectric memory comprises at least one basic unit, the at least one basic unit comprises a first basic unit and a second basic unit, the first basic unit and the second basic unit are arranged in a stack, and an isolation layer is arranged between the first basic unit and the second basic unit, each basic unit in the at least one basic unit comprises a plurality of ferroelectric capacitors and a first transistor; The first transistor comprises a first gate, a first channel, and a first source and a first drain located at two ends of the first channel, the first transistor is a full-ring gate transistor, the first channel is columnar, the first gate is arranged with a spacing at two ends of the first channel and surrounds the periphery of the first channel, the first gate is strip-shaped and the length direction is perpendicular to the axial direction of the first channel; One pole of the plurality of ferroelectric capacitors is formed on one pole of the first source or the first drain, and the other poles of the plurality of ferroelectric capacitors are independent of each other, and the plurality of ferroelectric capacitors correspond to form a plurality of storage units.

13. The ferroelectric memory of claim 12, wherein, The other poles of the plurality of ferroelectric capacitors are respectively coupled to a plurality of source lines or a plurality of bit lines.

14. The ferroelectric memory of claim 12 or 13, wherein, One pole of the plurality of ferroelectric capacitors is the first source, or one pole of the plurality of ferroelectric capacitors is the first drain.

15. A storage device, comprising: The storage device comprises a circuit board and a ferroelectric memory connected to the circuit board, and the ferroelectric memory is the ferroelectric memory according to any one of claims 1-14.

16. A storage device, comprising: The storage device comprises a controller and a ferroelectric memory, the controller is used for controlling reading and writing of the ferroelectric memory, and the ferroelectric memory is the ferroelectric memory according to any one of claims 1-14.

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