A reference voltage buffer circuit and device

Abstract

The present invention provides a reference voltage buffer circuit and a device. The circuit includes a feedback module and an output module. The feedback module includes a first voltage input terminal and a second voltage input terminal. The output module includes a first voltage output terminal and a second voltage output terminal. The circuit further includes a first level conversion module and a second level conversion module. Both the first level conversion module and the second level conversion module are connected to the feedback module. The feedback module is connected to the output module. The first level conversion module is used to perform voltage translation on the first input voltage input by the first voltage input terminal, so as to reduce the minimum voltage value of the first output voltage output by the first voltage output terminal. The second level conversion module is used to perform voltage translation on the second input voltage input by the second voltage input terminal, so as to increase the maximum voltage value of the second output voltage output by the second voltage output terminal. The present invention has the effect of increasing the voltage range of the output voltage.

Description

Technical Field

[0001] The present invention belongs to the technical field of buffers, and particularly relates to a reference voltage buffer circuit and device. Background Art

[0002] In an analog-to-digital conversion circuit, a bandgap reference circuit is generally built-in. However, the voltage generated by the bandgap reference is difficult to drive large capacitors in the analog-to-digital conversion circuit, and a buffer stage needs to be added to enhance the driving ability. There are generally two design schemes for the reference voltage buffer circuit. One is to externally connect a large capacitor through a pin to reduce the influence of the analog-to-digital converter on the reference voltage fluctuation by the large capacitor. The second is to increase the bandwidth of the buffer to pull back the reference voltage within a specified time. For an analog-to-digital converter, a large reference voltage is beneficial to improving the performance of the converter. The larger the reference voltage, the larger the conversion range, and the larger the input signal, which is very helpful for improving the signal-to-noise ratio.

[0003] The reference voltage buffer circuit in the related art usually includes two branches, namely a feedback branch and an output branch. The feedback branch includes two amplifiers and several MOS transistors. First, an input voltage is generated by other circuits, and then the input voltage is input to the amplifier in the feedback branch. The feedback branch determines the generation of the static voltage. The output branch is used to drive the analog-to-digital conversion circuit, and this branch requires high bandwidth and low output impedance. The feedback branch and the output branch are proportional mirrors, and the size of the output voltage of the final buffer circuit can be controlled by controlling the voltage of the feedback branch.

[0004] However, the voltage magnitudes of the two output voltages of the buffer circuit in the related art are limited by the structure. The maximum value of one of the output voltages is the maximum output level of one of the amplifiers minus the VGS of the MOS transistor, and the minimum value of the other output voltage is the minimum output value of the other amplifier plus the VGS of the MOS transistor. The finally calculated output voltage range is small, and for low power supply voltage applications, the small output range of the output voltage is not conducive to the design of a high-performance analog-to-digital conversion circuit. Summary of the Invention

[0005] The present invention provides a reference voltage buffer circuit and device to solve the problem of the small voltage range of the output voltage of the buffer circuit.

[0006] In a first aspect, the present invention provides a reference voltage buffer circuit, which includes a feedback module and an output module. The feedback module includes a first voltage input terminal and a second voltage input terminal, and the output module includes a first voltage output terminal and a second voltage output terminal. It is characterized in that the circuit further includes a first level conversion module and a second level conversion module. Both the first level conversion module and the second level conversion module are connected to the feedback module, and the feedback module is connected to the output module. The first level conversion module is used to perform voltage translation on the first input voltage input by the first voltage input terminal to reduce the minimum voltage value of the first output voltage output by the first voltage output terminal, and the second level conversion module is used to perform voltage translation on the second input voltage input by the second voltage input terminal to increase the maximum voltage value of the second output voltage output by the second voltage output terminal.

[0007] Optionally, the feedback module includes an amplifier A1, an amplifier A2, an NMOS transistor M1a, a PMOS transistor M2a, an NMOS transistor M3a, a resistor R1a, a resistor R2a, a resistor R3a, a capacitor C1a, and a capacitor C2a. The first voltage input terminal is connected to the non-inverting input terminal of the amplifier A1. The inverting input terminal of the amplifier A1 is connected to one end of the resistor R1a. The output terminal of the amplifier A1 is connected to the input terminal of the first level conversion module. The output terminal of the first level conversion module is connected to the gate of the NMOS transistor M1a. The source of the NMOS transistor M1a is connected to the inverting input terminal of the amplifier A1. The drain of the NMOS transistor M1a is externally connected to a power supply voltage. The substrate of the NMOS transistor M1a is connected to one end of the resistor R2a. The other end of the resistor R2a is connected to one end of the capacitor C1a and the output module. The other end of the capacitor C1a is grounded;

[0008] The second voltage input terminal is connected to the non-inverting input terminal of the amplifier A2. The inverting input terminal of the amplifier A2 is connected to the other end of the resistor R1a. The output terminal of the amplifier A2 is connected to the input terminal of the second level conversion module. The output terminal of the second level conversion module is connected to the gate of the PMOS transistor M2a. The source of the PMOS transistor M2a is connected to the inverting input terminal of the amplifier A2. The drain of the PMOS transistor M2a is grounded. The substrate of the PMOS transistor M2a is connected to one end of the resistor R3a. The other end of the resistor R3a is connected to one end of the capacitor C2a and the output module. The other end of the capacitor C2a is grounded;

[0009] The NMOS transistor M3a is connected in parallel across both ends of the resistor R1a. The drain of the NMOS transistor M3a is connected to the inverting input terminal of the amplifier A1. The source of the NMOS transistor M3a is connected to the inverting input terminal of the amplifier A2. The drain and the gate of the NMOS transistor M3a are short-circuited.

[0010] Optionally, the output module includes an NMOS transistor M1b, a PMOS transistor M2b, an NMOS transistor M3b, and a resistor R1b. One end of the resistor R2a is connected to one end of the capacitor C1a and the gate of the NMOS transistor M1b. The drain of the NMOS transistor M1b is externally connected to a power supply voltage. The source of the NMOS transistor M1b is connected to one end of the resistor R1b. The other end of the resistor R1b is connected to the source of the PMOS transistor M2b. One end of the resistor R3a is connected to one end of the capacitor C2a and the gate of the PMOS transistor M2b. The drain of the PMOS transistor M2b is grounded. The NMOS transistor M3b is connected in parallel across both ends of the resistor R1b. The drain of the NMOS transistor M3b is connected to the source of the NMOS transistor M1b and a first voltage output terminal. The source of the NMOS transistor M3b is connected to the source of the PMOS transistor M2b and a second voltage output terminal. The drain and the gate of the NMOS transistor M3b are short-circuited.

[0011] Optionally, the first level conversion module includes a high-voltage boost unit, a first filtering unit, and a first level conversion unit. The first level conversion unit is connected to the feedback module. The first filtering unit is connected to the first level conversion unit. The high-voltage boost unit is connected to the first filtering unit and the clock circuit;

[0012] The second level conversion module includes a negative-voltage boost unit, a second filtering unit, and a second level conversion unit. The second level conversion unit is connected to the feedback module. The second filtering unit is connected to the second level conversion unit. The negative-voltage boost unit is connected to the second filtering unit and the clock circuit.

[0013] Optionally, the clock circuit includes a CKP output terminal and a CKN output terminal. The high-voltage boost unit includes capacitors C1, C2, C3, C4, PMOS transistor M1, NMOS transistors M2, M3, M4, M5, and PMOS transistor M6. The CKP output terminal is connected to one end of capacitor C1. The other end of capacitor C1 is connected to the drain of PMOS transistor M1 and the source of NMOS transistor M2. The gate of PMOS transistor M1 is connected to the substrate of NMOS transistor M2. The gate of NMOS transistor M2 is connected to the source of NMOS transistor M3 and one end of capacitor C2. The other end of capacitor C2 is connected to the CKN output terminal;

[0014] The source of NMOS transistor M3 is further connected to the gate of NMOS transistor M4. The gate of NMOS transistor M3 is connected to the source of NMOS transistor M4. The source of NMOS transistor M4 is further connected to one end of capacitor C3 and the gate of NMOS transistor M5. The other end of capacitor C3 is connected to the CKP output terminal. The source of NMOS transistor M5 is connected to one end of capacitor C4 and the drain of PMOS transistor M6. The other end of capacitor C4 is connected to the CKN output terminal. The sources of PMOS transistor M1 and PMOS transistor M6 are both connected to the first filtering unit. The drains of NMOS transistor M2, NMOS transistor M3, NMOS transistor M4, and NMOS transistor M5 are all externally connected to a power supply voltage.

[0015] Optionally, the first level conversion unit includes PMOS transistors M7, M8, NMOS transistors M9, and M10. The sources of PMOS transistor M7 and PMOS transistor M8 are both connected to the first filtering unit. The gates of PMOS transistor M7 and PMOS transistor M8 are connected. The gate and drain of PMOS transistor M7 are short-circuited. The drain of PMOS transistor M8 is connected to the drain of NMOS transistor M9 and voltage output terminal Vo. The gate and drain of NMOS transistor M9 are short-circuited. The source of NMOS transistor M9 is connected to the drain of NMOS transistor M10. The gate of NMOS transistor M10 is connected to voltage input terminal Vi. The source of NMOS transistor M10 is externally connected to a power supply voltage.

[0016] Optionally, the clock circuit includes a CKP output terminal and a CKN output terminal. The negative voltage boost unit includes a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, an NMOS transistor M11, a PMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M15, and an NMOS transistor M16. The CKP output terminal is connected to one end of the capacitor C7. The other end of the capacitor C7 is connected to the drain of the NMOS transistor M11 and the source of the PMOS transistor M12. The gate of the NMOS transistor M11 is connected to the substrate of the PMOS transistor M12. The gate of the PMOS transistor M12 is connected to the source of the PMOS transistor M13 and one end of the capacitor C8. The other end of the capacitor C8 is connected to the CKN output terminal;

[0017] The source of the PMOS transistor M13 is further connected to the gate of the PMOS transistor M14. The gate of the PMOS transistor M13 is connected to the source of the PMOS transistor M14. The source of the PMOS transistor M14 is further connected to one end of the capacitor C9 and the gate of the PMOS transistor M15. The other end of the capacitor C9 is connected to the CKP output terminal. The source of the PMOS transistor M15 is connected to one end of the capacitor C10 and the drain of the NMOS transistor M16. The other end of the capacitor C10 is connected to the CKN output terminal. The sources of the NMOS transistor M11 and the NMOS transistor M16 are both connected to the second filtering unit. The drains of the PMOS transistor M12, the PMOS transistor M13, the PMOS transistor M14, and the PMOS transistor M15 are all grounded.

[0018] Optionally, the second level conversion unit includes an NMOS transistor M17, an NMOS transistor M18, a PMOS transistor M19, and a PMOS transistor M20. The sources of the NMOS transistor M17 and the NMOS transistor M18 are both connected to the second filtering unit. The gates of the NMOS transistor M17 and the NMOS transistor M18 are connected. The gate and the drain of the NMOS transistor M17 are short-circuited. The drain of the NMOS transistor M18 is connected to the source of the PMOS transistor M19 and the voltage output terminal Vo. The drain and the gate of the PMOS transistor M19 are short-circuited. The drain of the PMOS transistor M19 is connected to the source of the PMOS transistor M20. The gate of the PMOS transistor M20 is connected to the voltage input terminal Vi. The drain of the PMOS transistor M20 is externally connected to a power supply voltage.

[0019] Optionally, the first filtering unit and the second filtering unit are the same filtering unit, and the filtering unit includes a capacitor C0a, a capacitor C0b and a resistor R0, one end of the resistor R0 is connected to one end of the capacitor C0a and the boost unit, the other end of the capacitor C0a is grounded, the other end of the resistor R0 is connected to one end of the capacitor C0b and the level conversion unit, and the other end of the capacitor C0b is grounded.

[0020] In a second aspect, the present invention provides a device, comprising a reference voltage buffer circuit as described in the first aspect.

[0021] The beneficial effects of the present invention are as follows: the circuit of the present invention includes a feedback module and an output module, the feedback module includes a first voltage input terminal and a second voltage input terminal, and the output module includes a first voltage output terminal and a second voltage output terminal. It is characterized in that the circuit also includes a first level conversion module and a second level conversion module, the first level conversion module and the second level conversion module are both connected to the feedback module, and the feedback module is connected to the output module. The first level conversion module is used to perform voltage shifting on the first input voltage input by the first voltage input terminal, so that the first input voltage is converted to output a negative voltage after passing through the amplifier, so as to release the voltage limit of the first output voltage, thereby reducing the minimum voltage value of the first output voltage output by the first voltage output terminal, and the second level conversion module is used to perform voltage shifting on the second input voltage input by the second voltage input terminal, so as to increase the maximum voltage value of the second output voltage output by the second voltage output terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 FIG. 4 is a circuit diagram of a reference voltage buffer circuit according to one embodiment of the present invention.

[0023] Figure 2 FIG. 1 is a circuit diagram of a first level conversion module in one embodiment of the present invention.

[0024] Figure 3 FIG. 4 is a circuit diagram of a second level conversion module in one embodiment of the present invention.

[0025] Description of reference numerals:

[0026] 1. Feedback module; 2. Output module; 3. First level conversion module; 4. Second level conversion module; 31. High-voltage boost unit; 32. First filtering unit; 33. First level conversion unit; 41. Negative-voltage boost unit; 42. Second filtering unit; 43. Second level conversion unit. DETAILED DESCRIPTION

[0027] The present invention discloses a reference voltage buffer circuit.

[0028] In one embodiment of the present invention, referring to Figure 1 , the circuit includes a feedback module and an output module. The feedback module includes a first voltage input terminal and a second voltage input terminal. The output module includes a first voltage output terminal and a second voltage output terminal. The circuit further includes a first level conversion module and a second level conversion module. Both the first level conversion module and the second level conversion module are connected to the feedback module, and the feedback module is connected to the output module.

[0029] Among them, in this embodiment, the first level conversion module includes a high-voltage boost unit, a first filtering unit, and a first level conversion unit. The second level conversion module includes a negative-voltage boost unit, a second filtering unit, and a second level conversion unit. The high-voltage boost unit is connected to the first filtering unit, the first filtering unit is connected to the first level conversion unit, and the first level conversion unit is connected to the feedback module. The negative-voltage boost unit is connected to the second filtering unit, the second filtering unit is connected to the second level conversion unit, and the second level conversion unit is also connected to the feedback module.

[0030] In this embodiment, the feedback module includes an amplifier A1, an amplifier A2, an NMOS transistor M1a, a PMOS transistor M2a, an NMOS transistor M3a, a resistor R1a, a resistor R2a, a resistor R3a, a capacitor C1a, and a capacitor C2a. The first voltage input terminal is connected to the positive-phase input terminal of the amplifier A1. The first voltage input terminal is used to receive an input voltage generated by other external circuits. The inverting input terminal of the amplifier A1 is connected to one end of the resistor R1a. The output terminal of the amplifier A1 is connected to the input terminal of the first level conversion module. The output terminal of the first level conversion module is connected to the gate of the NMOS transistor M1a. The source of the NMOS transistor M1a is connected to the inverting input terminal of the amplifier A1. The drain of the NMOS transistor M1a is externally connected to a power supply voltage. The substrate of the NMOS transistor M1a is connected to one end of the resistor R2a. The other end of the resistor R2a is connected to one end of the capacitor C1a and the output module. The other end of the capacitor C1a is grounded.

[0031] The second voltage input terminal is connected to the non-inverting input terminal of amplifier A2. The second voltage input terminal is used to receive the input voltage generated by other external circuits. The inverting input terminal of amplifier A2 is connected to the other end of resistor R1a. The output terminal of amplifier A2 is connected to the input terminal of the second level conversion module. The output terminal of the second level conversion module is connected to the gate of PMOS transistor M2a. The source of PMOS transistor M2a is connected to the inverting input terminal of amplifier A2. The drain of PMOS transistor M2a is grounded. The substrate of PMOS transistor M2a is connected to one end of resistor R3a. The other end of resistor R3a is connected to one end of capacitor C2a and the output module. The other end of capacitor C2a is grounded. NMOS transistor M3a is connected in parallel across resistor R1a. The drain of NMOS transistor M3a is connected to the inverting input terminal of amplifier A1. The source of NMOS transistor M3a is connected to the inverting input terminal of amplifier A2. The drain and gate of NMOS transistor M3a are short-circuited.

[0032] The output module includes NMOS transistor M1b, PMOS transistor M2b, NMOS transistor M3b and resistor R1b. One end of resistor R2a is connected to one end of capacitor C1a and the gate of NMOS transistor M1b. The drain of NMOS transistor M1b is externally connected to a power supply voltage. The source of NMOS transistor M1b is connected to one end of resistor R1b. The other end of resistor R1b is connected to the source of PMOS transistor M2b. One end of resistor R3a is connected to one end of capacitor C2a and the gate of PMOS transistor M2b. The drain of PMOS transistor M2b is grounded. NMOS transistor M3b is connected in parallel across resistor R1b. The drain of NMOS transistor M3b is connected to the source of NMOS transistor M1b and the first voltage output terminal. The source of NMOS transistor M3b is connected to the source of PMOS transistor M2b and the second voltage output terminal. The drain and gate of NMOS transistor M3b are short-circuited. The first voltage output terminal outputs the first output voltage Vreft, and the second voltage output terminal outputs the second output voltage Vrefb.

[0033] Refer to Figure 1 , a high voltage higher than the power supply voltage can be generated by the high-voltage Boost unit. This voltage is filtered by the first filtering unit and then output to the first level conversion unit. The first level conversion unit shifts the voltage level of the output voltage of amplifier A1 based on the filtered voltage, so that the highest voltage of the first output voltage Vreft is increased from VDD - VGS + VDS to VDD - VDS.

[0034] Similarly, a voltage lower than the low level can be generated by the negative voltage Boost unit. After being filtered by the second filtering unit, the voltage is output to the second level conversion unit. The second level conversion unit shifts the output voltage of the amplifier A2, converting the output voltage of the amplifier A2 into a negative voltage, thereby removing the minimum voltage limit of the second output voltage Vrefb. The minimum voltage changes from VGS + VDS to Vds, where VGS is the gate-source voltage of the PMOS transistor M2a, approximately 0.5V, VDS is the minimum voltage value output by the amplifier A2, approximately 0.2V, and Vds refers to the drain-source voltage of the PMOS transistor M2a. Vds needs to be greater than 0.2V to keep the PMOS transistor M2a in the saturation region. Therefore, the second output voltage is the minimum voltage to ensure that the PMOS transistors M2a and M2b are in the saturation region, ultimately increasing the voltage range of the circuit output voltage by 2VGS.

[0035] In one implementation of the present invention, referring to Figure 2 , the first level conversion module includes a high-voltage boost unit, a first filtering unit, and a first level conversion unit. The first level conversion unit is connected to the feedback module, the first filtering unit is connected to the first level conversion unit, and the high-voltage boost unit is connected to the first filtering unit and the clock circuit.

[0036] In this implementation, the clock circuit includes a CKP output terminal and a CKN output terminal. The high-voltage boost unit includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a PMOS transistor M1, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, and a PMOS transistor M6. The CKP output terminal is connected to one end of the capacitor C1. The other end of the capacitor C1 is connected to the drain of the PMOS transistor M1 and the source of the NMOS transistor M2. The gate of the PMOS transistor M1 is connected to the substrate of the NMOS transistor M2. The gate of the NMOS transistor M2 is connected to the source of the NMOS transistor M3 and one end of the capacitor C2. The other end of the capacitor C2 is connected to the CKN output terminal.

[0037] The source of the NMOS transistor M3 is also connected to the gate of the NMOS transistor M4. The gate of the NMOS transistor M3 is connected to the source of the NMOS transistor M4. The source of the NMOS transistor M4 is also connected to one end of the capacitor C3 and the gate of the NMOS transistor M5. The other end of the capacitor C3 is connected to the CKP output terminal. The source of the NMOS transistor M5 is connected to one end of the capacitor C4 and the drain of the PMOS transistor M6. The other end of the capacitor C4 is connected to the CKN output terminal. The sources of the PMOS transistor M1 and the PMOS transistor M6 are both connected to the first filtering unit. The drains of the NMOS transistor M2, the NMOS transistor M3, the NMOS transistor M4, and the NMOS transistor M5 are all externally connected to a power supply voltage.

[0038] The first level conversion unit includes PMOS transistor M7, PMOS transistor M8, NMOS transistor M9, and NMOS transistor M10. The sources of PMOS transistor M7 and PMOS transistor M8 are both connected to the first filtering unit. The gates of PMOS transistor M7 and PMOS transistor M8 are connected. The gate and drain of PMOS transistor M7 are shorted. The drain of PMOS transistor M8 is connected to the drain of NMOS transistor M9 and the voltage output terminal Vo. The drain and gate of NMOS transistor M9 are shorted. The source of NMOS transistor M9 is connected to the drain of NMOS transistor M10. The gate of NMOS transistor M10 is connected to the voltage input terminal Vi. The source of NMOS transistor M10 is externally connected to a power supply voltage.

[0039] The first filtering unit and the second filtering unit are the same filtering unit. In this embodiment, the "first" in the first filtering unit and the "second" in the second filtering unit are only used for name distinction and do not have any other meanings. The filtering unit includes capacitor C0a, capacitor C0b, and resistor R0. One end of resistor R0 is connected to one end of capacitor C0a and the boost unit. The other end of capacitor C0a is grounded. The boost unit in this embodiment refers to a high-voltage boost unit. Therefore, one end of resistor R0 is connected to one end of capacitor C0a, the source of PMOS transistor M1, and the source of PMOS transistor M6. The other end of resistor R0 is connected to one end of capacitor C0b and the level conversion unit. The other end of capacitor C0b is grounded. The level conversion unit in this embodiment refers to the first level conversion unit. Therefore, the other end of resistor R0 is connected to one end of capacitor C0b, the source of PMOS transistor M7, and the source of PMOS transistor M8.

[0040] In this embodiment, the voltage input terminal Vi in the first level conversion unit is connected to the output terminal of amplifier A1. A high-voltage Vbst is obtained through the high-voltage boost unit. Assuming the power supply voltage VDD is 1.8V and VDS is 0.3V, then Figure 1 the maximum value of Vreft_m is: VDD - VDS. When the power supply voltage VDD is 1.8V, Vreft_m is 1.5V. Since there will be clock signal-related glitches in the high-voltage output by the high-voltage boost unit, part of the glitches can be filtered out by the low-pass filter composed of resistor R0, capacitor C0a, and capacitor C0b in the filtering unit, and a Vbst_rc voltage is generated. Finally, the voltage output from the voltage output terminal V0 of the second level conversion unit is 1.5V - 0.3V = 1.2V. Under the condition of a low power supply voltage, the output range can also be guaranteed. For a higher power supply voltage, the designed value of VDS can be reduced, thereby further increasing the voltage range of the circuit output voltage.

[0041] In one embodiment of the present invention, referring to Figure 3 , the second level conversion module includes a negative voltage boost unit, a second filtering unit, and a second level conversion unit. The second level conversion unit is connected to the feedback module, the second filtering unit is connected to the second level conversion unit, and the negative voltage boost unit is connected to the second filtering unit and the clock circuit.

[0042] The clock circuit includes a CKP output terminal and a CKN output terminal. The negative voltage boost unit includes a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, an NMOS transistor M11, a PMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M15, and an NMOS transistor M16. The CKP output terminal is connected to one end of the capacitor C7. The other end of the capacitor C7 is connected to the drain of the NMOS transistor M11 and the source of the PMOS transistor M12. The gate of the NMOS transistor M11 is connected to the substrate of the PMOS transistor M12. The gate of the PMOS transistor M12 is connected to the source of the PMOS transistor M13 and one end of the capacitor C8. The other end of the capacitor C8 is connected to the CKN output terminal.

[0043] The source of the PMOS transistor M13 is further connected to the gate of the PMOS transistor M14. The gate of the PMOS transistor M13 is connected to the source of the PMOS transistor M14. The source of the PMOS transistor M14 is further connected to one end of the capacitor C9 and the gate of the PMOS transistor M15. The other end of the capacitor C9 is connected to the CKP output terminal. The source of the PMOS transistor M15 is connected to one end of the capacitor C10 and the drain of the NMOS transistor M16. The other end of the capacitor C10 is connected to the CKN output terminal. The sources of the NMOS transistor M11 and the NMOS transistor M16 are both connected to the second filtering unit. The drains of the PMOS transistor M12, the PMOS transistor M13, the PMOS transistor M14, and the PMOS transistor M15 are all grounded.

[0044] The second level conversion unit includes an NMOS transistor M17, an NMOS transistor M18, a PMOS transistor M19, and a PMOS transistor M20. The sources of the NMOS transistor M17 and the NMOS transistor M18 are both connected to the second filtering unit. The gates of the NMOS transistor M17 and the NMOS transistor M18 are connected. The gate of the NMOS transistor M17 is shorted to the drain. The drain of the NMOS transistor M18 is connected to the source of the PMOS transistor M19 and the voltage output terminal Vo. The drain of the PMOS transistor M19 is shorted to the gate. The drain of the PMOS transistor M19 is connected to the source of the PMOS transistor M20. The gate of the PMOS transistor M20 is connected to the voltage input terminal Vi. The drain of the PMOS transistor M20 is externally connected to a power supply voltage.

[0045] The first filtering unit and the second filtering unit are the same filtering unit. In this embodiment, the "first" in the first filtering unit and the "second" in the second filtering unit are only used for name distinction and do not have any other meanings. The filtering unit includes a capacitor C0a, a capacitor C0b, and a resistor R0. One end of the resistor R0 is connected to one end of the capacitor C0a and the boost unit. The other end of the capacitor C0a is grounded. The boost unit in this embodiment refers to a negative voltage boost unit. Therefore, one end of the resistor R0 is connected to one end of the capacitor C0a, the source of the NMOS transistor M11, and the source of the NMOS transistor M16. The other end of the resistor R0 is connected to one end of the capacitor C0b and the level conversion unit. The other end of the capacitor C0b is grounded. The level conversion unit in this embodiment refers to the second level conversion unit. Therefore, the other end of the resistor R0 is connected to one end of the capacitor C0b, the source of the NMOS transistor M17, and the source of the NMOS transistor M18.

[0046] In this embodiment, a negative voltage Vneg is obtained through the negative voltage boost unit, and the negative voltage Vneg is -VDD. When the CKP output terminal of the clock circuit outputs a high level and the CKN output terminal outputs a low level, the voltage of the V5 node is 0V, and the voltage of the V6 node is -VDD. At this time, the NMOS transistor M11 is turned off, and the PMOS transistor M12 is turned on. When the CKP output terminal of the clock circuit outputs a low level and the CKN output terminal outputs a high level, the voltage of the V5 node is -VDD, and the voltage of the V6 node is 0. At this time, the PMOS transistor M12 is turned off, and the NMOS transistor M11 is turned on and conducts. Therefore, the negative voltage Vneg is -VDD. Similarly, the working principles of the PMOS transistor M14, the PMOS transistor M15, and the NMOS transistor M16 are the same, but they are complementary to the working states of the NMOS transistor M11, the PMOS transistor M12, and the PMOS transistor M13, so that the negative voltage boost unit can keep Vneg negative throughout the clock cycle of the clock circuit.

[0047] Since there will be glitches related to the clock signal in the negative voltage output by the negative voltage boost unit, a part of the glitches can be filtered out by the low-pass filter composed of resistor R0, capacitor C0a, and capacitor C0b in the filter unit, and the Vneg_rc voltage is generated. The voltage input terminal Vi in the second level conversion unit is connected to the output terminal of amplifier A2. The minimum voltage output by the output terminal of amplifier A2 is VDS, which is about 0.3V. The second level conversion unit reduces the output voltage of amplifier A1 by 2*VGS. Therefore, the voltage magnitude output by the voltage output terminal Vo of the second level conversion unit is approximately: 0.3V - 2*0.7V = -1.1V. However, the voltage magnitude output by the second level conversion unit is limited by NMOS transistor M18. To ensure the normal operation of NMOS transistor M18, the minimum voltage output by the second level conversion unit is Vneg_rc + VDS, which is about -0.6V. That is, the minimum voltage after level translation is -0.6V, so that Figure 1 the minimum value of the Vrefb_m voltage is not limited by the gate voltage of PMOS transistor M2a.

[0048] The present invention also discloses a device, which includes Figures 1 to 3 the circuit shown. In the shown circuit, a feedback module and an output module are included. The feedback module includes a first voltage input terminal and a second voltage input terminal. The output module includes a first voltage output terminal and a second voltage output terminal. It is characterized in that the circuit further includes a first level conversion module and a second level conversion module. Both the first level conversion module and the second level conversion module are connected to the feedback module. The feedback module is connected to the output module. The first level conversion module is used to perform voltage translation on the first input voltage input to the first voltage input terminal, so that the first input voltage is converted to output a negative voltage after passing through the amplifier, so as to relieve the voltage limitation of the first output voltage, thereby reducing the minimum voltage value of the first output voltage output by the first voltage output terminal. The second level conversion module is used to perform voltage translation on the second input voltage input to the second voltage input terminal, so as to increase the maximum voltage value of the second output voltage output by the second voltage output terminal.

[0049] Those of ordinary skill in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the protection scope of the present application is limited to these examples; under the idea of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of one or more embodiments of the present application as described above. For the sake of brevity, they are not provided in detail.

[0050] One or more embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the present application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of the present application shall be included within the protection scope of the present application.

Claims

1. A reference voltage buffer circuit, the circuit comprising a feedback module and an output module, the feedback module including a first voltage input terminal and a second voltage input terminal, the output module including a first voltage output terminal and a second voltage output terminal, characterized in that, The circuit further includes a first level conversion module and a second level conversion module. Both the first level conversion module and the second level conversion module are connected to the feedback module, and the feedback module is connected to the output module. The first level conversion module is used to perform voltage translation on the first input voltage input by the first voltage input terminal, so as to reduce the minimum voltage value of the first output voltage output by the first voltage output terminal. The second level conversion module is used to perform voltage translation on the second input voltage input by the second voltage input terminal, so as to increase the maximum voltage value of the second output voltage output by the second voltage output terminal; The feedback module includes an amplifier A1, an amplifier A2, an NMOS transistor M1a, a PMOS transistor M2a, an NMOS transistor M3a, a resistor R1a, a resistor R2a, a resistor R3a, a capacitor C1a and a capacitor C2a. The first voltage input terminal is connected to the non-inverting input terminal of the amplifier A1. The inverting input terminal of the amplifier A1 is connected to one end of the resistor R1a. The output terminal of the amplifier A1 is connected to the input terminal of the first level conversion module. The output terminal of the first level conversion module is connected to the gate of the NMOS transistor M1a. The source of the NMOS transistor M1a is connected to the inverting input terminal of the amplifier A1. The drain of the NMOS transistor M1a is externally connected to a power supply voltage. The substrate of the NMOS transistor M1a is connected to one end of the resistor R2a. The other end of the resistor R2a is connected to one end of the capacitor C1a and the output module. The other end of the capacitor C1a is grounded; The second voltage input terminal is connected to the non-inverting input terminal of the amplifier A2. The inverting input terminal of the amplifier A2 is connected to the other end of the resistor R1a. The output terminal of the amplifier A2 is connected to the input terminal of the second level conversion module. The output terminal of the second level conversion module is connected to the gate of the PMOS transistor M2a. The source of the PMOS transistor M2a is connected to the inverting input terminal of the amplifier A2. The drain of the PMOS transistor M2a is grounded. The substrate of the PMOS transistor M2a is connected to one end of the resistor R3a. The other end of the resistor R3a is connected to one end of the capacitor C2a and the output module. The other end of the capacitor C2a is grounded; The NMOS transistor M3a is connected in parallel across the two ends of the resistor R1a. The drain of the NMOS transistor M3a is connected to the inverting input terminal of the amplifier A1. The source of the NMOS transistor M3a is connected to the inverting input terminal of the amplifier A2. The drain and gate of the NMOS transistor M3a are short-circuited.

2. The reference voltage buffer circuit according to claim 1, characterized in that, The output module includes NMOS transistor M1b, PMOS transistor M2b, NMOS transistor M3b, and resistor R1b. One end of resistor R2a is connected to one end of capacitor C1a and the gate of NMOS transistor M1b. The drain of NMOS transistor M1b is externally connected to a power supply voltage. The source of NMOS transistor M1b is connected to one end of resistor R1b. The other end of resistor R1b is connected to the source of PMOS transistor M2b. One end of resistor R3a is connected to one end of capacitor C2a and the gate of PMOS transistor M2b. The drain of PMOS transistor M2b is grounded. NMOS transistor M3b is connected in parallel across both ends of resistor R1b. The drain of NMOS transistor M3b is connected to the source of NMOS transistor M1b and a first voltage output terminal. The source of NMOS transistor M3b is connected to the source of PMOS transistor M2b and a second voltage output terminal. The drain and gate of NMOS transistor M3b are short-circuited.

3. A reference voltage buffer circuit according to claim 1, wherein The first level conversion module includes a high-voltage boost unit, a first filtering unit, and a first level conversion unit. The first level conversion unit is connected to the feedback module. The first filtering unit is connected to the first level conversion unit. The high-voltage boost unit is connected to the first filtering unit and the clock circuit. The second level conversion module includes a negative-voltage boost unit, a second filtering unit, and a second level conversion unit. The second level conversion unit is connected to the feedback module. The second filtering unit is connected to the second level conversion unit. The negative-voltage boost unit is connected to the second filtering unit and the clock circuit.

4. A reference voltage buffer circuit according to claim 3, characterized in that, The clock circuit includes a CKP output terminal and a CKN output terminal. The high-voltage boost unit includes capacitors C1, C2, C3, C4, PMOS transistor M1, NMOS transistors M2, M3, M4, M5, and PMOS transistor M6. The CKP output terminal is connected to one end of capacitor C1. The other end of capacitor C1 is connected to the drain of PMOS transistor M1 and the source of NMOS transistor M2. The gate of PMOS transistor M1 is connected to the substrate of NMOS transistor M2. The gate of NMOS transistor M2 is connected to the source of NMOS transistor M3 and one end of capacitor C2. The other end of capacitor C2 is connected to the CKN output terminal. The source of the NMOS transistor M3 is also connected to the gate of the NMOS transistor M4, the gate of the NMOS transistor M3 is connected to the source of the NMOS transistor M4, the source of the NMOS transistor M4 is also connected to one end of the capacitor C3 and the gate of the NMOS transistor M5, the other end of the capacitor C3 is connected to the CKP output terminal, the source of the NMOS transistor M5 is connected to one end of the capacitor C4 and the drain of the PMOS transistor M6, the other end of the capacitor C4 is connected to the CKN output terminal, the sources of the PMOS transistor M1 and the PMOS transistor M6 are both connected to the first filtering unit, and the drains of the NMOS transistor M2, the NMOS transistor M3, the NMOS transistor M4, and the NMOS transistor M5 are all externally connected to a power supply voltage.

5. A reference voltage buffer circuit according to claim 3, characterized in that, The first level conversion unit includes a PMOS transistor M7, a PMOS transistor M8, an NMOS transistor M9, and an NMOS transistor M10. The sources of the PMOS transistor M7 and the PMOS transistor M8 are both connected to the first filtering unit. The gate of the PMOS transistor M7 is connected to the gate of the PMOS transistor M8. The gate and the drain of the PMOS transistor M7 are short-circuited. The drain of the PMOS transistor M8 is connected to the drain of the NMOS transistor M9 and the voltage output terminal Vo. The drain and the gate of the NMOS transistor M9 are short-circuited. The source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M10. The gate of the NMOS transistor M10 is connected to the voltage input terminal Vi. The source of the NMOS transistor M10 is externally connected to a power supply voltage.

6. The reference voltage buffer circuit according to claim 3, characterized in that, The clock circuit includes a CKP output terminal and a CKN output terminal. The negative voltage boost unit includes a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, an NMOS transistor M11, a PMOS transistor M12, a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M15, and an NMOS transistor M16. The CKP output terminal is connected to one end of the capacitor C7. The other end of the capacitor C7 is connected to the drain of the NMOS transistor M11 and the source of the PMOS transistor M12. The gate of the NMOS transistor M11 is connected to the substrate of the PMOS transistor M12. The gate of the PMOS transistor M12 is connected to the source of the PMOS transistor M13 and one end of the capacitor C8. The other end of the capacitor C8 is connected to the CKN output terminal; The source of the PMOS transistor M13 is also connected to the gate of the PMOS transistor M14, the gate of the PMOS transistor M13 is connected to the source of the PMOS transistor M14, the source of the PMOS transistor M14 is also connected to one end of the capacitor C9 and the gate of the PMOS transistor M15, the other end of the capacitor C9 is connected to the CKP output terminal, the source of the PMOS transistor M15 is connected to one end of the capacitor C10 and the drain of the NMOS transistor M16, the other end of the capacitor C10 is connected to the CKN output terminal, the sources of the NMOS transistor M11 and the NMOS transistor M16 are both connected to the second filtering unit, and the drains of the PMOS transistor M12, the PMOS transistor M13, the PMOS transistor M14, and the PMOS transistor M15 are all grounded.

7. The reference voltage buffer circuit according to claim 3, wherein, The second level conversion unit includes an NMOS transistor M17, an NMOS transistor M18, a PMOS transistor M19, and a PMOS transistor M20. The sources of the NMOS transistor M17 and the NMOS transistor M18 are both connected to the second filtering unit. The gate of the NMOS transistor M17 is connected to the gate of the NMOS transistor M18, and the gate and drain of the NMOS transistor M17 are short-circuited. The drain of the NMOS transistor M18 is connected to the source of the PMOS transistor M19 and the voltage output terminal Vo. The drain and gate of the PMOS transistor M19 are short-circuited. The drain of the PMOS transistor M19 is connected to the source of the PMOS transistor M20. The gate of the PMOS transistor M20 is connected to the voltage input terminal Vi, and the drain of the PMOS transistor M20 is externally connected to a power supply voltage.

8. The reference voltage buffer circuit according to claim 3, wherein The first filtering unit and the second filtering unit are the same filtering unit. The filtering unit includes a capacitor C0a, a capacitor C0b, and a resistor R0. One end of the resistor R0 is connected to one end of the capacitor C0a and the boost unit. The other end of the capacitor C0a is grounded. The other end of the resistor R0 is connected to one end of the capacitor C0b and the level conversion unit. The other end of the capacitor C0b is grounded.

9. An analog-to-digital conversion device, characterized in that, The analog-to-digital conversion device includes a reference voltage buffer circuit according to any one of claims 1 to 8.

Images