Power-down control circuit

Abstract

An embodiment of the present application provides a power-down control circuit. The control circuit includes: a first chip for converting an input voltage signal into a first output voltage signal. When the first enable terminal of the first chip is at a first level, the first output voltage signal is equal to the input voltage signal; when the first enable terminal is at a second level, the voltage of the first output voltage signal is zero; a first voltage division module connected between the input terminal of the first chip and the ground terminal, and the output terminal of the first voltage division module is connected to the first enable terminal, and the first chip is controlled to perform a power-down operation at a first moment through the first enable terminal; a first delay module connected between the first output terminal of the first chip and the first enable terminal, and jointly controls the first chip to perform a power-down operation at a second moment with the first voltage division module, and the second moment is later than the first moment. Through the embodiment of the present application, the technical problem of poor flexibility in power-down control in the related art is solved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic technologies, and more particularly, to a power-down control circuit. Background Art

[0002] Currently, the demand for servers in the market is increasing. When the server is undergoing routine maintenance, the server will lose power. As the control chips such as the Baseboard Management Controller (BMC) inside the current server have relevant timing requirements for the power-down of multiple internal power supplies, some current designs can no longer meet these newly added requirements. For example, Figure 1 is a schematic diagram of the power-on and power-off timing of the 12V on the main board in the related art. P12V_Input is the output voltage of the Power Supply Unit (PSU). P12V_Input is converted by an electrical fuse (Efuse, also known as an electronic fuse or electronic fuse) to output the 12V power used by the main board. The power-on of the 12V power generally uses the voltage division of P12V_Input or the PSU_PG signal (the indication signal of the PSU) as the Enable of the Efuse. For these two different power-on and power-off methods, generally, when the 12V_Input voltage rises to 90%, the 12V power on the main board is turned on, and when the 12V_Input power drops to 90%, the Efuse of the 12V on the main board is turned off. The control scheme adopted in the related art has uncontrollable factors when the server shuts down and loses power. For example, when powering on, in order to ensure that the output voltage P12V_Input of the PSU is fully powered on before the 12V voltage on the main board starts to power on, generally, the 12V power is started when P12V_Input is powered on to more than 90%. This also leads to when losing power, when the P12V_Input power drops to 90%, the Efuse of the 12V starts to turn off. After the 12V power is turned off, there is no input for other powers on the main board, and they will also be immediately turned off. The main board cannot achieve sequential power-down or delayed power-down control. It can be seen that the flexibility of power-down control in the related art is poor. Therefore, it is particularly necessary to provide a circuit for delayed power-down.

[0003] Aiming at the technical problem of poor flexibility in power-down control existing in the related art, no effective solution has been proposed yet. Summary of the Invention

[0004] The embodiments of the present application provide a power-down control circuit to at least solve the technical problem of poor flexibility in power-down control existing in the related art.

[0005] According to an embodiment of the present application, a power-down control circuit is provided, including: a first chip for converting an input voltage signal into a first output voltage signal, wherein when the first enable terminal of the first chip is at a first level value, the first output voltage signal is equal to the input voltage signal, and when the first enable terminal of the first chip is at a second level value, the voltage value of the first output voltage signal is zero; a first voltage dividing module connected between the input terminal of the first chip and the ground terminal, and the output terminal of the first voltage dividing module is connected to the first enable terminal of the first chip, and the first voltage dividing module is used to control the first chip to perform a power-down operation at a first moment through the first enable terminal; a first delay module connected between the first output terminal of the first chip and the first enable terminal, wherein the first voltage dividing module is further used to jointly control the first chip to perform a power-down operation at a second moment through the first enable terminal and the first delay module, and the second moment is later than the first moment.

[0006] In an exemplary embodiment, the first delay module includes: a first resistor connected between the first output terminal and the first enable terminal, wherein the first output terminal is used to output the first output voltage signal; or, a first resistor and a first diode, wherein the positive electrode of the first diode is connected to the first output terminal, the negative electrode of the first diode is connected to the first enable terminal through the first resistor, and the first output terminal is used to output the first output voltage signal.

[0007] In an exemplary embodiment, when the resistance value of the first resistor is equal to a first target resistance value and the input voltage signal drops from a first normal voltage value to a first predetermined voltage value, the first voltage dividing module and the first delay module jointly control the first chip to perform a power-down operation at a second moment through the first enable terminal, wherein the first predetermined voltage value is a first predetermined ratio of the first normal voltage value, and the input voltage signal drops to the first predetermined voltage value at the second moment.

[0008] In an exemplary embodiment, it further includes: a second diode, wherein the positive electrode of the second diode is connected to the first input terminal of the first chip, the negative electrode of the second diode is connected to the first end of the first voltage dividing module, the second end of the first voltage dividing module is connected to the ground terminal, and the first input terminal is used to input the input voltage signal; wherein when the input voltage signal is in the power-down period, the first voltage dividing module and the first delay module jointly control the first chip to perform a power-down operation at a second moment through the first enable terminal, and the power-down period represents the process in which the input voltage signal drops from a normal voltage value to zero, and the power-down period includes the second moment.

[0009] In an exemplary embodiment, the first voltage dividing module includes: a second resistor, wherein the first end of the second resistor is connected to the negative electrode of the second diode; a third resistor, wherein the first end of the third resistor is connected to the second end of the second resistor, the second end of the third resistor is connected to the ground terminal, and the first end of the third resistor is connected to the first enable terminal.

[0010] In an exemplary embodiment, it further includes: a second chip, wherein a second input end of the second chip is connected to a first output end of the first chip, and the second chip is configured to convert a first output voltage signal into a second output voltage signal; a second voltage dividing module, connected between the second input end and the ground end, and an output end of the second voltage dividing module is connected to a second enable end of the second chip, and the second voltage dividing module is configured to control the second chip to perform a power-off operation at a third moment through the second enable end.

[0011] In an exemplary embodiment, it further includes: a second delay module, connected between the second input end and the ground end, and an output end of the second delay module is connected to the second enable end, and a control end of the second delay module is connected to a second output end of the second chip, wherein the second output end of the second chip is configured to output a target indication signal of the second chip, and the target indication signal is configured to indicate whether the second chip has completed a power-on operation, and the second voltage dividing module is further configured to jointly control the second chip to perform a power-off operation at a fourth moment through the second enable end with the second delay module, and the fourth moment is later than the third moment.

[0012] In an exemplary embodiment, the second delay module includes: a first MOS transistor, wherein a gate of the first MOS transistor is connected to the second output end of the second chip, and a source of the first MOS transistor is connected to the ground end; a second MOS transistor, wherein a gate of the second MOS transistor is connected to a drain of the first MOS transistor, a drain of the second MOS transistor is connected to the second enable end through a fourth resistor, a source of the second MOS transistor is connected to the second input end, and a gate of the second MOS transistor is connected to the source of the second MOS transistor through a fifth resistor.

[0013] In an exemplary embodiment, when a resistance value of the fourth resistor is equal to a second target resistance value, and the first output voltage signal drops from a second normal voltage value to a second predetermined voltage value, the second voltage dividing module and the second delay module jointly control the second chip to perform a power-off operation at the fourth moment through the second enable end, wherein the second predetermined voltage value is a second predetermined ratio of the second normal voltage value, and the input voltage signal drops to the second predetermined voltage value at the fourth moment.

[0014] In an exemplary embodiment, the second voltage dividing module includes: a sixth resistor, wherein a first end of the sixth resistor is connected to the second input end; a seventh resistor, wherein a first end of the seventh resistor is connected to a second end of the sixth resistor, a second end of the seventh resistor is connected to the ground end, and the first end of the seventh resistor is connected to the second enable end.

[0015] According to the embodiments of the present application, the output terminal of the first voltage dividing module is connected to the first enable terminal of the first chip to control the first chip to perform a power-down operation at a first moment. The first delay module is connected between the first output terminal and the first enable terminal of the first chip. The first chip is controlled to perform a power-down operation at a second moment through the cooperation of the first voltage dividing module and the first delay module, where the second moment is later than the first moment. The purpose of delaying the power-down operation of the first chip through the first delay module is achieved, avoiding the problem in the related art that the first chip on the main board cannot be delayed in power-down. Therefore, the technical problem of poor flexibility in power-down control existing in the related art can be solved, and the effect of improving the flexibility of power-down control is achieved. Description of the Drawings

[0016] Figure 1 is a schematic diagram of the power-on and power-off timing of the 12V on the main board in the related art;

[0017] Figure 2 is a hardware structure block diagram of a server with a power-down control circuit according to an embodiment of the present application;

[0018] Figure 3 is a schematic diagram of the power-on and power-off timing of the 3.3V on the main board in the related art;

[0019] Figure 4 is a framework diagram of a power-down control circuit according to an embodiment of the present application;

[0020] Figure 5 is an improved schematic diagram of the power-on and power-off timing of 12V according to an embodiment of the present application;

[0021] Figure 6 is an improved schematic diagram of the power-on and power-off timing of 3.3V according to an embodiment of the present application;

[0022] Figure 7 is a schematic diagram of the timing control circuit of the 12V Efuse according to an embodiment of the present application;

[0023] Figure 8 is a schematic diagram of the 3.3V power supply timing control circuit according to an embodiment of the present application. Detailed Embodiments

[0024] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0025] It should be noted that the terms "first", "second", etc. in the specification, claims and above-mentioned drawings of this application are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of this application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0026] The power-off control circuit embodiments provided in the embodiments of this application can be executed in a server, a mobile terminal, a computer terminal or a similar computing device. Taking running on a server as an example, Figure 2 is the hardware structure block diagram of the server of the power-off control circuit in the embodiments of this application. As Figure 2 shown, the server may include one or more ( Figure 2 only one is shown in the figure) processors 202 (the processor 202 may include, but is not limited to, processing devices such as a microprocessor MCU or a programmable logic device FPGA) and a memory 204 for storing data. Among them, the above-mentioned server may further include a transmission device 206 for communication functions and an input / output device 208. Those of ordinary skill in the art can understand that Figure 2 the structure shown is only schematic and does not limit the structure of the above-mentioned server. For example, the server may further include more or fewer components than Figure 2 shown in the figure, or have a different configuration from Figure 2 shown in the figure.

[0027] The memory 204 can be used to store computer programs, for example, software programs and modules of application software. The processor 202 executes various functional applications and data processing by running the computer programs stored in the memory 204, that is, implements the above-mentioned method. The memory 204 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some instances, the memory 204 may further include a memory remotely disposed relative to the processor 202, and these remote memories can be connected to the server through a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0028] The transmission device 206 is used to receive or send data via a network. Specific examples of the above network may include a wireless network provided by the communication provider of the server. In one example, the transmission device 206 includes a network adapter (Network Interface Controller, abbreviated as NIC), which can be connected to other network devices through a base station and thus communicate with the Internet. In one example, the transmission device 206 can be a Radio Frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0029] Figure 3 is a schematic diagram of the power-on and power-off timing of the 3.3V on the main board in the related art. The 3.3V power supply of the main board is generally obtained by converting the 12V power supply using a Buck power supply module. The Enable control circuits for the power-on and power-off of the 3.3V power supply generally use the same two methods as the 12V power supply. When the 12V power supply is powered on to 90%, P3V3 (i.e., the 3.3V power supply) starts to be powered on. When the 12V power supply drops to 90%, the power supply of P3V3 starts to be turned off. The control scheme adopted in the related art also has uncontrollable factors when the server shuts down and loses power. For example, P3V3 is the first group of converted power supplies on the main board, and the Enable signal cannot be controlled by a Complex Programmable Logic Device (CPLD) (the power supply of the CPLD is P3V3). Generally, the 12V power supply (such as Figure 3 P12V in Figure 3 is used for voltage division to make Enable, or the PG signal of Efuse (such as

[0030] P12V_PG in Figure 4 is used directly to make Enable in two ways. When shutting down, when the 12V power supply drops to 90%, the P3V3 power supply is turned off, and the P3V3 on the main board loses power very early, and the CPLD cannot normally control other power supplies to lose power according to the timing requirements. In view of the above problems in the related art, the embodiment of the present application proposes an improved power-off control scheme. Figure 4 as shown, includes:

[0031] A first chip, configured to convert an input voltage signal into a first output voltage signal. Wherein, when the first enable terminal of the first chip is at a first level value, the first output voltage signal is equal to the input voltage signal; when the first enable terminal of the first chip is at a second level value, the voltage value of the first output voltage signal is zero;

[0032] The first voltage dividing module is connected between the input end and the ground end of the first chip. The output end of the first voltage dividing module is connected to the first enabling end of the first chip. The first voltage dividing module is used to control the first chip to perform a power-off operation at a first moment through the first enabling end.

[0033] The first delay module is connected between the first output end and the first enabling end of the first chip. Wherein, the first voltage dividing module is further used to jointly control the first chip to perform a power-off operation at a second moment through the first enabling end and the first delay module, and the second moment is later than the first moment.

[0034] Through the embodiments of the present application, the output end of the first voltage dividing module is connected to the first enabling end of the first chip to control the first chip to perform a power-off operation at a first moment, while the first delay module is connected between the first output end and the first enabling end of the first chip, and the first chip is jointly controlled by the first voltage dividing module and the first delay module to perform a power-off operation at a second moment, where the second moment is later than the first moment. The purpose of delaying the power-off operation of the first chip through the first delay module is achieved, and the problem that the first chip on the main board cannot be delayed in power-off in the related art is avoided. Therefore, the technical problem of poor flexibility in power-off control in the related art can be solved, and the effect of improving the flexibility of power-off control is achieved.

[0035] In the above embodiment, the first chip may be an electronic fuse Efuse (or referred to as an electronic fuse or an electronic fuse), taking a common power supply unit PSU in a server as an example, the above input voltage signal is the output voltage of the PSU (such as P12V_Input), and the above first output voltage signal is the P12V power supply used by the main board, that is, the first chip is used to convert the input voltage signal (P12V_Input) into the first output voltage signal (P12V), as Figure 4 shown, when the first enabling end (such as the Enable end) of the first chip is at a first level value (such as a high level or 1), the first output voltage signal is equal to the input voltage signal. Taking the above input voltage signal as P12V_Input as an example, that is, the voltage value during normal operation is 12V, and the first output voltage at this time is 12V. When the first enabling end (such as the Enable end) of the first chip is at a second level value (such as a low level or 0), the first output voltage is equal to 0V, which is equivalent to a power-off, and the power supply voltage used by the main board is 0V at this time; the output voltage of the first chip (such as the above Efuse) (corresponding to the above first output voltage signal) is 12V or 0V, depending on the first enabling end of the first chip; the above electronic fuse Efuse can play a protective role in the circuit, such as overcurrent protection.

[0036] In the above embodiments, the first voltage dividing module is connected between the input terminal (such as the Vin terminal) of the first chip and the ground terminal. Since the above input voltage signal (such as P12V_Input) is input through the access terminal of the first chip, that is, under normal operation or normal power-on, the voltage input to the input terminal of the first chip is 12V. Therefore, the first voltage dividing module is connected between the 12V power supply and the ground terminal. Optionally, the first voltage dividing module can be a voltage dividing circuit composed of two resistors (or more resistors). For example, the resistor R1 and the resistor R2 are connected in series, and the voltage across the resistor R1 (or R2) is used as the output voltage, and this output voltage can be used to control the first enable terminal of the above first chip (such as Efuse). For example, assume that the voltage value of the first enable terminal of the first chip is greater than or equal to 3V (or 1.2V, or other value), that is, when it corresponds to a high level, the first enable terminal is effective and the first chip can work normally. When the voltage value of the first enable terminal of the first chip is less than 3V (or 1.2V, or other value), the first chip cannot work normally, and at this time, the first output terminal of the first chip is 0V. Optionally, in addition to the above two resistors (or more resistors), the first voltage dividing module may further include a diode (such as D1). For example, the diode D1 is connected in series with the resistors R1 and R2, which can also play a role in preventing leakage.

[0037] In the above embodiments, the first delay module is connected between the first output terminal and the first enable terminal of the first chip, as Figure 4 shown. In this way, the first enable terminal of the first chip can be jointly controlled by the first delay module and the above first voltage dividing module. For example, before the first delay module is introduced, the first enable terminal of the first chip is controlled by the first voltage dividing module, and the first chip can be controlled to perform a power-off (or called power-down) operation at the first moment. For example, the first moment corresponds to the moment when the input voltage signal (such as Figure 1 P12V_Input in) drops to 90% of the power supply; in the embodiment of the present application, the first delay module is introduced, and the first enable terminal of the first chip is jointly controlled by the first delay module and the above first voltage dividing module, so that the first chip can perform a power-off operation at the second moment. For example, the second moment corresponds to the moment when the input voltage signal (such as Figure 1 P12V_Input in) drops to 70% (or 50%, or other) of the power supply, so as to achieve the purpose of delayed power-off; the first delay module can be a resistor (such as R3), and the resistance value of the resistor R3 can be designed or selected according to actual needs. Optionally, the first delay module may further include a diode (such as D2). For example, the diode D2 is connected in series with the resistor R3, which can also play a role in preventing leakage.

[0038] In the related art, generally, the 12V power supply on the motherboard is turned on when the 12V_Input voltage rises to 90%, and the Efuse of the 12V on the motherboard is turned off when the 12V_Input power supply drops to 90%. It is impossible to achieve flexible control of power-off. Through the control of the first enable terminal in the embodiments of the present application, the purpose of flexibly controlling the power-off of the first chip (or motherboard) can be achieved. Through the embodiments of the present application, the purpose of delaying the power-off operation of the first chip through the first delay module is achieved, avoiding the problem that the first chip on the motherboard cannot be delayed in power-off in the related art. Therefore, the technical problem of poor flexibility in power-off control existing in the related art can be solved, and the effect of improving the flexibility of power-off control is achieved.

[0039] In an alternative embodiment, the first delay module includes: a first resistor connected between the first output terminal and the first enable terminal, where the first output terminal is used to output the first output voltage signal; or, a first resistor and a first diode, where the positive electrode of the first diode is connected to the first output terminal, and the negative electrode of the first diode is connected to the first enable terminal through the first resistor, and the first output terminal is used to output the first output voltage signal.

[0040] Optionally, the above-mentioned first delay module may only include one resistor, such as the above-mentioned first resistor, which is connected between the first output terminal of the first chip (such as the above-mentioned Efuse) and the first enable terminal. At this time, the input signal (high-level or low-level signal) of the first enable terminal is jointly determined by the first voltage division module and this first resistor; there is no circuit similar to the above-mentioned first delay module in the related art, that is, when the input voltage signal (such as Figure 1 P12V_Input in) drops to 90% when the power supply drops, that is, when it drops from the normal voltage value of 12V to 90% of the normal voltage value, the first enable terminal of the first chip changes from high level to low level. At this time (corresponding to the above-mentioned first moment), the first chip performs a power-off operation. However, in the embodiments of the present application, the introduction of the first delay module, such as the above-mentioned first resistor, can enable the first chip to perform a power-off (or called power-down) operation only when the input voltage signal (such as Figure 1 P12V_Input in) drops to 70% (or 50%, or others) of the power supply, achieving the purpose of flexibly controlling the power-off of the first chip; optionally, the above-mentioned first delay module may also include a resistor (such as the first resistor) and a diode (such as the first diode), and this first diode can play a role in leakage protection.

[0041] In an alternative embodiment, when the resistance value of the first resistor is equal to the first target resistance value and the input voltage signal drops from the first normal voltage value to the first predetermined voltage value, the first voltage dividing module and the first delay module jointly control the first chip to perform a power-down operation at the second moment through the first enabling terminal, where the first predetermined voltage value is a first predetermined ratio of the first normal voltage value, and the input voltage signal drops to the first predetermined voltage value at the second moment.

[0042] Optionally, as can be seen from the foregoing embodiments, by designing or selecting the first resistor, the purpose of delaying the power-down of the first chip can be achieved. For example, the resistance value of the first resistor is equal to the first target resistance value (such as xxΩ / KΩ, or others). When the input voltage signal (such as Figure 1 P12V_Input in) drops from the first normal voltage value (such as 12V) to the first predetermined voltage value (such as 70% of the first normal voltage value, or others), the voltage signal input to the first enabling terminal changes from a high level to a low level, that is, the first chip can be controlled to perform a power-down operation at the moment when the input voltage signal drops to 70%. Optionally, the resistance value of the above-mentioned first resistor can be adjusted according to actual needs. For example, the resistance value of the first resistor is designed as other resistance values. When the input voltage signal (such as Figure 1 P12V_Input in) drops from the first normal voltage value (such as 12V) to other predetermined voltage values (such as 50% of the first normal voltage value, or others), the voltage signal input to the first enabling terminal changes from a high level to a low level, that is, the first chip can be controlled to perform a power-down operation at the moment when the input voltage signal drops to 50%. The power-down operation can also be flexibly controlled by designing the resistance value of the first resistor and the resistance values of the two resistors in the first voltage dividing module to enable the first enabling terminal of the first chip to be turned off at the required voltage threshold (i.e., the voltage threshold for changing from a high level to a low level). Through this embodiment, the purpose of flexibly controlling the power-down operation can be achieved.

[0043] In an alternative embodiment, it further includes: a second diode, where the positive electrode of the second diode is connected to the first input terminal of the first chip, the negative electrode of the second diode is connected to the first end of the first voltage dividing module, the second end of the first voltage dividing module is connected to the ground terminal, and the first input terminal is used for inputting the input voltage signal; where, when the input voltage signal is in the power-down period, the first voltage dividing module and the first delay module jointly control the first chip to perform a power-down operation at the second moment through the first enabling terminal, and the power-down period represents the process in which the input voltage signal drops from the normal voltage value to zero, and the power-down period includes the second moment.

[0044] Optionally, the power-down control circuit described above may further include a second diode, which is connected between the first input terminal of the first chip and the first voltage-dividing module. For example, the positive electrode of the second diode is connected to the first input terminal of the first chip, the negative electrode of the second diode is connected to the first end of the first voltage-dividing module, the second end of the first voltage-dividing module is connected to the ground terminal, and the output terminal of the first voltage-dividing module is connected to the first enable terminal of the first chip. That is, the output voltage-dividing signal of the first voltage-dividing module is used to control the first enable terminal, and the second diode can play a role in preventing leakage.

[0045] In an optional embodiment, the first voltage-dividing module includes: a second resistor, wherein the first end of the second resistor is connected to the negative electrode of the second diode; a third resistor, wherein the first end of the third resistor is connected to the second end of the second resistor, the second end of the third resistor is connected to the ground terminal, and the first end of the third resistor is connected to the first enable terminal.

[0046] Optionally, the first voltage-dividing module may be a voltage-dividing circuit composed of two resistors (or more resistors). For example, resistor R1 (corresponding to the above-mentioned second resistor) and resistor R2 (corresponding to the above-mentioned third resistor) are connected in series, and the voltage across resistor R2 is used as the output voltage, and this output voltage can be used to control the first enable terminal of the above-mentioned first chip (such as Efuse). For example, assuming that the voltage value of the first enable terminal of the first chip is greater than or equal to 3V (or 1.2V, or other value), that is, corresponding to a high level (or 1, corresponding to the aforementioned first level value), the first enable terminal is effective and the first chip can work normally. When the voltage value of the first enable terminal of the first chip is less than 3V (or 1.2V, or other value), that is, corresponding to a low level (or 0, corresponding to the aforementioned second level value), the first enable terminal is invalid and the first chip cannot work normally. At this time, the first output terminal of the first chip is 0V; that is, the voltage across the third resistor in the first voltage-dividing module is used to control the first enable terminal of the first chip.

[0047] In an optional embodiment, it further includes: a second chip, wherein the second input terminal of the second chip is connected to the first output terminal of the first chip, and the second chip is used to convert the first output voltage signal into a second output voltage signal; a second voltage-dividing module, connected between the second input terminal and the ground terminal, and the output terminal of the second voltage-dividing module is connected to the second enable terminal of the second chip. The second voltage-dividing module is used to control the second chip to perform a power-down operation at the third moment through the second enable terminal.

[0048] Optionally, the above-mentioned power-down control circuit may further include a second chip and a second voltage dividing module. The second chip is used to convert the first output voltage signal into a second output voltage signal. For example, the first output voltage signal is the P12V power supply used by the aforementioned main board, and the second output voltage signal may be the 3.3V (or can be called P3V3) power supply of the main board. That is, the second chip can implement the function of converting 12V voltage into 3.3V (or other voltages). For example, the second chip can be a buck power supply module or a voltage regulator (VR) conversion chip; the second voltage dividing module is connected between the second input terminal of the second chip and the ground terminal, and the output terminal of the second voltage dividing module is connected to the second enable terminal of the second chip. That is, the second enable terminal of the second chip is controlled by the output voltage dividing signal of the second voltage dividing module. Optionally, the second voltage dividing module can be a voltage dividing circuit composed of two resistors (or more resistors). For example, the resistor R4 and the resistor R5 are connected in series, and the voltage across the resistor R4 (or R5) is used as the output voltage, and this output voltage can be used to control the second enable terminal of the above-mentioned second chip. For example, assume that the voltage value of the second enable terminal of the second chip is greater than or equal to 3V (or 1.2V, or other values), that is, when it corresponds to a high level, the second enable terminal is effective, and at this time the second chip can work normally. When the voltage value of the second enable terminal of the second chip is less than 3V (or 1.2V, or other values), the second chip cannot work normally, and at this time the second output terminal of the second chip is 0V; in this way, the second enable terminal of the second chip can be controlled by the second voltage dividing module. For example, the second chip can be controlled to perform a power-down operation at the third moment. The third moment can be the same as or different from the aforementioned first moment.

[0049] In an alternative embodiment, it further includes: a second delay module, connected between the second input terminal and the ground terminal, and the output terminal of the second delay module is connected to the second enable terminal, and the control terminal of the second delay module is connected to the second output terminal of the second chip. The second output terminal of the second chip is used to output a target indication signal of the second chip, and the target indication signal is used to indicate whether the second chip has completed the power-on operation. The second voltage dividing module is further used to jointly control the power-down operation of the second chip at the fourth moment through the second enable terminal with the second delay module, and the fourth moment is later than the third moment.

[0050] Optionally, the above-mentioned power-down control circuit may further include a second delay module. The second delay module is connected between the second input terminal of the second chip and the ground terminal, and the output terminal of the second delay module is connected to the second enable terminal of the second chip, and the control terminal of the second delay module is connected to the second output terminal of the second chip. The second output terminal of the second chip is used to output a target indication signal of the second chip, such as the PG terminal of the second chip. The target indication signal is similar toFigure 1 The PSU_PG signal in Figure 1 , and the target indication signal is used to indicate whether the second chip has completed power-on. For example, when the power-on is completed, the target indication signal (such as PG) is 1, and when the power-on is not completed, the target indication signal is 0. The output end of the second delay module is also connected to the second enable end of the second chip. In this way, the second enable end of the second chip can be jointly controlled by the second delay module and the second voltage dividing module, so that the second chip performs a power-off operation at the fourth moment, where the fourth moment is later than the third moment, and the fourth moment can be the same as or different from the aforementioned second moment. For example, the third moment corresponds to the moment when the second output voltage signal drops to 90% (or 85%, or other), and the fourth moment corresponds to the moment when the second output voltage signal drops to 60% (or 50%, or other), so as to achieve the purpose of controlling the second chip to delay power-off.

[0051] In an optional embodiment, the second delay module includes: a first MOS transistor, where the gate of the first MOS transistor is connected to the second output end of the second chip, and the source of the first MOS transistor is connected to the ground end; a second MOS transistor, where the gate of the second MOS transistor is connected to the drain of the first MOS transistor, the drain of the second MOS transistor is connected to the second enable end through a fourth resistor, the source of the second MOS transistor is connected to the second input end, and the gate of the second MOS transistor is connected to the source of the second MOS transistor through a fifth resistor.

[0052] Optionally, the second delay module may include a first MOS transistor and a second MOS transistor. The gate of the first MOS transistor is connected to the second output terminal (such as the PG terminal of the second chip) of the second chip. The source of the first MOS transistor is connected to the ground terminal, and the drain of the first MOS transistor is connected to the gate of the second MOS transistor. For example, the first MOS transistor is an NMOS transistor and the second MOS transistor is a PMOS transistor. In addition, the drain of the second MOS transistor is connected to the second enable terminal of the second chip through a resistor (such as the fourth resistor mentioned above). The source of the second MOS transistor is connected to the second input terminal of the second chip, and a fifth resistor is connected between the gate and the source of the second MOS transistor. In this embodiment, before the second chip is powered on, the second output terminal (such as the PG terminal) of the second chip is 0 (or low level). At this time, the first MOS transistor is turned off, and the second MOS transistor is also in the off state. In this case, the second enable terminal of the second chip is controlled by the second voltage division module mentioned above. When the second output terminal of the second chip is 1 (or high level), it means that the second chip has been powered on. At this time, the first MOS transistor is turned on, and the second MOS transistor is also in the on state. In this case, the second enable terminal of the second chip is jointly controlled by the second voltage division module and the second delay module. Specifically, it is jointly determined by the second voltage division module and the fourth resistor in the second delay module. Therefore, according to the actual working requirements, when the power supply is powered off (or loses power), the fourth resistor can be designed or selected to control the second enable terminal of the second chip to change from high level to low level at different times, that is, to control the second chip to perform a power-off operation at different times.

[0053] In an alternative embodiment, when the resistance value of the fourth resistor is equal to the second target resistance value and the first output voltage signal drops from the second normal voltage value to the second predetermined voltage value, the second voltage division module and the second delay module jointly control the second chip to perform a power-off operation at the fourth time through the second enable terminal, where the second predetermined voltage value is a second predetermined ratio of the second normal voltage value, and the input voltage signal drops to the second predetermined voltage value at the fourth time.

[0054] Optionally, as can be seen from the foregoing embodiments, by designing or selecting the fourth resistor, the purpose of delaying the power-off of the second chip can be achieved. For example, the resistance value of the fourth resistor is equal to the second target resistance value (such as xxΩ / KΩ, or others). When the first output voltage signal (such as Figure 3When the P12V in it drops from the second normal voltage value (such as 12V) to the second predetermined voltage value (such as 60% of the second normal voltage value, or others), the voltage signal input to the second enable terminal changes from high level to low level, that is, it can control the second chip to perform a power-off operation at the moment when the input voltage signal drops to 60%. Optionally, the resistance value of the fourth resistor can be adjusted according to actual needs. For example, the resistance value of the fourth resistor is designed as other resistance values. When the first output voltage signal (such as Figure 3 When the P12V in it drops from the second normal voltage value (such as 12V) to other predetermined voltage values (such as 50% of the second normal voltage value, or others), the voltage signal input to the second enable terminal changes from high level to low level, that is, it can control the first chip to perform a power-off operation at the moment when the input voltage signal drops to 50%. It is also possible to design or select the resistance value of the fourth resistor and the resistance values of the two resistors in the second voltage division module to achieve the closing of the second enable terminal of the second chip at the required voltage threshold (that is, the voltage threshold for changing from high level to low level). Through this embodiment, the purpose of flexibly controlling the power-off operation of the second chip can be achieved.

[0055] In an optional embodiment, the second voltage division module includes: a sixth resistor, where the first end of the sixth resistor is connected to the second input terminal; a seventh resistor, where the first end of the seventh resistor is connected to the second end of the sixth resistor, the second end of the seventh resistor is connected to the ground terminal, and the first end of the seventh resistor is connected to the second enable terminal.

[0056] Optionally, the above second voltage division module can be a voltage division circuit composed of two resistors (or more resistors). For example, the resistor R4 (corresponding to the above sixth resistor) and the resistor R5 (corresponding to the above seventh resistor) are connected in series, and the voltage across the resistor R5 is used as the output voltage, and this output voltage can be used to control the second enable terminal of the above second chip. For example, assuming that the voltage value of the second enable terminal of the second chip is greater than or equal to 3V (or 1.2V, or other values), that is, corresponding to the high level, the second enable terminal is effective and the second chip can work normally. When the voltage value of the second enable terminal of the second chip is less than 3V (or 1.2V, or other values), the second chip cannot work normally, and at this time, the second output terminal of the second chip is 0V; that is, the voltage across the seventh resistor in the second voltage division module is used to control the second enable terminal of the second chip.

[0057] Obviously, the above-described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. The present invention will be specifically described below in conjunction with the embodiments.

[0058] The embodiment of the present application provides a circuit solution for delayed power-off, which is turned on when the 12V power supply of the main board reaches 90% of the power-on of the 12V_Input of the PSU, and is turned off when the 12V_Input drops to a relatively low voltage during power-off (according to design requirements, for example: the 12V power supply is turned off when it drops to 50%). P3V3 is the main power supply of the CPLD on the main board, and the power-on and power-off timing also needs to be adjusted. When the 12V power supply of the main board rises above 90%, the Buck power conversion module for converting 12V to 3.3V (corresponding to the aforementioned second chip) is turned on. When the 12V power supply drops to a relatively low voltage, the P3V3 power supply is turned off, allowing the CPLD to have time to turn off other power supplies according to the timing requirements.

[0059] Figure 5 It is a schematic diagram of the improved power-on and power-off timing of 12V according to the embodiment of the present application, and the power-on timing remains unchanged. Figure 5 The change process of the PSU_PG signal in Figure 1 is the same as that in Figure 5 That is, when the P12V_Input is powered on to 90%, the PSU_PG is at a high level, and when the P12V_Input drops to 90% during power-off, the PSU_PG becomes a low level; if the PSU_PG signal is used to control the enable terminal Enable of the Efuse of the P12V power supply (corresponding to the aforementioned first chip), the purpose of delayed power-off cannot be achieved. During the power-off process, when the P12V_Input power supply drops to a relatively low voltage value (such as 50%,

[0060] Figure 6 It is a schematic diagram of the improved power-on and power-off timing of 3.3V according to the embodiment of the present application. The power-off process of the 3.3V power supply on the main board is also optimized: Figure 6 The change process of the P12V_PG signal in Figure 3 is the same as that in Figure 6 That is, when the P12V is powered on to 90%, the P12V_PG is at a high level, and when the P12V drops to 90% during power-off, the P12V_PG becomes a low level; if the P12V_PG signal is used to control the enable terminal Enable of the P3V3 power supply (corresponding to the second enable terminal of the aforementioned second chip), the purpose of delayed power-off cannot be achieved. When the 12V power supply (corresponding to Figure 6 the P12V inFigure 6 The Buck power supply module with P3V3. The duration of the 3.3V voltage on the main board is extended from the original T3 time (corresponding to the aforementioned third moment) to T4 (corresponding to the aforementioned fourth moment). During the T4 time, the CPLD can sequentially turn off other power supplies on the main board as needed.

[0061] To more clearly illustrate the implementation scheme of the embodiments of the present application, the following will be described in detail with reference to the circuit diagram.

[0062] Figure 7 It is a schematic diagram of the timing control circuit of the 12V Efuse according to the embodiments of the present application. The following will explain the circuit principle:

[0063] (1) The 200 node (corresponding to the first input terminal of the aforementioned first chip) is the input voltage 12V_Input of the main board, and the 300 node (corresponding to the first output terminal of the aforementioned first chip) is the 12V power supply output of the Efuse. The original design method is that the 101 node (Enable signal, corresponding to the first enable terminal of the aforementioned first chip) directly controls the power-on of the Efuse by using the voltage division method of R1 (corresponding to the aforementioned second resistor) and R2 (corresponding to the aforementioned third resistor). The current circuit adds a D1 diode (corresponding to the aforementioned second diode) between R1 and the 200 node, and at the same time connects the 101 node to the 300 node through a resistor R3 (corresponding to the aforementioned first resistor) and a diode D2 (corresponding to the aforementioned first diode).

[0064] (2) Before the Efuse is powered on, the voltage of the 300 node is 0V. Then, the voltage of the 101 node is calculated according to the following formula 1:

[0065]

[0066] Where: V F is the forward voltage drop of the diode D1. According to this formula, appropriate R1 and R2 can be selected. When the voltage of the 200 node climbs to 90%, the 101 node reaches the Enable threshold of the Efuse.

[0067] (3) After the Efuse is powered on, the voltages of 12V_Input and 12V are almost the same. According to the same calculation, the voltage of 101 is calculated according to formula 2:

[0068]

[0069] VF is the forward voltage drop of D1 and D2. By selecting an appropriate R3, when the voltage of the 200 node drops to a predetermined value, such as 50%, the 101 node reaches the Enable off threshold of the Efuse.

[0070] (4) Diodes D1 and D2 can prevent leakage and avoid leakage between 12V_Input and the 12V power supply.

[0071] For the first power supply P3V3 converted by the Buck power module on the main board, the power-on and power-off timing control circuit of this power supply is as Figure 8 shown. The following explains the circuit principle:

[0072] (1) In the original design, the Enable (node 102, corresponding to the second enable terminal of the aforementioned second chip) of the Buck power module (or called the VR conversion chip, corresponding to the aforementioned second chip) is controlled by voltage division using R4 (corresponding to the aforementioned sixth resistor) and R5 (corresponding to the aforementioned seventh resistor) in the figure. Appropriate values of R4 and R5 can be selected to ensure that when the voltage at node 300 (corresponding to the second input terminal of the aforementioned second chip) rises to 90%, node 102 reaches the Enable threshold of the VR chip. The calculation method is as formula 3.

[0073]

[0074] (2) Now, add N-type MOS transistor Q2 (corresponding to the aforementioned first MOS transistor), P-type MOS transistor Q1 (corresponding to the aforementioned second MOS transistor), as well as resistor R7 (corresponding to the aforementioned fifth resistor) and R6 (corresponding to the aforementioned fourth resistor). Before the VR conversion chip of P3V3 is powered on, the PG signal (node 104, corresponding to the second output terminal of the aforementioned second chip) of the VR is at a low level, Q2 is turned off, the voltage of 103 is the same as that of node 300, Q1 is also in the off state, and the voltage of node 102 is calculated according to formula 3.

[0075] (3) Select node 104: The PG signal of the VR chip is used as the indication signal (corresponding to the aforementioned target indication signal). After the VR chip is powered on, P3V3 (corresponding Figure 8 to node 400) outputs normally, the voltage of node 104 is at a high level. At this time, MOS transistor Q2 conducts, node 103 becomes low level, MOS transistor Q1 conducts, and resistor R6 is connected between node 300 and 102. The voltage of node 102 is tested and calculated according to the following formula 4. By selecting an appropriate value of R6, it can be effectively set that when node 300 drops to the specified threshold (such as 50%), node 102 reaches the off threshold of Enable.

[0076]

[0077] The above two different circuits realize the function of powering on only after the previous-stage power supply is fully powered on (more than 90%) and powering off when the previous-stage power supply drops to a lower voltage (such as 50%, set according to requirements) through the circuit switching methods of enabling the two power supplies of the 12V Efuse and the P3V3 VR conversion chip during power-on and power-off.

[0078] In the above embodiment, the 12V Efuse is adjusted from being controlled by resistor voltage division to being jointly controlled by two paths, and two anti-reverse diodes are added to avoid leakage. The resistance value of the newly added control circuit is calculated according to the power-off threshold required. The Enable of the Buck power supply module that converts 12V to P3V3 has a newly added control circuit compared with the traditional resistor voltage division control: this control circuit is controlled by the indication signal PG to control an N-type MOS, a P-type MOS, and a newly added voltage-dividing resistor, and the required resistance value is calculated according to the power-off threshold required.

[0079] Through the above embodiment, the Enable control loop of the 12V Efuse is improved. The power-on working circuit and the power-off working circuit are different, realizing the function of power-off delay, and at the same time ensuring the purpose of no leakage between the two power supplies on both sides; the Enable control circuit of the P3V3 power supply is improved. After the power-on is completed, the control circuit that switches the Enable is controlled by the indication signal to achieve the purpose of delayed power-off. Through the embodiments of this application, for the two power supplies of the 12V and P3V3 power supplies: powering on only after the previous-stage power supply is powered on (powering on late), and powering off as soon as the previous-stage power supply starts to power off (powering off early), these two contradictory problems, the improved circuit can achieve the problems of powering on late and powering off late.

[0080] It should be noted that the above-mentioned various units or modules can be implemented by software or hardware. For the latter, it can be achieved in the following ways, but not limited to this: the above-mentioned units or modules are all located in the same processor; or, the above-mentioned various units or modules are separately located in different processors in any combination form.

[0081] The specific examples in this embodiment can refer to the examples described in the above embodiment and the exemplary embodiments, and will not be repeated here.

[0082] Obviously, those skilled in the art should understand that the various modules or steps of the embodiments of the present application described above can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. They can be implemented by program codes executable by the computing device. Thus, they can be stored in a storage device and executed by the computing device. And in some cases, the steps shown or described can be executed in a sequence different from that here, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module for implementation. In this way, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0083] The above are only the preferred embodiments of the present application and are not used to limit the embodiments of the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the principle of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A power-down control circuit, characterized in that, it includes: A first chip, configured to convert an input voltage signal into a first output voltage signal. Wherein, when the first enable terminal of the first chip is at a first level value, the first output voltage signal is equal to the input voltage signal; when the first enable terminal of the first chip is at a second level value, the voltage value of the first output voltage signal is zero; A first voltage dividing module, connected between the input terminal of the first chip and the ground terminal. The output terminal of the first voltage dividing module is connected to the first enable terminal of the first chip. The first voltage dividing module is configured to control the first chip to perform a power-down operation at a first moment through the first enable terminal; A first delay module, connected between the first output terminal of the first chip and the first enable terminal. Wherein, the first voltage dividing module is further configured to jointly control the first chip to perform a power-down operation at a second moment through the first enable terminal and the first delay module, wherein the second moment is later than the first moment; The control circuit further includes: A second chip, wherein the second input terminal of the second chip is connected to the first output terminal of the first chip. The second chip is configured to convert the first output voltage signal into a second output voltage signal; A second voltage dividing module, connected between the second input terminal and the ground terminal. The output terminal of the second voltage dividing module is connected to the second enable terminal of the second chip. The second voltage dividing module is configured to control the second chip to perform a power-down operation at a third moment through the second enable terminal.

2. The control circuit according to claim 1, characterized in that, the first delay module includes: A first resistor, connected between the first output terminal and the first enable terminal, wherein the first output terminal is configured to output the first output voltage signal; Or, A first resistor and a first diode, wherein the positive electrode of the first diode is connected to the first output terminal, the negative electrode of the first diode is connected to the first enable terminal through the first resistor, and the first output terminal is configured to output the first output voltage signal.

3. The control circuit according to claim 2, characterized in that, when the resistance value of the first resistor is equal to a first target resistance value, and when the input voltage signal drops from a first normal voltage value to a first predetermined voltage value, the first voltage dividing module and the first delay module jointly control the first chip to perform a power-down operation at the second moment through the first enable terminal, wherein the first predetermined voltage value is a first predetermined ratio of the first normal voltage value, and the input voltage signal drops to the first predetermined voltage value at the second moment.

4. The control circuit according to claim 1, characterized in that, it further includes: A second diode, wherein the positive electrode of the second diode is connected to the first input terminal of the first chip, the negative electrode of the second diode is connected to the first end of the first voltage dividing module, and the second end of the first voltage dividing module is connected to the ground terminal. The first input terminal is configured to input the input voltage signal; Wherein, when the input voltage signal is in the power-down period, the first voltage dividing module and the first delay module jointly control the first chip to perform a power-down operation at the second moment through the first enable terminal. The power-down period represents the process in which the input voltage signal drops from a normal voltage value to zero, and the power-down period includes the second moment.

5. The control circuit according to claim 4, wherein, the first voltage dividing module includes: a second resistor, wherein the first end of the second resistor is connected to the negative electrode of the second diode; a third resistor, wherein the first end of the third resistor is connected to the second end of the second resistor, the second end of the third resistor is connected to the ground terminal, and the first end of the third resistor is connected to the first enable terminal.

6. The control circuit according to claim 1, wherein, it further includes: a second delay module, connected between the second input terminal and the ground terminal, and the output terminal of the second delay module is connected to the second enable terminal, and the control terminal of the second delay module is connected to the second output terminal of the second chip. Wherein, the second output terminal of the second chip is used to output a target indication signal of the second chip, and the target indication signal is used to indicate whether the second chip has completed a power-on operation. The second voltage dividing module is further used to jointly control the second chip to perform a power-down operation at the fourth moment through the second enable terminal with the second delay module, and the fourth moment is later than the third moment.

7. The control circuit according to claim 6, wherein, the second delay module includes: a first MOS transistor, wherein the gate of the first MOS transistor is connected to the second output terminal of the second chip, and the source of the first MOS transistor is connected to the ground terminal; a second MOS transistor, wherein the gate of the second MOS transistor is connected to the drain of the first MOS transistor, the drain of the second MOS transistor is connected to the second enable terminal through a fourth resistor, the source of the second MOS transistor is connected to the second input terminal, and the gate of the second MOS transistor is connected to the source of the second MOS transistor through a fifth resistor.

8. The control circuit according to claim 7, wherein, when the resistance value of the fourth resistor is equal to the second target resistance value, and the first output voltage signal drops from the second normal voltage value to the second predetermined voltage value, the second voltage dividing module and the second delay module jointly control the second chip to perform a power-down operation at the fourth moment through the second enable terminal, wherein the second predetermined voltage value is a second predetermined ratio of the second normal voltage value, and the input voltage signal drops to the second predetermined voltage value at the fourth moment.

9. The control circuit according to claim 1, wherein, the second voltage dividing module includes: a sixth resistor, wherein the first end of the sixth resistor is connected to the second input terminal; The seventh resistor, wherein a first end of the seventh resistor is connected to a second end of the sixth resistor, a second end of the seventh resistor is connected to the ground terminal, and the first end of the seventh resistor is connected to the second enable terminal.

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