Method, apparatus, device, and medium for matching signal line length with via stub length

Abstract

The present application relates to a method, device, equipment, and medium for matching the length of a signal line with the length of a via stub. The method includes: establishing a transmission line model of PCB materials with different energy loss levels; establishing a via model of PCB materials with different energy loss levels, different via sizes, different effective via lengths, and different via stub lengths; building a time-domain and frequency-domain simulation link; obtaining the design parameters in the simulation link and quantifying and formulating them; setting the fixed design parameters of the simulation link according to the SI index of the high-speed signal link and optimizing the adjustable design parameters, and setting the variation range of the optimized adjustable design parameters; running simulation software to obtain simulation results; summarizing the simulation results to form a corresponding relationship table between the signal line length and the via stub length. By using this method to summarize and form a general corresponding relationship table between the PCB line length and the via stub length that meets the SI index of the overall high-speed signal link, the project development progress can be improved.

Description

Technical Field

[0001] This application relates to the technical field of printed circuit boards, and particularly to a method, device, equipment, and medium for matching the length of signal lines with the length of via stubs. Background Art

[0002] As the signal rate on the server & memory system board becomes faster and faster, the design requirements for printed circuit boards (PCBs) are becoming more and more stringent, and the detailed processing of each interconnected component needs to be treated strictly. For high-speed line signals, such as PCIE4.0 and PCIE5.0, if the line length is too long or the length of the via stub for layer change is too long, the SI index of this high-speed signal link will decrease. Therefore, SI engineers need to perform simulation analysis according to the allowable range of the signal line length and the via stub length for the project, and obtain the corresponding relationship between the allowable via stub length for a certain line length to guide the PCB routing design.

[0003] Generally, for the high-speed signal lines of printed circuit boards (PCBs), optimization is carried out based on the position or size of a certain via on the signal line to find the low-impedance return path of a single via, and it is not possible to reasonably set the lengths of all via stubs on the high-speed signal line from the overall perspective of the high-speed signal line to simulate and form a routing method that meets the SI index of the high-speed signal link. Even if the simulation of this link is performed for the current PCB line length and the via stub length, and the time-domain and frequency-domain simulation information is obtained, and it is judged whether it passes according to the time-domain and frequency-domain simulation results, this simulation strategy is a single simulation based on a specific project and a specific board, and no general routing rules are formed, which is not conducive to project development in case of an urgent project. At the same time, from the overall perspective of the high-speed signal line, there is no need to optimize the length of each via stub, but to meet the SI index of the overall high-speed signal link by selecting reasonable via stub length parameters. Thus, it is possible to meet the requirements of the SI index of the overall high-speed signal link by avoiding the optimization method only for the position or size of each via.

[0004] Therefore, how to form a general routing rule that meets the SI index of the overall high-speed signal link through simulation from the overall perspective of the high-speed signal line has become a key influencing factor in improving the project development progress. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a method, device, equipment, and medium for matching the length of signal lines with the length of via stubs, which can scan and analyze the corresponding relationship between the PCB line length and the via stub length from the overall perspective of the high-speed signal line, so as to form a general corresponding relationship table between the PCB line length and the via stub length that meets the SI index of the overall high-speed signal link, and is used to improve the project development progress.

[0006] On the one hand, a method for matching the length of a signal line with the length of a via stub is provided. The method includes:

[0007] Using simulation software to establish a transmission line model of PCB materials with different energy loss levels;

[0008] Using simulation software to establish via models of PCB materials with different energy loss levels, different via sizes, different effective via lengths, and different via stub lengths;

[0009] Build a time-domain and frequency-domain simulation link, where the simulation link is a signal line composed of the transmission line model and the via model;

[0010] Obtain the design parameters of the transmission line model and the via model in the simulation link, and parameterize and formulate the design parameters of the transmission line model and the via model;

[0011] Set the fixed design parameters of the simulation link according to the SI index of the high-speed signal link and optimize the adjustable design parameters, and set the variation range of the optimized adjustable design parameters;

[0012] Run the simulation software to obtain simulation results that meet the SI index of the high-speed signal link; and

[0013] Summarize the design parameters of different stacks, different energy loss level PCB materials, and different via stub lengths of each project into the PCB interconnect component design system, analyze the corresponding relationship between the signal line length and the via stub length, and form a corresponding relationship table between the signal line length and the via stub length.

[0014] In one embodiment, in the step of using simulation software to establish a transmission line model of PCB materials with different energy loss levels, it includes:

[0015] Obtain the loss amounts of PCB materials with various energy loss levels;

[0016] Input various energy loss level PCB materials and their corresponding loss amounts into the simulation software;

[0017] Establish a general stack structure of the transmission line, and the composed film layers of the stack structure include a signal layer, a dielectric layer, and a reference layer;

[0018] Set the thickness and coordinate values of each layer of the stack structure;

[0019] Extract the corresponding transmission line models according to different energy loss level PCB materials and different stack structures.

[0020] In one embodiment, in the step of obtaining the loss amounts of PCB materials with various energy loss levels, the PCB materials with various energy loss levels obtained are medium-loss PCB materials, low-loss PCB materials, and ultra-low-loss PCB materials; the length of the signal line is in inches as the length unit, and for PCB materials with different energy loss levels, their loss per inch is different at different frequency points; the loss amount is the per-inch insertion loss data of PCB materials with various energy loss levels at each frequency point; the total insertion loss of each signal line in the transmission line model = per-inch insertion loss data * signal line length.

[0021] In one embodiment, the step of using simulation software to establish via models of PCB materials with different energy loss levels, different via sizes, different via effective lengths, and different via stub lengths includes:

[0022] Obtain the via size and the spacing between two adjacent vias for PCB materials with different energy loss levels;

[0023] According to the coordinate values of the signal layers in the stack-up structure, obtain the film layers where the via enters and exits the line, and calculate the via effective length in combination with the thickness of each layer in the stack-up structure;

[0024] Obtain the corresponding via stub length based on the via effective length.

[0025] In one embodiment, the step of obtaining the design parameters of the transmission line model and the via model in the simulation link, and parameterizing and formulating the design parameters of the transmission line model and the via model includes:

[0026] Establish a back-drilling depth variable, with 1 mil as the reference, and increase the back-drilling depth in units of 1 mil, and scan to obtain the SI characteristics of vias with different via stub lengths;

[0027] Establish ports, and use wave ports at the transmission line;

[0028] Obtain the design parameters in the simulation link, where the design parameters include: PCB materials with various energy loss levels are medium-loss PCB materials, low-loss PCB materials, and ultra-low-loss PCB materials, the thickness and coordinate values of each layer in the stack-up structure, via size, the spacing between two adjacent vias, via effective length, via stub length, and number of vias.

[0029] In one embodiment, in the step of setting the fixed design parameters of the simulation link according to the SI metrics of the high-speed signal link, optimizing the adjustable design parameters, and setting the variation range of the optimized adjustable design parameters, the fixed design parameters include the constituent film layers of the stacked structure, the thickness of each layer of the stacked structure, and the line length of the signal line; the optimized adjustable design parameters include the via size, the pitch between two adjacent vias, the effective length of the via, the stub length of the via, the number of vias, the reference line length, the step line length, insertion loss, impedance, and return loss.

[0030] In one embodiment, when running the simulation software to obtain the simulation results that meet the SI metrics of the high-speed signal link, it includes:

[0031] For medium-loss PCB materials, the transmission line is based on 3000 mil, and then stepped by 500 mil to scan to 8 inches. Adding the different stub lengths of the vias in the medium-loss PCB material, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different stub lengths of the vias in the medium-loss PCB material are obtained through scanning simulation;

[0032] For low-loss PCB materials, the transmission line is based on 5000 mil, and then stepped by 500 mil to scan to 10 inches. Adding the different stub lengths of the vias in the low-loss PCB material, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different stub lengths of the vias in the low-loss PCB material are obtained through scanning simulation;

[0033] For ultra-low-loss PCB materials, the transmission line is based on 7000 mil, and then stepped by 500 mil to scan to 15 inches. Adding the different stub lengths of the vias in the ultra-low-loss PCB material, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different stub lengths of the vias in the ultra-low-loss PCB material are obtained through scanning simulation;

[0034] The obtained simulation results include S parameters. The S parameters are analyzed in the time domain and frequency domain in the system to determine the time-domain and frequency-domain margins of the system.

[0035] On the other hand, a device for matching the signal line length and the via stub length is provided. The device includes:

[0036] A transmission line model establishment module for establishing a transmission line model of PCB materials with different energy loss levels using simulation software;

[0037] A via model establishment module for establishing via models of PCB materials with different energy loss levels, different via sizes, different effective lengths of vias, and different stub lengths of vias using simulation software;

[0038] Establish a simulation link module for building a time-domain and frequency-domain simulation link, where the simulation link is a signal line composed of the transmission line model and the via model;

[0039] Design parameter quantization module, used to obtain the design parameters of the transmission line model and the via model in the simulation link, and variablize and formulate the design parameters of the transmission line model and the via model;

[0040] Design parameter setting module, used to set the fixed design parameters of the simulation link and optimize the adjustable design parameters according to the SI index of the high-speed signal link, and set the change range of the optimized adjustable design parameters;

[0041] Simulation result acquisition module, used to run simulation software to obtain simulation results that meet the SI index of the high-speed signal link; and

[0042] Generate a correspondence table module, used to summarize the design parameters of different stacks, different energy loss level PCB materials, and different via stub lengths in each project into the PCB interconnection component design system, analyze the correspondence between the signal line length and the via stub length, and form a correspondence table between the signal line length and the via stub length.

[0043] On the other hand, a computer device is provided, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the following steps are implemented:

[0044] Use simulation software to establish a transmission line model of PCB materials with different energy loss levels;

[0045] Use simulation software to establish via models of PCB materials with different energy loss levels, different via sizes, different via effective lengths, and different via stub lengths;

[0046] Build a time-domain and frequency-domain simulation link, where the simulation link is a signal line composed of the transmission line model and the via model;

[0047] Obtain the design parameters of the transmission line model and the via model in the simulation link, and variablize and formulate the design parameters of the transmission line model and the via model;

[0048] Set the fixed design parameters of the simulation link and optimize the adjustable design parameters according to the SI index of the high-speed signal link, and set the change range of the optimized adjustable design parameters;

[0049] Run simulation software to obtain simulation results that meet the SI index of the high-speed signal link; and

[0050] Summarize the design parameters of different stacks, different energy loss levels of PCB materials, and different via stub lengths for each project into the PCB interconnect component design system, analyze the corresponding relationship between the signal line length and the via stub length, and form a corresponding relationship table between the signal line length and the via stub length.

[0051] In another aspect, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0052] Use simulation software to establish a transmission line model of PCB materials with different energy loss levels;

[0053] Use simulation software to establish via models of PCB materials with different energy loss levels, different via sizes, different effective via lengths, and different via stub lengths;

[0054] Build a time-domain and frequency-domain simulation link, where the simulation link is a signal line composed of the transmission line model and the via model;

[0055] Obtain the design parameters of the transmission line model and the via model in the simulation link, and parameterize and formulate the design parameters of the transmission line model and the via model;

[0056] Set the fixed design parameters of the simulation link and optimize the adjustable design parameters according to the SI index of the high-speed signal link, and set the change range of the optimized adjustable design parameters;

[0057] Run the simulation software to obtain simulation results that meet the SI index of the high-speed signal link; and

[0058] Summarize the design parameters of different stacks, different energy loss levels of PCB materials, and different via stub lengths for each project into the PCB interconnect component design system, analyze the corresponding relationship between the signal line length and the via stub length, and form a corresponding relationship table between the signal line length and the via stub length.

[0059] The above method, device, equipment, and medium for matching the signal line length and the via stub length start from the overall perspective of the high-speed signal line, scan and analyze the corresponding relationship between the PCB line length and the via stub length, summarize and form a general corresponding relationship table between the PCB line length and the via stub length that meets the SI index of the overall high-speed signal link, and use it as interconnection information reserve for quick reference in subsequent project designs, which can improve the project development progress. Description of the Drawings

[0060] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0061] Figure 1 It is an application environment diagram for simulating a signal line length and via stub length matching method in an embodiment with a single connector topology.

[0062] Figure 2 It is an application environment diagram for simulating a signal line length and via stub length matching method in an embodiment with two connector topologies.

[0063] Figure 3 It is a schematic flowchart of a method for matching signal line length and via stub length in an embodiment.

[0064] Figure 4 It is a schematic flowchart of the steps for establishing a transmission line model of PCB materials with different energy loss levels using simulation software in an embodiment.

[0065] Figure 5 It is a schematic flowchart of the steps for establishing a via model of PCB materials with different energy loss levels, different via sizes, different via effective lengths, and different via stub lengths using simulation software in an embodiment.

[0066] Figure 6 It is a schematic flowchart of the steps for obtaining the design parameters of the transmission line model and the via model in the simulation link, and parameterizing and formulating the design parameters of the transmission line model and the via model in an embodiment.

[0067] Figure 7 It is a schematic plan view of a via stub in an embodiment.

[0068] Figure 8 It is a schematic cross-sectional view of a via stub in an embodiment.

[0069] Figure 9 It is a structural block diagram of a device for matching signal line length and via stub length in an embodiment.

[0070] Figure 10 It is an internal structure diagram of a computer device in an embodiment. Detailed implementation manners

[0071] In order to make the objectives, technical solutions, and advantages of this application clearer, the following further elaborates on this application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely used to explain this application and are not used to limit this application.

[0072] The method for matching the signal line length and the via stub length provided by this application can be applied to an application environment such as Figure 1 , Figure 2 as shown. Among them, Figure 1 simulation analysis is performed on a topology of a PCIe5.0 connector (SMT). As Figure 2 shown, if it is a topology of two connectors (SMT), scanning analysis can be performed by matching two boards with different PCB materials, and the method is similar to Figure 1 the method for matching the signal line length and the via stub length. The method basically includes: establishing a transmission line model for different grades of PCB materials; establishing a via model for different grades of PCB materials, different via sizes, different via effective lengths, and different via stub lengths; taking the connector model for the transmitter & receiver & board interconnection as an example of the simulation model provided by Intel; and then building a time-domain and frequency-domain simulation link. Variable the transmission line model and the via model, and for different grades of PCB materials with different energy loss levels, obtain the time-domain and frequency-domain simulation results corresponding to different line lengths and different via stub lengths through scanning simulation.

[0073] In one embodiment, as Figure 3 shown, a method for matching the signal line length and the via stub length is provided. Taking the application of this method to Figure 1 , Figure 2 one or two connector (SMT) topologies for simulation analysis as an example, the method includes the following steps:

[0074] Step S1, use simulation software to establish a transmission line model for different grades of PCB materials with different energy loss levels;

[0075] Step S2, use simulation software to establish a via model for different grades of PCB materials, different via sizes, different via effective lengths, and different via stub lengths;

[0076] Step S3, build a time-domain and frequency-domain simulation link, and the simulation link is a signal line composed of the transmission line model and the via model;

[0077] Step S4, obtain the design parameters of the transmission line model and the via model in the simulation link, and variable and formulate the design parameters of the transmission line model and the via model;

[0078] Step S5: Set the fixed design parameters and optimized adjustable design parameters of the simulation link according to the SI indicators of the high-speed signal link, and set the variation range of the optimized adjustable design parameters;

[0079] Step S6: Run the simulation software to obtain the simulation results that meet the SI indicators of the high-speed signal link; and

[0080] Step S7: Summarize the design parameters of different stacks, different energy loss level PCB materials, and different via stub lengths of each project into the PCB interconnection component design system, analyze the corresponding relationship between the signal line length and the via stub length, and form a corresponding relationship table between the signal line length and the via stub length.

[0081] In this embodiment, based on the invariance of the signal line length, from the overall perspective of the high-speed signal line, summarize the different stack, different PCB material, and different via design parameters of each project into the PCB interconnection component design system, scan and analyze the corresponding relationship between the PCB line length and the via stub length, so as to form a general corresponding relationship table between the PCB line length and the via stub length that meets the overall SI indicators of the high-speed signal link, as an interconnection information reserve for quick reference in subsequent project designs, which can improve the project development progress.

[0082] Among them, the noun PCB is the definition of a printed circuit board, which is the abbreviation of Printed Circuit Board.

[0083] Specifically, through the above simulation, obtain the time-domain and frequency-domain simulation result information corresponding to different line lengths and vias, and then conduct summary analysis to obtain the corresponding relationship between the general line length and the via stub, and provide it to the layout engineer for layout and wiring design, thereby shortening the project development cycle.

[0084] As Figure 4 shown, in this embodiment, in step S1 of using the simulation software to establish the transmission line model of PCB materials with different energy loss levels, it includes:

[0085] Step S11: Obtain the loss amounts of various energy loss level PCB materials;

[0086] Step S12: Input various energy loss level PCB materials and their corresponding loss amounts into the simulation software;

[0087] Step S13: Establish a general stack structure of the transmission line, and the constituent film layers of the stack structure include a signal layer, a dielectric layer, and a reference layer;

[0088] Step S14: Set the thickness and coordinate values of each layer of the stack structure;

[0089] Step S15: Extract corresponding transmission line models according to PCB materials with different energy loss levels and different stack-up structures.

[0090] The method for extracting the transmission line model is as follows: First, establish a general stack-up structure with an outer prepreg of 2.7 mil and a line width and pitch of 85 ohm, such as 4.8 / 6.4 mil. The line width and pitch can be optimized through scanning different PCB materials; inner layer stack-up structures such as 3 / 6 (3 mil core, 6 mil prepreg), 4 / 5 (4 mil core, 5 mil prepreg), 3 / 9 (3 mil core, 9 mil prepreg), etc., to form a 4 / 5 stack-up structure. Extract corresponding transmission line models according to different materials and different stack-up structures.

[0091] In this embodiment, in the step of obtaining the loss amounts of PCB materials with various energy loss levels, the obtained PCB materials with various energy loss levels are medium-loss PCB materials, low-loss PCB materials, and ultra-low-loss PCB materials; the line length of the signal line is in inches. For PCB materials with different energy loss levels, their losses per inch are different at different frequency points; the loss amount is the insertion loss data per inch of PCB materials with various energy loss levels at each frequency point; the total insertion loss of each signal line in the transmission line model = insertion loss data per inch * signal line length.

[0092] The loss energy of the PCB material is manifested in the signal waveform, such as a decrease in voltage amplitude.

[0093] As Figure 5 shown, in this embodiment, step S2 of using simulation software to establish via models of PCB materials with different energy loss levels, different via sizes, different via effective lengths, and different via stub lengths includes:

[0094] Step S21: Obtain via sizes (drill diameter, pad diameter, anti-pad diameter) and the spacing between two adjacent vias for PCB materials with different energy loss levels;

[0095] Step S22: According to the coordinate values of the signal layer in the stack-up structure, obtain the film layer where the via enters and exits the line, and calculate the via effective length in combination with the thickness of each layer of the stack-up structure;

[0096] Step S23: Obtain the corresponding via stub length according to the via effective length.

[0097] It is understandable that for the purpose of calculating the length of the via stub in the general stack-up structure, the signal layers, dielectric layers, and reference layers included in the constituent film layers of the stack-up structure can be divided into the starting layer and the arriving layer according to their uses. According to the two layers connected by the signal via, by comparing the stack-up information of the PCB, the via length and the via stub length are calculated; whether there is back-drilling treatment, if there is back-drilling, determine how much the maximum back-drilling depth is and how the via stub is after back-drilling, so as to determine the via stub length; if there is no back-drilling, then the via stub length is the via stub length calculated previously.

[0098] As Figure 6 shown, in this embodiment, the steps of obtaining the design parameters of the transmission line model and the via model in the simulation link, and parameterizing and formulating the design parameters of the transmission line model and the via model in step S4 include:

[0099] Step S41, establish a back-drilling depth variable, with 1 mil as the benchmark, and increase the back-drilling depth in units of 1 mil, and scan to obtain the SI characteristics of vias with different via stub lengths.

[0100] Step S42, establish ports, and use wave ports at the transmission line.

[0101] Step S43, obtain the design parameters in the simulation link, where the design parameters include: various energy loss levels, PCB materials are medium-loss PCB materials, low-loss PCB materials, and ultra-low-loss PCB materials, the thickness and coordinate values of each layer of the stack-up structure, the via size, the spacing between two adjacent vias, the effective length of the via, the via stub length, and the number of vias.

[0102] In other words, combined with Figure 7 、 Figure 8 the structure diagram of the via stub shown, the extraction of the via model includes:

[0103] 1) Use simulation software for modeling.

[0104] a) Stack-up establishment, including parameterizing and formulating the thickness, coordinates and other parameters of each layer of the signal layer, dielectric layer, and reference layer for reference in other projects.

[0105] b) Parameterize and formulate parameters such as via size (drill diameter, pad diameter, anti-pad diameter), spacing between signal vias, and spacing between signal vias and return ground vias for reference in other projects.

[0106] c) Establish the via in-out line layers, so as to obtain the effective length of the via, and also parameterize it for reference in other projects.

[0107] d) After the via model is established, establish a backdrill depth variable with 1 mil as the reference and increase the backdrill depth in 1 mil increments (so that the via stub length can be obtained), and perform a scan to obtain the SI characteristics of vias with different via stub lengths.

[0108] e) Establish ports and use wave ports at the transmission lines. The parameter variables of each port are formulated for reference in other projects.

[0109] f) Add a solution method and set radiation condition boundaries (PML), excitation, frequency range, etc. The solution of electromagnetic field problems boils down to the solution of Maxwell's equations. In HFSS, the solution of the wave equation is also derived from the differential form of Maxwell's equations. Boundary conditions define the boundaries of the solution region and the electromagnetic field characteristics at the junctions of different objects, and are the basis for solving Maxwell's equations. Only on the premise that the field vectors are single-valued, bounded, and continuously distributed in space, the differential form of Maxwell's equations is valid; at the boundaries of the solution region, at the junctions of different media, and at the field sources, the field vectors are discontinuous, and then the derivatives of the fields lose their meaning. Boundary conditions are to define the electromagnetic field characteristics across discontinuous boundaries. Therefore, correctly understanding, defining, and setting boundary conditions is a prerequisite for correctly using HFSS to simulate and analyze electromagnetic field characteristics. Types of excitation in HFSS: In HFSS, excitation is a type of excitation source defined on the surface of a three-dimensional object or a two-dimensional object, and this type of excitation source can be an electromagnetic wave excitation, a voltage source, or a current source. The excitation port is a special type of boundary condition that allows energy to enter or exit the geometric structure.

[0110] g) Set the parameters to be optimized.

[0111] h) Run the simulation, view the simulation results or save the simulation results, such as S-parameters, and then put the S-parameters into the system for time-domain and frequency-domain analysis to determine the time-domain and frequency-domain margins of the system.

[0112] 2) Summarize the different stack-ups, different PCB materials, and different via design parameters of each project into the PCB interconnect component design system as interconnect information reserves for quick reference in subsequent project designs.

[0113] In this embodiment, in the step of setting the fixed design parameters of the simulation link and optimizing the adjustable design parameters according to the SI indicators of the high-speed signal link, and setting the change range of the optimized adjustable design parameters, the fixed design parameters include the constituent film layers of the stack-up structure, the thickness of each layer of the stack-up structure, and the signal line length; the optimized adjustable design parameters include via size, the spacing between adjacent vias, the effective length of the via, the via stub length, the number of vias, the reference line length, the step line length, insertion loss, impedance, and return loss.

[0114] In this embodiment, when running the simulation software to obtain the simulation results that meet the SI metrics of the high-speed signal link, it includes:

[0115] For the medium-loss PCB material, the transmission line is based on 3000 mil, and then steps by 500 mil until it scans to 8 inches. Adding different via stub lengths of the medium-loss PCB material, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different via stub lengths of the medium-loss PCB material are obtained through scanning simulation;

[0116] For the low-loss PCB material, the transmission line is based on 5000 mil, and then steps by 500 mil until it scans to 10 inches. Adding different via stub lengths of the low-loss PCB material, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different via stub lengths of the low-loss PCB material are obtained through scanning simulation;

[0117] For the ultra-low-loss PCB material, the transmission line is based on 7000 mil, and then steps by 500 mil until it scans to 15 inches. Adding different via stub lengths of the ultra-low-loss PCB material, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different via stub lengths of the ultra-low-loss PCB material are obtained through scanning simulation;

[0118] The obtained simulation results include S-parameters. The S-parameters are subjected to time-domain and frequency-domain analysis in the system to determine the time-domain and frequency-domain margins of the system.

[0119] Among them, the S-parameters, that is, scattering parameters, are an important parameter in microwave transmission. The S-parameters are a form of output of via modeling simulation. A file in.snp format contains the electrical characteristics of this via.

[0120] In the above method for matching the signal line length and the via stub length, by starting from the overall perspective of the high-speed signal line and performing a scanning analysis on the corresponding relationship between the PCB line length and the via stub length, a general corresponding relationship table of the PCB line length and the via stub length that meets the overall SI metrics of the high-speed signal link is summarized and formed as interconnection information reserve for quick reference in subsequent project designs, which can improve the project development progress.

[0121] It should be understood that although Figures 2 - 6 the steps in the flowchart of Figures 2 - 6At least a part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed and completed at the same moment, but can be executed at different moments. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turns with at least a part of other steps or sub-steps or stages of other steps.

[0122] In one embodiment, as Figure 9 shown, a device 10 for matching the length of a signal line with the length of a via stub includes: a transmission line model establishing module 1, a via model establishing module 2, a simulation link establishing module 3, a design parameter quantification module 4, a design parameter setting module 5, a simulation result obtaining module 6, and a corresponding relationship table generating module 7.

[0123] The transmission line model establishing module 1 is used to establish a transmission line model of PCB materials with different energy loss levels by using simulation software.

[0124] The via model establishing module 2 is used to establish via models of PCB materials with different energy loss levels, different via sizes, different effective via lengths, and different via stub lengths by using simulation software.

[0125] The simulation link establishing module 3 is used to build a time-domain and frequency-domain simulation link, and the simulation link is a signal line composed of the transmission line model and the via model.

[0126] The design parameter quantification module 4 is used to obtain the design parameters of the transmission line model and the via model in the simulation link, and variableize and formulate the design parameter variables of the transmission line model and the via model.

[0127] The design parameter setting module 5 is used to set the fixed design parameters of the simulation link according to the SI index of the high-speed signal link and optimize the adjustable design parameters, and set the change range of the optimized adjustable design parameters.

[0128] The simulation result obtaining module 6 is used to run the simulation software to obtain the simulation results that meet the SI index of the high-speed signal link.

[0129] The corresponding relationship table generating module 7 is used to summarize the design parameters of different stack-ups, different PCB materials with different energy loss levels, and different via stub lengths of each item into the PCB interconnection component design system, analyze the corresponding relationship between the signal line length and the via stub length, and form a corresponding relationship table between the signal line length and the via stub length.

[0130] In this embodiment, in the step where the transmission line model establishing module 1 is used to establish a transmission line model of PCB materials with different energy loss levels by using simulation software, it includes:

[0131] Obtain the loss amounts of PCB materials with various energy loss levels;

[0132] Input various energy loss level PCB materials and their corresponding loss amounts into the simulation software;

[0133] Establish a general stack-up structure of the transmission line, and the constituent film layers of the stack-up structure include a signal layer, a dielectric layer, and a reference layer;

[0134] Set the thickness and coordinate values of each layer of the stack-up structure;

[0135] Extract the corresponding transmission line models according to different energy loss level PCB materials and different stack-up structures.

[0136] In this embodiment, in the step of obtaining the loss amounts of PCB materials with various energy loss levels, the obtained PCB materials with various energy loss levels are medium-loss PCB materials, low-loss PCB materials, and ultra-low-loss PCB materials; the line length of the signal line is in inches as the length unit, and for PCB materials with different energy loss levels, their losses per inch are different at different frequency points; the loss amount is the insertion loss data per inch of PCB materials with various energy loss levels at each frequency point; the total insertion loss of each signal line in the transmission line model = insertion loss data per inch * signal line length.

[0137] In this embodiment, the step of using the simulation software to establish via models with different energy loss level PCB materials, different via sizes, different via effective lengths, and different via stub lengths in the via model establishment module 2 includes:

[0138] Obtain the via size and the spacing between two adjacent vias for different energy loss level PCB materials;

[0139] According to the coordinate values of the signal layer in the stack-up structure, obtain the film layer where the via enters and exits the line, and calculate the via effective length in combination with the thickness of each layer of the stack-up structure;

[0140] Obtain the corresponding via stub length according to the via effective length.

[0141] In this embodiment, the step of obtaining the design parameters of the transmission line model and the via model in the simulation link in the design parameter quantification module 4 and variableizing and formulating the design parameters of the transmission line model and the via model includes:

[0142] Establish a back drill depth variable, with 1 mil as the reference, and increase the back drill depth in units of 1 mil to scan the SI characteristics of vias with different via stub lengths;

[0143] Establish ports, and use wave ports at the transmission line;

[0144] Obtain the design parameters in the simulation link, where the design parameters include: various energy loss levels, PCB materials are medium-loss PCB materials, low-loss PCB materials, and ultra-low-loss PCB materials, the thickness and coordinate values of each layer of the stack structure, via hole size, the spacing between two adjacent vias, via hole effective length, via hole stub length, and the number of vias.

[0145] In this embodiment, the design parameter setting module 5 is used to set the fixed design parameters and optimize the adjustable design parameters of the simulation link according to the SI index of the high-speed signal link, and set the variation range of the optimized adjustable design parameters. In the step, the fixed design parameters include the constituent film layers of the stack structure, the thickness of each layer of the stack structure, and the signal line length; the optimized adjustable design parameters include via hole size, the spacing between two adjacent vias, via hole effective length, via hole stub length, the number of vias, reference line length, step line length, insertion loss, impedance, and return loss.

[0146] In this embodiment, when the simulation result acquisition module 6 is used to run the simulation software and obtain the simulation results that meet the SI index of the high-speed signal link, it includes:

[0147] For the medium-loss PCB material, the transmission line is based on 3000 mil, and then steps by 500 mil to scan to 8 inches, plus different via hole stub lengths of the medium-loss PCB material. Through scanning simulation, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different via hole stub lengths of the medium-loss PCB material are obtained;

[0148] For the low-loss PCB material, the transmission line is based on 5000 mil, and then steps by 500 mil to scan to 10 inches, plus different via hole stub lengths of the low-loss PCB material. Through scanning simulation, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different via hole stub lengths of the low-loss PCB material are obtained;

[0149] For the ultra-low-loss PCB material, the transmission line is based on 7000 mil, and then steps by 500 mil to scan to 15 inches, plus different via hole stub lengths of the ultra-low-loss PCB material. Through scanning simulation, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different via hole stub lengths of the ultra-low-loss PCB material are obtained;

[0150] The obtained simulation results include S parameters. The S parameters are subjected to time-domain and frequency-domain analysis in the system to determine the time-domain and frequency-domain margins of the system.

[0151] Among them, the S parameter, that is, the scattering parameter, is an important parameter in microwave transmission.

[0152] In the above signal line length and via stub length matching device 10, by starting from the overall perspective of high-speed signal lines, scanning and analyzing the corresponding relationship between the PCB line length and the via stub length, a general corresponding relationship table of the PCB line length and the via stub length that meets the SI index of the overall high-speed signal link is summarized and formed as interconnection information reserve for quick reference in subsequent project designs, which can improve the project development progress.

[0153] For the specific limitations of the signal line length and via stub length matching device 10, reference can be made to the limitations on the signal line length and via stub length matching method in the above text, which will not be elaborated here. Each module in the above signal line length and via stub length matching device can be implemented in whole or in part by software, hardware, and their combinations. The above modules can be embedded in the processor of the computer device in hardware form or independent of it, or stored in the memory of the computer device in software form to facilitate the processor to call and execute the operations corresponding to the above modules.

[0154] In one embodiment, a computer device is provided. The computer device can be a server, and its internal structure diagram can be as Figure 10 shown. The computer device includes a processor, a memory, a network interface, and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store signal line length and via stub length matching data. The network interface of the computer device is used to communicate with external terminals through a network connection. When the computer program is executed by the processor, it implements a signal line length and via stub length matching method.

[0155] Those skilled in the art can understand that Figure 10 the structure shown in

[0156] is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0157] Use simulation software to establish a transmission line model of PCB materials with different energy loss levels;

[0158] Use simulation software to establish via models with different energy loss levels of PCB materials, different via sizes, different effective via lengths, and different via stub lengths;

[0159] Build a time-domain and frequency-domain simulation link, where the simulation link is a signal line composed of the transmission line model and the via model;

[0160] Obtain the design parameters of the transmission line model and the via model in the simulation link, and parameterize and formulate the design parameters of the transmission line model and the via model;

[0161] Set the fixed design parameters of the simulation link according to the SI index of the high-speed signal link and optimize the adjustable design parameters, and set the variation range of the optimized adjustable design parameters;

[0162] Run the simulation software to obtain simulation results that meet the SI index of the high-speed signal link; and

[0163] Summarize the design parameters of different stack-ups, different energy loss levels of PCB materials, and different via stub lengths of each project into the PCB interconnection component design system, analyze the corresponding relationship between the signal line length and the via stub length, and form a corresponding relationship table between the signal line length and the via stub length.

[0164] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0165] In the step of using simulation software to establish a transmission line model of PCB materials with different energy loss levels, it includes:

[0166] Obtain the loss amounts of PCB materials with various energy loss levels;

[0167] Input various energy loss levels of PCB materials and their corresponding loss amounts into the simulation software;

[0168] Establish a general stack-up structure of the transmission line, and the constituent film layers of the stack-up structure include a signal layer, a dielectric layer, and a reference layer;

[0169] Set the thickness and coordinate values of each layer of the stack-up structure;

[0170] Extract the corresponding transmission line models according to different energy loss levels of PCB materials and different stack-up structures.

[0171] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0172] In the step of obtaining the loss amounts of PCB materials with various energy loss levels, the PCB materials with various energy loss levels obtained are medium-loss PCB materials, low-loss PCB materials, and ultra-low-loss PCB materials; the length of the signal line is in inches as the unit of length, and for PCB materials with different energy loss levels, the loss per inch is different at different frequency points; the loss amount is the insertion loss data per inch of PCB materials with various energy loss levels at each frequency point; the total insertion loss of each signal line in the transmission line model = the insertion loss data per inch * the length of the signal line.

[0173] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0174] The step of using simulation software to establish via models of PCB materials with different energy loss levels, different via sizes, different via effective lengths, and different via stub lengths includes:

[0175] Obtain the via size and the spacing between two adjacent vias for PCB materials with different energy loss levels;

[0176] According to the coordinate values of the signal layer in the stack-up structure, obtain the film layer where the via enters and exits the line, and calculate the via effective length in combination with the thickness of each layer in the stack-up structure;

[0177] Obtain the corresponding via stub length according to the via effective length.

[0178] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0179] The step of obtaining the design parameters of the transmission line model and the via model in the simulation link, and parameterizing and formulating the design parameters of the transmission line model and the via model includes:

[0180] Establish a backdrill depth variable, with 1 mil as the reference, and increase the backdrill depth in units of 1 mil, and scan to obtain the SI characteristics of vias with different via stub lengths;

[0181] Establish ports, and use wave ports at the transmission line;

[0182] Obtain the design parameters in the simulation link, where the design parameters include: the PCB materials with various energy loss levels are medium-loss PCB materials, low-loss PCB materials, and ultra-low-loss PCB materials, the thickness and coordinate values of each layer in the stack-up structure, the via size, the spacing between two adjacent vias, the via effective length, the via stub length, and the number of vias.

[0183] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0184] In the step of setting the fixed design parameters of the simulation link according to the SI index of the high-speed signal link and optimizing the adjustable design parameters, and setting the variation range of the optimized adjustable design parameters, the fixed design parameters include the constituent film layers of the stacked structure, the thickness of each layer of the stacked structure, and the line length of the signal line; the optimized adjustable design parameters include the via size, the spacing between two adjacent vias, the effective length of the via, the stub length of the via, the number of vias, the reference line length, the step line length, the insertion loss, the impedance, and the return loss.

[0185] In one embodiment, when the processor executes the computer program, the following steps are further implemented:

[0186] When running the simulation software to obtain the simulation results that meet the SI index of the high-speed signal link, it includes:

[0187] For the medium-loss PCB material, the transmission line is based on 3000 mil, and then steps by 500 mil until it scans to 8 inches. Adding different stub lengths of the vias in the medium-loss PCB material, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different stub lengths of the vias in the medium-loss PCB material are obtained through scanning simulation;

[0188] For the low-loss PCB material, the transmission line is based on 5000 mil, and then steps by 500 mil until it scans to 10 inches. Adding different stub lengths of the vias in the low-loss PCB material, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different stub lengths of the vias in the low-loss PCB material are obtained through scanning simulation;

[0189] For the ultra-low-loss PCB material, the transmission line is based on 7000 mil, and then steps by 500 mil until it scans to 15 inches. Adding different stub lengths of the vias in the ultra-low-loss PCB material, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different stub lengths of the vias in the ultra-low-loss PCB material are obtained through scanning simulation;

[0190] The obtained simulation results include S parameters. The S parameters are analyzed in the time domain and frequency domain in the system to determine the time-domain and frequency-domain margins of the system.

[0191] For the specific limitations on the steps implemented when the processor executes the computer program, reference can be made to the limitations on the method of matching the signal line length and the stub length of the via in the above text, which will not be elaborated here.

[0192] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented:

[0193] Use the simulation software to establish a transmission line model of PCB materials with different energy loss levels;

[0194] Use simulation software to establish via models with different energy loss levels of PCB materials, different via sizes, different effective via lengths, and different via stub lengths;

[0195] Build a time-domain and frequency-domain simulation link, where the simulation link is a signal line composed of the transmission line model and the via model;

[0196] Obtain the design parameters of the transmission line model and the via model in the simulation link, and parameterize and formulate the design parameters of the transmission line model and the via model;

[0197] Set the fixed design parameters of the simulation link according to the SI indicators of the high-speed signal link and optimize the adjustable design parameters, and set the variation range of the optimized adjustable design parameters;

[0198] Run the simulation software to obtain simulation results that meet the SI indicators of the high-speed signal link; and

[0199] Summarize the design parameters of different stack-ups, different energy loss levels of PCB materials, and different via stub lengths of each project into the PCB interconnect component design system, analyze the corresponding relationship between the signal line length and the via stub length, and form a corresponding relationship table between the signal line length and the via stub length.

[0200] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0201] In the step of using simulation software to establish a transmission line model of PCB materials with different energy loss levels, it includes:

[0202] Obtain the loss amounts of PCB materials with various energy loss levels;

[0203] Input various energy loss levels of PCB materials and their corresponding loss amounts into the simulation software;

[0204] Establish a general stack-up structure of the transmission line, and the constituent film layers of the stack-up structure include a signal layer, a dielectric layer, and a reference layer;

[0205] Set the thickness and coordinate values of each layer of the stack-up structure;

[0206] Extract the corresponding transmission line models according to different energy loss levels of PCB materials and different stack-up structures.

[0207] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0208] In the step of obtaining the loss amounts of PCB materials with various energy loss levels, the PCB materials with various energy loss levels obtained are medium-loss PCB materials, low-loss PCB materials, and ultra-low-loss PCB materials; the length of the signal line is in inches as the length unit, and for PCB materials with different energy loss levels, the loss per inch is different at different frequency points; the loss amount is the insertion loss data per inch of PCB materials with various energy loss levels at each frequency point; the total insertion loss of each signal line in the transmission line model = insertion loss data per inch * signal line length.

[0209] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0210] The step of using simulation software to establish via models of PCB materials with different energy loss levels, different via sizes, different via effective lengths, and different via stub lengths includes:

[0211] Obtain the via size and the spacing between two adjacent vias for PCB materials with different energy loss levels;

[0212] According to the coordinate values of the signal layer in the stack-up structure, obtain the film layer where the via enters and exits the line, and calculate the via effective length in combination with the thickness of each layer in the stack-up structure;

[0213] Obtain the corresponding via stub length according to the via effective length.

[0214] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0215] The step of obtaining the design parameters of the transmission line model and the via model in the simulation link, and parameterizing and formulating the design parameters of the transmission line model and the via model includes:

[0216] Establish a back-drilling depth variable, with 1 mil as the benchmark, and increase the back-drilling depth in units of 1 mil, and scan to obtain the SI characteristics of vias with different via stub lengths;

[0217] Establish ports, and use wave ports at the transmission line;

[0218] Obtain the design parameters in the simulation link, where the design parameters include: the PCB materials with various energy loss levels are medium-loss PCB materials, low-loss PCB materials, and ultra-low-loss PCB materials, the thickness and coordinate values of each layer in the stack-up structure, via size, the spacing between two adjacent vias, via effective length, via stub length, and number of vias.

[0219] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0220] In the step of setting the fixed design parameters of the simulation link and optimizing the adjustable design parameters according to the SI index of the high-speed signal link, and setting the variation range of the optimized adjustable design parameters, the fixed design parameters include the constituent film layers of the stacked structure, the thickness of each layer of the stacked structure, and the signal line length; the optimized adjustable design parameters include the via size, the spacing between two adjacent vias, the effective length of the via, the stub length of the via, the number of vias, the reference line length, the step line length, the insertion loss, the impedance, and the return loss.

[0221] In one embodiment, when the computer program is executed by the processor, the following steps are further implemented:

[0222] When running the simulation software to obtain the simulation results that meet the SI index of the high-speed signal link, it includes:

[0223] For the medium-loss PCB material, the transmission line is based on 3000 mil, and then steps by 500 mil until it scans to 8 inches. Adding the different stub lengths of the vias of the medium-loss PCB material, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different stub lengths of the vias of the medium-loss PCB material are obtained through scanning simulation;

[0224] For the low-loss PCB material, the transmission line is based on 5000 mil, and then steps by 500 mil until it scans to 10 inches. Adding the different stub lengths of the vias of the low-loss PCB material, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different stub lengths of the vias of the low-loss PCB material are obtained through scanning simulation;

[0225] For the ultra-low-loss PCB material, the transmission line is based on 7000 mil, and then steps by 500 mil until it scans to 15 inches. Adding the different stub lengths of the vias of the ultra-low-loss PCB material, the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different stub lengths of the vias of the ultra-low-loss PCB material are obtained through scanning simulation;

[0226] The obtained simulation results include S parameters. The S parameters are analyzed in the time domain and frequency domain in the system to determine the time-domain and frequency-domain margins of the system.

[0227] For the specific limitations on the steps implemented when the computer program is executed by the processor, reference can be made to the limitations on the method of matching the signal line length and the via stub length in the above text, which will not be elaborated here.

[0228] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0229] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0230] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for matching the length of a signal line with the length of a via stub, characterized in that Including: Obtain the design parameters of the transmission line model and the via model in the simulation link, and parameterize and formulate the design parameters of the transmission line model and the via model; Set the fixed design parameters of the simulation link according to the SI index of the high-speed signal link and optimize the adjustable design parameters, and set the change range of the optimized adjustable design parameters; Run the simulation software to obtain the simulation results that meet the SI index of the high-speed signal link; For medium-loss PCB materials, with the transmission line based on 3000 mil and stepped by 500 mil, scan up to 8 inches, and add different via stub lengths of the medium-loss PCB materials. Through scanning simulation, obtain the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different via stub lengths of the medium-loss PCB materials; For low-loss PCB materials, with the transmission line based on 5000 mil and stepped by 500 mil, scan up to 10 inches, and add different via stub lengths of the low-loss PCB materials. Through scanning simulation, obtain the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different via stub lengths of the low-loss PCB materials; For ultra-low-loss PCB materials, with the transmission line based on 7000 mil and stepped by 500 mil, scan up to 15 inches, and add different via stub lengths of the ultra-low-loss PCB materials. Through scanning simulation, obtain the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different via stub lengths of the ultra-low-loss PCB materials; And Summarize the design parameters of different stacks, different energy loss level PCB materials, and different via stub lengths of each project into the PCB interconnect component design system, analyze the corresponding relationship between the signal line length and the via stub length, and form a corresponding relationship table between the signal line length and the via stub length.

2. The method for matching the length of the signal line with the length of the via stub according to claim 1, wherein The method further includes: Use the simulation software to establish a transmission line model of PCB materials with different energy loss levels; Among them, in the step of using the simulation software to establish a transmission line model of PCB materials with different energy loss levels, it includes: Obtain the loss amounts of PCB materials with various energy loss levels; Input the PCB materials with various energy loss levels and their corresponding loss amounts into the simulation software; Establish a general stack structure of the transmission line, and the composed film layers of the stack structure include a signal layer, a dielectric layer, and a reference layer; Set the thickness and coordinate values of each layer of the stack structure; Extract the corresponding transmission line model according to different energy loss level PCB materials and different stack structures.

3. The method for matching the length of a signal line with the length of a via stub according to claim 2, wherein In the step of obtaining the loss amounts of PCB materials with various energy loss levels, the obtained PCB materials with various energy loss levels are medium-loss PCB materials, low-loss PCB materials, and ultra-low-loss PCB materials; the signal line length is in inches as the length unit, and for PCB materials with different energy loss levels, their loss per inch is different at different frequency points; the loss amount is the per-inch insertion loss data of PCB materials with various energy loss levels at each frequency point; the total insertion loss of each signal line in the transmission line model = per-inch insertion loss data * signal line length.

4. The method for matching the length of the signal line with the length of the via stub according to claim 3, wherein The method further includes: Use simulation software to establish via models with different energy loss levels of PCB materials, different via sizes, different via effective lengths, and different via stub lengths; Among them, the steps of using simulation software to establish via models with different energy loss levels of PCB materials, different via sizes, different via effective lengths, and different via stub lengths include: Obtain the via size and the spacing between two adjacent vias for PCB materials with different energy loss levels; According to the coordinate values of the signal layers in the stack-up structure, obtain the film layers where the via inlets and outlets are located, and calculate the via effective length by combining the thicknesses of each layer in the stack-up structure; Obtain the corresponding via stub length based on the via effective length.

5. The method for matching the length of a signal line with the length of a via stub according to claim 4, wherein The steps of obtaining the design parameters of the transmission line model and the via model in the simulation link, and parameterizing and formulating the design parameters of the transmission line model and the via model include: Establish a backdrill depth variable, with 1 mil as the reference, and increase the backdrill depth in units of 1 mil, and scan to obtain the SI characteristics of vias with different via stub lengths; Establish ports, and use wave ports at the transmission line; Obtain the design parameters in the simulation link, where the design parameters include: PCB materials with various energy loss levels are medium-loss PCB materials, low-loss PCB materials, and ultra-low-loss PCB materials, the thicknesses and coordinate values of each layer in the stack-up structure, via size, the spacing between two adjacent vias, via effective length, via stub length, number of vias, and via loss; the via loss = single via loss * number of vias; Add a solution method corresponding to the design parameters, and set the radiation boundary conditions, excitation, and frequency range.

6. The method for matching the length of a signal line with the length of a via stub according to claim 5, wherein In the step of setting the fixed design parameters of the simulation link and optimizing the adjustable design parameters according to the SI indicators of the high-speed signal link, and setting the variation range of the optimized adjustable design parameters, the fixed design parameters include the constituent film layers of the stack-up structure, the thicknesses of each layer in the stack-up structure, and the signal line length; The optimized adjustable design parameters include via size, the spacing between two adjacent vias, via effective length, via stub length, number of vias, reference line length, step line length, insertion loss, impedance, and return loss.

7. The method for matching the length of a signal line with the length of a via stub according to claim 1, wherein The method further includes: Build a time-domain and frequency-domain simulation link, and the simulation link is a signal line composed of the transmission line model and the via model; Among them, when running the simulation software to obtain the simulation results that meet the SI indicators of the high-speed signal link, it further includes: the obtained simulation results include S parameters, and perform time-domain and frequency-domain analysis on the S parameters in the system to determine the time-domain and frequency-domain margins of the system.

8. A device for matching the length of a signal line with the length of a via stub, characterized in that, The device includes: A transmission line model establishment module, which is used to establish a transmission line model of PCB materials with different energy loss levels using simulation software; A via model establishment module, which is used to establish via models with different energy loss levels of PCB materials, different via sizes, different via effective lengths, and different via stub lengths using simulation software; A simulation link establishment module, which is used to build a time-domain and frequency-domain simulation link, and the simulation link is a signal line composed of the transmission line model and the via model; A design parameter quantization module, which is used to obtain the design parameters of the transmission line model and the via model in the simulation link, and variablize and formulate the design parameter variables of the transmission line model and the via model; A design parameter setting module, which is used to set the fixed design parameters of the simulation link and optimize the adjustable design parameters according to the SI index of the high-speed signal link, and set the variation range of the optimized adjustable design parameters; A simulation result acquisition module, which is used to run simulation software to obtain the simulation results that meet the SI index of the high-speed signal link; for medium-loss PCB materials, the transmission line is based on 3000 mil, with a step of 500 mil, scanned to 8 inches, plus different via stub lengths of the medium-loss PCB material, and the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different via stub lengths of the medium-loss PCB material are obtained through scanning simulation; for low-loss PCB materials, the transmission line is based on 5000 mil, with a step of 500 mil, scanned to 10 inches, plus different via stub lengths of the low-loss PCB material, and the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different via stub lengths of the low-loss PCB material are obtained through scanning simulation; for ultra-low-loss PCB materials, the transmission line is based on 7000 mil, with a step of 500 mil, scanned to 15 inches, plus different via stub lengths of the ultra-low-loss PCB material, and the time-domain and frequency-domain simulation results corresponding to different signal line lengths and different via stub lengths of the ultra-low-loss PCB material are obtained through scanning simulation; and A corresponding relationship table generation module, which is used to summarize the design parameters of different laminations, different energy loss level PCB materials, and different via stub lengths of each project into the PCB interconnection component design system, analyze the corresponding relationship between the signal line length and the via stub length, and form a corresponding relationship table between the signal line length and the via stub length.

9. A computer device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, the steps of the method described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps of the method described in any one of claims 1 to 7 are implemented.

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