Process control method for cmp

Abstract

The application discloses a kind of process control methods of CMP, comprising: step one, providing the semiconductor substrate formed with first film layer, first film layer has padA and padB for controlling polishing thickness and respectively has first and second initial thickness value.Step two, simultaneously using padA and padB control thickness after polishing, comprising: step 21, set the target value and upper and lower limit value of the thickness of padA and padB and weight.Step 22, calculate the polishing amount of padA and padB, the upper and lower limit value of polishing amount.Step 23, according to the size relationship of the polishing amount of padA and padB, the upper and lower limit value of polishing amount logical judgment is carried out and according to logical judgment set final polishing amount, final polishing amount ensure that the final thickness value of padA with larger weight is located between first upper and lower limit value and ensure that the final thickness value of padB is located between second upper and lower limit value or deviates limit value minimum.Step 24, according to final polishing amount control CMP.The application can increase the control precision of polishing thickness, improve the stability and quality of product.

Description

TECHNICAL FIELD

[0001] The present application relates to a manufacturing method of a semiconductor integrated circuit, and in particular, to a process control method of chemical mechanical polishing (CMP). BACKGROUND

[0002] 28HK product, i.e. a high dielectric constant metal gate (HKMG) product of 28nm, needs to form a high dielectric constant (HK) gate dielectric layer and a metal gate (MG) at the same time. In the existing HKMG process, a post metal gate process, metal gate loop, and chemical mechanical polishing (CMP) of the first layer of interlayer dielectric (ILD0) are important steps. The thickness control requirement of the ILD0 CMP process after polishing is very high, otherwise it will affect the height of the metal gate and the success of the polysilicon dummy gate etching.

[0003] In actual production, before the ILD0 CMP, a photoresist back etching (PREB) process is included to remove the hard mask layer on the top of the polysilicon dummy gate. Due to the normal fluctuation of the PREB process horn and the height difference of the large and small polysilicon (poly) regions, i.e. the height difference of the dummy poly gates of different sizes, it is difficult to control the polishing of the large and small pads. In the existing method, only one pad is used as a key pad to control the process polishing thickness. The remaining thickness difference of the large and small pads is often large. The thickness of the controlled pad is normal, but the non-controlled pad is often not in the target, occasionally exceeding the control range, resulting in an out of control action plan (OCAP) in the online (inline), and even affecting the subsequent dummy poly remove (DPR) etching process.

[0004] In the post metal gate process, a dummy gate structure, i.e. a dummy gate structure, is usually used to form the gate dielectric layer, channel region, and source-drain region of the device by using the polysilicon dummy gate of the dummy gate structure. Then the metal gate is replaced, which includes removing the polysilicon dummy gate of the dummy gate structure, i.e. DPR, and filling the area where the polysilicon gate of the dummy gate structure is removed with metal to form a metal gate. Before DPR, a hard mask layer (HM) including an oxide layer is formed on the top of the polysilicon gate. Therefore, the oxide layer of the hard mask layer needs to be removed before DPR. The removal process of the hard mask layer usually adopts the PREB process. The PREB process is before the ILD0 deposition process, and the DPR process is after the ILD0 CMP.

[0005] The PREB process is mainly to avoid damage to other regions such as active regions in the process of removing the oxide layer of the hard mask layer of the polysilicon gate in the 28nm HKMG process. A photolithography is used to protect other regions. The general process is as follows: first, a large block of polysilicon gate photoresist is opened by a photolithography, and then the remaining photoresist (PR) on the polysilicon gate is also opened by a PR etch back (EB) process, i.e. EB1, which is mainly to overcome the PR loading on the large block of polysilicon gate. At this time, all the poly has been opened, and a second etch back process, i.e. EB2, is performed to remove the oxide layer of the hard mask layer. The existing PREB process method will be described in detail in combination with the accompanying drawings, as shown in Figures 1A-1C The existing gate manufacturing method includes the following steps:

[0006] Step one, as shown in Figure 1A A semiconductor substrate 101 is provided, and a gate dielectric layer 103 and a polysilicon gate 104 are formed on the surface of the semiconductor substrate 101 in sequence. The polysilicon gate 104 here is a polysilicon dummy gate, which needs to be removed later.

[0007] The semiconductor substrate 101 is a silicon substrate.

[0008] The gate dielectric layer 103 includes a high dielectric constant layer, and an interface layer is also provided between the high dielectric constant layer and the semiconductor substrate 101.

[0009] The semiconductor substrate 101 has a field oxide layer 102 formed therein, and the active region is isolated by the field oxide layer 102; the active region includes the active region of the core region and the active region of the input / output (IO) region.

[0010] The field oxide layer 102 is a shallow trench field oxide, which is formed by a shallow trench isolation process.

[0011] The width of the polysilicon gate 104 includes multiple types, and the width of the polysilicon gate 104 in the active region outside the core region is greater than the width of the polysilicon gate 104 in the active region in the core region.

[0012] The existing gate structure, i.e. the corresponding component of the metal gate formed later, includes a core component and an input / output component, which are located in the core region and outside the core region, respectively.

[0013] The component is a field effect transistor.

[0014] The components include an n-type field-effect transistor (FET), i.e., an nFET, and a p-type field-effect transistor, i.e., a pFET.

[0015] Step Two, as follows Figure 1A As shown, a hard mask layer is formed on the surface of the polysilicon gate 104; the hard mask layer is formed by stacking a first nitride layer 105 and a second oxide layer 106.

[0016] Step 3, as follows Figure 1A As shown, multiple pseudo-gate structures are formed by photolithography etching. Each pseudo-gate structure is formed by stacking the etched gate dielectric layer 103, the polysilicon gate 104, and the hard mask layer. After etching, the width of the polysilicon gate 104 includes two widths.

[0017] Step 4, as follows Figure 1A As shown, sidewalls 108 are formed on the side of each of the pseudo-gate structures.

[0018] The material of the sidewall 108 includes a nitrided layer. Figure 1A In this context, the sidewall 108 also includes an oxide layer.

[0019] Step 5, as follows Figure 1A As shown, the source and drain regions of the device are formed in the active regions on both sides of the pseudo-gate structure.

[0020] The process of forming the source and drain regions of the component includes a component enhancement process.

[0021] The component enhancement process includes a germanium-silicon process. The component enhancement process forms a germanium-silicon layer 107 in the source or drain region of the p-type field-effect transistor.

[0022] The component enhancement process will cause uneven gate structure height in each region, that is, uneven height of the superimposed structure of gate dielectric layer 103, polysilicon gate 104, first nitride layer 105 and second oxide layer 106.

[0023] After the source region and the drain region are formed, the step of forming a nitride layer 109 is further included. The nitride layer 109 is typically used as a CESL layer.

[0024] The above are the steps before performing the PREB process.

[0025] Step 6: Remove the second oxide layer 106 from the hard mask layer. In existing methods, the PREB process is used to remove the second oxide layer 106, specifically as follows:

[0026] like Figure 1A As shown, a photolithography process is performed to form a photoresist pattern 201, and the open area 202 of the photoresist pattern 201 corresponds to the top area of ​​the larger polysilicon gate 104.

[0027] As shown in Figure 1B , then, the photoresist is etched back, and the photoresist pattern 201 after etching back exposes the surface of the second oxide layer 106.

[0028] As shown in Figure 1C , the second oxide layer 106 is usually removed by dry etching, and the photoresist pattern 201 is used to protect the area between the polysilicon gates 104 during etching.

[0029] As shown in Figure 1C , it can be seen that after the second oxide layer 106 is removed, the horn 203 composed of the protruding part of the side wall 108 is formed. The height of the horn 203 in different areas is different, which will adversely affect the control of the subsequent ILD0 CMP.

[0030] Then the photoresist pattern 201 is removed.

[0031] To solve the problem of large difference in the remaining thickness of the pad in the existing ILD0 CMP, the following is described in combination with the drawings: as shown in Figure 2 , it is a schematic diagram of the pad in the existing ILD0 CMP; Figure 2 In the semiconductor substrate 301, a gate structure 302 is formed, which is usually composed of a gate dielectric layer and a polysilicon dummy gate, Figure 2 In the semiconductor substrate 301, a gate structure 302 is formed, which is usually composed of a gate dielectric layer and a polysilicon dummy gate, Figure 1C As shown in

[0032] A side wall 303 is formed on the side of the gate structure 302, and two source / drain regions 304 are formed on both sides of the gate structure 302 in self-alignment, and a channel region 305 is located between the two source / drain regions 304 and covered by the gate structure 302.

[0033] The zeroth layer of interlayer film 306 will fill the space between the gate structures 302 and extend above the top surface of the gate structure 302.

[0034] In the metal gate replacement process, the gate structure 302 needs to be removed first, so the zeroth layer of interlayer film 306 needs to be subjected to CMP, i.e. ILD0 CMP, so that the top surface of the gate structure 302 is exposed.

[0035] As shown in Figure 2As shown, the zero layer interlayer film 306 includes pads, namely pad A and pad B, as indicated by marks 307 and 308, respectively, and the pad A and pad B are of different sizes, and after CMP, the two pads A and pad B have a thickness difference. In the prior art, only one pad is used to control the thickness of CMP, that is, when the pad A reaches the target thickness, the pad B can have a large difference from the target thickness, which can affect the stability and quality of the product process. SUMMARY

[0036] The technical problem to be solved by the present application is to provide a CMP process control method, which can increase the control accuracy of the polishing thickness, reduce the differences between different areas of the film layer, and thus improve the stability and quality of the product.

[0037] To solve the above technical problems, the CMP process control method provided by the present application comprises the following steps:

[0038] Step one, providing a semiconductor substrate, a first film layer needing to be subjected to CMP is formed on the semiconductor substrate, and the first film layer has two pads for controlling the polishing thickness, which are pad A and pad B, respectively, the pad A and the pad B are of different sizes, the pad A has a first initial thickness value, and the pad B has a second initial thickness value.

[0039] Step two, simultaneously using the pad A and the pad B to control the thickness after polishing, comprising the following sub-steps:

[0040] Step 21, setting a first target value, a first upper limit value and a first lower limit value of the thickness of the pad A.

[0041] Setting a second target value, a second upper limit value and a second lower limit value of the thickness of the pad B.

[0042] Setting a first weight of the pad A and a second weight of the pad B, and the first weight is greater than or equal to the second weight.

[0043] Step 22, calculating a first polishing amount, a first polishing amount upper limit value and a first polishing amount lower limit value of the pad A, the first polishing amount being the first initial thickness value minus the first target value, the first polishing amount upper limit value being the first initial thickness value minus the first lower limit value, and the first polishing amount lower limit value being the first initial thickness value minus the first upper limit value.

[0044] calculating a second polishing amount of the padB, a second polishing amount upper limit value and a second polishing amount lower limit value, the second polishing amount being the second initial thickness value minus the second target value, the second polishing amount upper limit value being the second initial thickness value minus the second upper limit value, the second polishing amount lower limit value being the second initial thickness value minus the second lower limit value.

[0045] Step 23, making a logical judgment according to the size relationship of the first polishing amount, the first polishing amount upper limit value, the first polishing amount lower limit value, the second polishing amount, the second polishing amount upper limit value and the second polishing amount lower limit value, setting a final polishing amount according to the logical judgment, the final polishing amount ensuring that the first final thickness value of the padA with a larger first weight is between the first upper limit value and the first lower limit value and ensuring that the second final thickness value of the padB is between the second upper limit value and the second lower limit value or ensuring that the deviation value of the second final thickness value of the padB deviating from the second upper limit value or the second lower limit value is minimum.

[0046] Step 24, controlling the CMP according to the final polishing amount.

[0047] Further improvement is that in step 23, the logical judgment includes:

[0048] If the first polishing amount is greater than the second polishing amount lower limit value and the first polishing amount is less than the second polishing amount upper limit value, the final polishing amount is set to the first polishing amount multiplied by the first weight plus the second polishing amount multiplied by the second weight.

[0049] Further improvement is that in step 23, the logical judgment includes:

[0050] If the first polishing amount is greater than or equal to the second polishing amount upper limit value and the first polishing amount lower limit value is less than the second polishing amount upper limit value, the final polishing amount is set to the second polishing amount upper limit value multiplied by the first weight plus the first polishing amount lower limit value multiplied by the second weight.

[0051] Further improvement is that in step 23, the logical judgment includes:

[0052] If the first polishing amount lower limit value is greater than or equal to the second polishing amount upper limit value, the final polishing amount is set to the first polishing amount lower limit value.

[0053] Further improvement is that in step 23, the logical judgment includes:

[0054] If the first polishing amount is less than the second polishing amount lower limit value and the second polishing amount lower limit value is less than the first polishing amount upper limit value, the final polishing amount is set as the second polishing amount lower limit value multiplied by the first weight plus the first polishing amount upper limit value multiplied by the second weight.

[0055] Further improvement is that in step 23, the logic judgment includes:

[0056] If the first polishing amount upper limit value is less than or equal to the second polishing amount lower limit value, the final polishing amount is set as the first polishing amount upper limit value.

[0057] Further improvement is that in step 24, the CMP is controlled by a polishing time, and the polishing time is equal to the final polishing amount divided by a polishing rate.

[0058] Further improvement is that the polishing time is controlled by an in-line advanced process control (iAPC).

[0059] Further improvement is that in step one, the semiconductor substrate includes a silicon substrate.

[0060] Further improvement is that the first film layer is a zero layer interlayer film.

[0061] Further improvement is that the first film layer is filled between gate structures and extends onto top surfaces of the gate structures, and the gate structures have different widths.

[0062] Further improvement is that the gate structure includes a gate dielectric layer and a polysilicon dummy gate which are sequentially stacked.

[0063] After step 24 is completed, a top surface of the polysilicon dummy gate is exposed.

[0064] Further improvement is that after step 24 is completed, a step of removing the polysilicon dummy gate is further included.

[0065] Different from existing single-pad control of polishing thickness, the present application simultaneously controls polishing thicknesses of two pads, and through logic judgment and weighted superposition of polishing thicknesses according to the logic judgment, an optimal final polishing amount can be obtained, the first final thickness value of pad A with a larger weight is ensured to be between the first upper limit value and the first lower limit value, and the second final thickness value of pad B with a smaller weight is ensured to be between the second upper limit value and the second lower limit value, and when the second final thickness value exceeds the range of the second upper limit value and the second lower limit value, a deviation value of the second final thickness value is minimized, so the present application can increase control precision of polishing thickness, reduce differences between different regions of a film layer, and thus improve product stability and product quality. BRIEF DESCRIPTION OF DRAWINGS

[0066] The application will be described in further detail below with reference to the drawings and specific embodiments:

[0067] As Figures 1A-1C shown, is the device structure diagram in each step of the existing PREB process method;

[0068] Figure 2 is the schematic diagram of the size pad in the existing ILD0 CMP;

[0069] Figure 3 is the flow chart of the process control method of the embodiment CMP of the application. Embodiment

[0070] As Figure 3 shown, is the flow chart of the process control method of the embodiment CMP of the application, the device schematic diagram in the embodiment method of the application also please refer to Figure 2 shown, the process control method of the embodiment CMP of the application includes the following steps:

[0071] Step one, providing a semiconductor substrate 301, a first film layer needing to be subjected to CMP is formed on the semiconductor substrate 301, the first film layer has two kinds of pads for controlling the polishing thickness, the two kinds of pads are padA and padB respectively, the padA and the padB are different in size, the padA has a first initial thickness value, and the padB has a second initial thickness value.

[0072] In the embodiment of the application, the semiconductor substrate 301 includes a silicon substrate.

[0073] The first film layer is a zeroth layer interlayer film 306.

[0074] The first film layer is filled between the gate structures 302 and extends to the top surface of the gate structures 302, and the gate structures 302 have different widths.

[0075] The gate structure 302 includes a gate dielectric layer and a polysilicon dummy gate which are sequentially superimposed;

[0076] The side walls 303 are formed on the side surfaces of the gate structures 302, and two source / drain regions 304 are formed on the two sides of the gate structures 302 respectively, and the channel region 305 is located between the two source / drain regions 304 and is covered by the gate structure 302.

[0077] As Figure 2 shown, the zeroth layer interlayer film 306 includes the padA shown by the mark 307 and the padB shown by the mark 308, and the padA and the padB are different in size.

[0078] Step two, controlling the thickness after grinding by using the padA and the padB simultaneously, including the following sub-steps:

[0079] Step 21, setting a first target value, a first upper limit value and a first lower limit value of the thickness of the padA.

[0080] Setting a second target value, a second upper limit value and a second lower limit value of the thickness of the padB.

[0081] Setting a first weight of the padA and a second weight of the padB; the first weight is greater than or equal to the second weight.

[0082] Step 22, calculating a first grinding amount, a first grinding amount upper limit value and a first grinding amount lower limit value of the padA, the first grinding amount being the first initial thickness value minus the first target value, the first grinding amount upper limit value being the first initial thickness value minus the first lower limit value, and the first grinding amount lower limit value being the first initial thickness value minus the first upper limit value.

[0083] The formula corresponding to the first grinding amount, the first grinding amount upper limit value and the first grinding amount lower limit value of the padA is:

[0084] RA_A=THK_A–Target_A (1);

[0085] Max_RA_A=THK_A–Min_Target_A (2);

[0086] Min_RA_A=THK_A–Max_Target_A (3);

[0087] Wherein, THK_A represents the first initial thickness value, Target_A represents the first target value, Min_Target_A represents the first lower limit value, Max_Target_A represents the first upper limit value, RA_A represents the first grinding amount, Max_RA_A represents the first grinding amount upper limit value, and Min_RA_A represents the first grinding amount lower limit value.

[0088] Calculating a second grinding amount, a second grinding amount upper limit value and a second grinding amount lower limit value of the padB, the second grinding amount being the second initial thickness value minus the second target value, the second grinding amount upper limit value being the second initial thickness value minus the second lower limit value, and the second grinding amount lower limit value being the second initial thickness value minus the second upper limit value.

[0089] RA_B=THK_B–Target_B (4);

[0090] Max_RA_B=THK_B–Min_Target_B (5);

[0091] Min_RA_B=THK_B–Max_Targret_B (6);

[0092] Wherein, THK_B represents the second initial thickness value, Target_B represents the second target value, Min_Target_B represents the second lower limit value, Max_Target_B represents the second upper limit value, RA_B represents the second polishing amount, Max_RA_B represents the second polishing amount upper limit value, and Min_RA_B represents the second polishing amount lower limit value.

[0093] Step 23, logical judgment is performed according to the size relationship of the first polishing amount, the first polishing amount upper limit value, the first polishing amount lower limit value, the second polishing amount, the second polishing amount upper limit value and the second polishing amount lower limit value, and a final polishing amount is set according to the logical judgment, the final polishing amount ensures that the first final thickness value of the pad A with a larger first weight is located between the first upper limit value and the first lower limit value and ensures that the second final thickness value of the pad B is located between the second upper limit value and the second lower limit value or ensures that the second final thickness value of the pad B deviates from the second upper limit value or the second lower limit value by a minimum deviation value.

[0094] In the embodiment of the application, the logical judgment comprises:

[0095] If the first polishing amount is greater than the second polishing amount lower limit value and the first polishing amount is less than the second polishing amount upper limit value, the final polishing amount is set as the first polishing amount multiplied by the first weight plus the second polishing amount multiplied by the second weight. At this time, the logical judgment can be expressed as:

[0096] If Min_RA_B<RA_A<Max_RA_B;

[0097] RA=RA_A*A%+RA_B*B% (7) 。

[0098] Wherein, RA represents the final polishing amount, A% represents the first weight, and B% represents the second weight. RA_A*A% can ensure that the first final thickness value is located between the first upper limit value and the first lower limit value after CMP is performed according to RA; and since Min_RA_B<RA_A<Max_RA_B, the second final thickness value is also ensured to be located between the second upper limit value and the second lower limit value after CMP is performed according to RA.

[0099] In the embodiment of the application, the logical judgment comprises:

[0100] If RA_A ≥ Max_RA_B and Min_RA_A < Max_RA_B, the final polishing amount is set as the second polishing amount upper limit value multiplied by the first weight plus the first polishing amount lower limit value multiplied by the second weight.

[0101] At this time, the logical judgment can be expressed as:

[0102] If RA_A ≥ Max_RA_B and Min_RA_A < Max_RA_B.

[0103] RA= Max_RA_B *A%+ Min_RA_A *B% (8)。

[0104] Where Max_RA_B is replaced by RA_A as the coefficient of weight A%, which can eliminate the adverse effect of larger RA_A on the second final thickness value of padB, and make the second final thickness value less than the second upper limit value, i.e. Max_RA_B. On the contrary, if RA_A is still used as the coefficient of weight A%, the value of RA_A*A% is larger, so that the second final thickness value is easy to exceed the limit of Max_RA_B.

[0105] Min_RA_A is replaced by RA_B as the coefficient of weight B%, which can ensure that the first final thickness value is above the first lower limit value, i.e. Min_RA_A.

[0106] In the embodiment of the application, the logical judgment comprises:

[0107] If the first polishing amount lower limit value is greater than or equal to the second polishing amount upper limit value, the final polishing amount is set as the first polishing amount lower limit value. At this time, the logical judgment can be expressed as:

[0108] If Min_RA_A ≥ Max_RA_B.

[0109] RA= Min_RA_A (9)。

[0110] After RA takes Min_RA_A, it can ensure that the first final thickness value is Min_RA_A, so as to ensure the safety of the main padA.

[0111] Since Min_RA_A is the minimum value that can be taken to ensure the safety of padA, and the difference between Min_RA_A and Max_RA_B is the minimum compared with RA_A, after the auxiliary padB adopts RA for CMP, although the second final thickness value will exceed Max_RA_B, the deviation value from Max_RA_B can be ensured to be the minimum.

[0112] In the embodiment of the application, the logical judgment comprises:

[0113] If the first polishing amount is less than the second polishing lower limit value and the second polishing lower limit value is less than the first polishing upper limit value, the final polishing amount is set as the second polishing lower limit value multiplied by the first weight plus the first polishing upper limit value multiplied by the second weight.

[0114] If RA_A<Min_RA_B<Max_RA_A;

[0115] RA= Min_RA_B*A%+ Max_RA_A*B% (10)。

[0116] Min_RA_B is used to replace RA_A as the coefficient of the weight A%, and since Min_RA_B<Max_RA_A, after the replacement, the first final thickness value will be located in the range defined by the first upper and lower limit values, that is, between Min_RA_A and Max_RA_A; at the same time, since RA_A<Min_RA_B, the defect that the second final thickness value will be less than Min_RA_B when RA_A is adopted can be prevented, so that the second final thickness value is also located in the range defined by the second upper and lower limit values.

[0117] In the embodiment of the application, the logical judgment comprises:

[0118] If the first polishing upper limit value is less than or equal to the second polishing lower limit value, the final polishing amount is set as the first polishing upper limit value.

[0119] If Max_RA_A≤Min_RA_B;

[0120] RA= Max_RA_A (11)。

[0121] After RA takes Max_RA_A, the first final thickness value can be ensured to be Max_RA_A, so that the safety of the main padA can be ensured.

[0122] Since Max_RA_A≤Min_RA_B, Max_RA_A is the maximum value that can be taken to ensure the safety of padA, and the difference between Max_RA_A and Min_RA_B is the minimum compared with RA_A, so after padB uses RA for CMP, although the second final thickness value will be less than Min_RA_B, the deviation value of the second final thickness value and Min_RA_B can be ensured to be the minimum.

[0123] Step 24, controlling the CMP according to the final polishing amount.

[0124] In the embodiment of the present application, the CMP is controlled by the polishing time, and the polishing time is equal to the final polishing amount divided by the polishing rate, and the corresponding formula is:

[0125] PT=RA / RR (12).

[0126] Wherein, PT is the polishing time, and RR is the polishing rate.

[0127] In some preferred embodiments, the polishing time is controlled by iAPC.

[0128] After step 24 is completed, the top surface of the polysilicon dummy gate is exposed.

[0129] After step 24 is completed, a step of removing the polysilicon dummy gate is further included.

[0130] Different from the existing single-pad control of polishing thickness, the embodiment of the present application simultaneously controls the polishing thickness of two pads, and the optimal final polishing amount can be obtained by logical judgment and weighted superposition of polishing thickness according to the logical judgment, the first final thickness value of padA with greater weight is located between the first upper limit value and the first lower limit value, and the second final thickness value of padB with smaller weight is located between the second upper limit value and the second lower limit value, and the deviation value of the second final thickness value is minimized when the second final thickness value exceeds the range of the second upper limit value and the second lower limit value, so the embodiment of the present application can increase the control accuracy of the polishing thickness, reduce the difference between different regions of the film layer, and thus improve the stability and product quality of the product.

[0131] The present application has been described in detail by specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can make many modifications and improvements without departing from the principles of the present application, and these should also be considered as falling within the scope of protection of the present application.

Claims

1. A CMP process control method, characterized in that, Includes the following steps: Step 1: Provide a semiconductor substrate, and form a first film layer on the semiconductor substrate for CMP. The first film layer has two pads for controlling the grinding thickness, namely pad A and pad B. The pads A and B are different in size. Pad A has a first initial thickness value and pad B has a second initial thickness value. Step 2: Simultaneously use pad A and pad B to control the thickness after grinding, including the following sub-steps: Step 21: Set the first target value, the first upper limit value, and the first lower limit value of the thickness of pad A; Set a second target value, a second upper limit value, and a second lower limit value for the thickness of the pad B; Set the first weight of padA and the second weight of padB; The first weight is greater than or equal to the second weight; Step 22: Calculate the first grinding amount, the upper limit of the first grinding amount, and the lower limit of the first grinding amount for pad A. The first grinding amount is the first initial thickness value minus the first target value. The upper limit of the first grinding amount is the first initial thickness value minus the first lower limit. The lower limit of the first grinding amount is the first initial thickness value minus the first upper limit. Calculate the second grinding amount, the upper limit of the second grinding amount, and the lower limit of the second grinding amount for the pad B. The second grinding amount is the second initial thickness value minus the second target value. The upper limit of the second grinding amount is the second initial thickness value minus the second lower limit. The lower limit of the second grinding amount is the second initial thickness value minus the second upper limit. Step 23: Perform a logical judgment based on the relationship between the first grinding amount, the upper limit of the first grinding amount, the lower limit of the first grinding amount, the second grinding amount, the upper limit of the second grinding amount, and the lower limit of the second grinding amount, and set the final grinding amount according to the logical judgment. The final grinding amount ensures that the first final thickness value of pad A, which has a larger first weight, is between the first upper limit and the first lower limit, and ensures that the second final thickness value of pad B is between the second upper limit and the second lower limit, or ensures that the deviation of the second final thickness value of pad B from the second upper limit or the second lower limit is minimized. Step 24: Control the CMP according to the final grinding amount.

2. The CMP process control method as described in claim 1, characterized in that: In step 23, the logical judgment includes: If the first grinding amount is greater than the lower limit of the second grinding amount and the first grinding amount is less than the upper limit of the second grinding amount, then the final grinding amount is set as the first grinding amount multiplied by the first weight plus the second grinding amount multiplied by the second weight.

3. The CMP process control method as described in claim 1, characterized in that: In step 23, the logical judgment includes: If the first grinding amount is greater than or equal to the upper limit of the second grinding amount and the lower limit of the first grinding amount is less than the upper limit of the second grinding amount, then the final grinding amount is set as the upper limit of the second grinding amount multiplied by the first weight plus the lower limit of the first grinding amount multiplied by the second weight.

4. The CMP process control method as described in claim 1, characterized in that: In step 23, the logical judgment includes: If the first lower limit of the grinding amount is greater than or equal to the second upper limit of the grinding amount, then the final grinding amount is set to the first lower limit of the grinding amount.

5. The CMP process control method as described in claim 1, characterized in that: In step 23, the logical judgment includes: If the first grinding amount is less than the second grinding amount lower limit and the second grinding amount lower limit is less than the first grinding amount upper limit, then the final grinding amount is set as the second grinding amount lower limit multiplied by the first weight plus the first grinding amount upper limit multiplied by the second weight.

6. The CMP process control method as described in claim 1, characterized in that: In step 23, the logical judgment includes: If the first grinding amount upper limit is less than or equal to the second grinding amount lower limit, then the final grinding amount is set to the first grinding amount upper limit.

7. The CMP process control method according to any one of claims 1 to 6, characterized in that: In step 24, the CMP is controlled by the grinding time, which is equal to the final grinding amount divided by the grinding rate.

8. The CMP process control method as described in claim 7, characterized in that: The grinding time is controlled by iAPC.

9. The CMP process control method as described in claim 7, characterized in that: In step one, the semiconductor substrate includes a silicon substrate.

10. The CMP process control method as described in claim 9, characterized in that: The first film layer is the zeroth interlayer film.

11. The CMP process control method as described in claim 10, characterized in that: The first film layer fills the space between the gate structures and extends to the top surface of the gate structures, which have different widths.

12. The CMP process control method as described in claim 11, characterized in that: The gate structure includes a gate dielectric layer and a polysilicon dummy gate stacked sequentially. After step 24 is completed, the top surface of the polysilicon pseudo gate is exposed.

13. The CMP process control method as described in claim 12, characterized in that: After step 24 is completed, the process also includes the step of removing the polysilicon pseudo-gate.

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