Method for improving wafer dicing performance and wafer structure

Abstract

The application provides a method for improving wafer cutting performance and a wafer structure. A trench is formed on a semiconductor substrate of the wafer by etching, and at least one epitaxial layer is formed on the surface of the trench by an epitaxial process, so that the opening of the trench is closed and a middle space gap structure is formed. The middle space gap structure is embedded in the semiconductor substrate, and is located in a cutting channel formed between adjacent semiconductor chips on the wafer. When the wafer is cut, the middle space gap structure arranged corresponding to the cutting gap guides the wafer to crack along the middle space gap structure. The middle space gap structure arranged around the semiconductor chip prevents the crack of the wafer from extending into the semiconductor chip, thereby improving the wafer cutting performance, reducing the cutting defects, being compatible with the process flow of the existing FSI and BSI image sensor chips, and greatly improving the cutting yield under the condition of considering the cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method and wafer structure for improving wafer dicing performance. Background Technology

[0002] In the integrated circuit manufacturing process, multiple semiconductor chips are formed on the same wafer. There are dicing channels between adjacent semiconductor chips. In the wafer dicing process, the chips are cut along the dicing channels to form individual semiconductor chips.

[0003] For example, in existing front-side illumination (FSI) or back-side illumination (BSI) image sensor (CMOS Image Sensor, CIS) processes, an epitaxial layer formed on a semiconductor substrate of a device wafer is typically used as the device layer. After forming semiconductor devices such as photodiodes in the device layer, a dielectric layer and multiple metal layers located in the dielectric layer are formed on the device layer. Then, optical structures such as filter layers and microlenses are formed on the front or back of the device wafer, thereby forming multiple front-side illumination or back-side illumination image sensor chips on the device wafer. Adjacent image sensor chips have cleaving channels. Finally, the device wafer is cut into individual chips by means of laser cleaving or mechanical cutting.

[0004] However, the mechanical forces and stresses during wafer dicing can cause micro-cracks and delamination at the chip edges, and the depth and width of these cracks affect the overall yield of the dicing process. To protect the internal areas of the chip and avoid defects such as delamination and serpentine surfaces caused by the characteristics of the dielectric layer film in the dicing path (e.g., typically a Low-k dielectric film with a low dielectric constant), the usual approach is to optimize the wafer dicing process, which often involves significant process difficulty and high cost. Summary of the Invention

[0005] The purpose of this invention is to provide a method and wafer structure for improving wafer dicing performance, reducing abnormal phenomena such as cross-sectional delamination and serpentine patterns, reducing process difficulty, and improving wafer dicing yield.

[0006] To address the aforementioned technical problems, one aspect of the present invention provides a method for improving wafer dicing performance, comprising: the wafer including a semiconductor substrate; etching the semiconductor substrate to form trenches; forming at least one epitaxial layer on the surface of the trenches through an epitaxial process to close the trench openings and form a mid-space gap structure; forming a plurality of semiconductor chips on the wafer, wherein the mid-space gap structure is located in the dicing channels between adjacent semiconductor chips.

[0007] Preferably, when the wafer is cut, a space gap structure corresponding to the cut guides the wafer to split along the space gap structure.

[0008] Preferably, when the wafer is cut, a space gap structure surrounding the semiconductor chip prevents cracks in the wafer from extending into the semiconductor chip.

[0009] Preferably, the etching of the semiconductor substrate to form trenches, and the formation of at least one epitaxial layer on the surface of the trenches through an epitaxial process to close the trench openings and form a gap structure includes: etching the semiconductor substrate to form a plurality of first trenches; lateral etching to connect the bottoms of the plurality of first trenches to form a second trench; and forming at least one epitaxial layer through at least one epitaxial process to close the tops of the first trenches and form a cavity in the second trench.

[0010] Preferably, the etching of the semiconductor substrate to form a plurality of first trenches includes: etching the semiconductor substrate to form a plurality of third trenches according to a preset photolithography pattern; forming a dielectric layer on the surface of the third trenches to protect the sidewalls of the third trenches; and continuing to etch the bottom of the third trenches to deepen the third trenches and form the first trenches.

[0011] Preferably, the width of the second groove is greater than the width of the first groove.

[0012] Preferably, the intermediate space gap structure is arranged continuously or discontinuously along the length direction of the cutting channel.

[0013] Preferably, the width of the intermediate space gap structure occupies part or all of the width of the cutting channel.

[0014] Another aspect of the present invention provides a wafer structure for improving wafer dicing performance, the wafer including a semiconductor substrate; a mid-space gap structure is embedded in the semiconductor substrate, the mid-space gap structure being located in the dicing path between adjacent semiconductor chips subsequently formed on the wafer.

[0015] Preferably, the space gap structure is configured to correspond to the cut, and is used to guide the wafer to split along the space gap structure.

[0016] Preferably, the spacer structure is arranged around the semiconductor chip to prevent cracks in the wafer from extending into the semiconductor chip.

[0017] Preferably, the intermediate space gap structure is arranged continuously or discontinuously along the length direction of the cutting channel.

[0018] Preferably, the width of the intermediate space gap structure occupies part or all of the width of the cutting channel.

[0019] The present invention relates to a method and wafer structure for improving wafer dicing performance. This method involves etching a semiconductor substrate of the wafer to form trenches, and then forming at least one epitaxial layer on the surface of the trenches using an epitaxial process. This closes the trench openings, forming a space gap structure. This creates a space gap structure embedded in the semiconductor substrate. The space gap structure is located in the dicing path between adjacent semiconductor chips subsequently formed on the wafer. During wafer dicing, the space gap structure, corresponding to the dicing cut, guides the wafer to cleave along the space gap structure. The space gap structure surrounding the semiconductor chip prevents cracks from extending into the semiconductor chip, thereby improving wafer dicing performance, reducing dicing defects, and ensuring compatibility with existing FSI and BSI image sensor chip processes. This significantly improves dicing yield while considering cost. Attached Figure Description

[0020] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.

[0021] Figure 1 This is a partial schematic diagram of a wafer structure according to an embodiment of the present invention;

[0022] Figures 2-6 This is a schematic diagram illustrating the formation process of the interstitial gap structure.

[0023] Figures 7-8 This is a schematic diagram of the layout of the first trench.

[0024] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation

[0025] To address the problems in the prior art, the present invention provides a method and wafer structure for improving wafer dicing performance.

[0026] In the following detailed description of preferred embodiments, reference will be made to the accompanying drawings, which form part of this invention. The accompanying drawings illustrate specific embodiments by way of example that enable the implementation of the invention. The exemplary embodiments are not intended to be exhaustive of all embodiments according to the invention. It will be understood that other embodiments may be utilized, and structural or logical modifications may be made, without departing from the scope of the invention. Therefore, the following detailed description is not restrictive, and the scope of the invention is defined by the appended claims.

[0027] Figure 1A partial schematic diagram of a wafer structure according to an embodiment of the present invention is shown. The wafer 10 includes a semiconductor substrate 100, in which intermediate space gap structures 400a and 400b are embedded. These intermediate space gap structures 400a and 400b are located in cleaving channels between adjacent semiconductor chips (e.g., FSI or BSI image sensor chips) 300a, 300b, 300c, and 300d subsequently formed on the wafer 10.

[0028] When along the laser concealed cutting or mechanical cutting methods Figure 1 When the wafer 10 is diced along the dotted line, the space gap structure 400a corresponding to the cut (dotted line area) guides the wafer 10 to cleave along the space gap structure 400a. The space gap structure 400b surrounding the semiconductor chips 300a, 300b, 300c, and 300d prevents the cracks of the wafer 10 from extending into the semiconductor chips 300a, 300b, 300c, and 300d, thereby reducing abnormal phenomena such as cross-sectional delamination and serpentine patterns, improving wafer dicing performance, reducing dicing defects, and being compatible with the existing process flow of FSI and BSI image sensor chips. While taking cost into consideration, it greatly improves the dicing yield.

[0029] In this embodiment, the simultaneous existence and separation of the intermediate space gap structure 400a corresponding to the cut and the intermediate space gap structure 400b surrounding the semiconductor chip is merely an example; in other embodiments not shown, the intermediate space gap structure 400a or 400b may also exist alone or be joined together adjacent to each other.

[0030] In a further preferred embodiment, the intermediate space gap structures 400a and 400b can be set continuously or discontinuously along the length of the cutting track, and the width of the intermediate space gap structures 400a and 400b can occupy part or all of the width of the cutting track. The specific selection is made according to the process requirements to ensure that the technical effect of reducing cutting defects and improving cutting yield is better.

[0031] Figures 2-6 for Figure 1 A cross-sectional view of region A along line BB, taking the central gap structure 400b as an example (the formation process of 400a is the same), illustrates the formation process of the central gap structure in one embodiment of the present invention, specifically including the following steps:

[0032] Step S1: As Figures 2-3 As shown, the semiconductor substrate 100 is etched to form a plurality of first trenches 110;

[0033] In an optional embodiment, the plurality of first grooves 110 have the same line width and length and are arranged in a rectangular array; the specific arrangement is not limited in this invention. Figure 7 ,Figure 8 The diagram illustrates possible arrangements of multiple first trenches 110 in different embodiments of the present invention. The specific settings, such as the number, line width, and spacing of the first trenches 110, can be selected according to process requirements. Preferred line widths and spacings of the first trenches 110 are as follows: the line width a of the first trench 110 is between 0.1 μm and 1 μm; the spacing b of the first trench is greater than 50 nm and less than 2 μm.

[0034] Preferably, such as Figure 3 As shown, the semiconductor substrate 100 has a hard mask layer 101 on its surface. A first trench 110 can be formed by etching the hard mask layer 101 and the semiconductor substrate 100 using a preset photolithography pattern. The hard mask layer 101 may include one or more of oxides, nitrides, and oxide oxynitrides, and the present invention is not limited thereto.

[0035] Preferably, in step S1, a plurality of first trenches 110 can be formed by the following steps:

[0036] Step S11: As Figure 2 As shown, according to the preset photolithography pattern, the semiconductor substrate 100 is etched to form a plurality of third trenches 130;

[0037] Step S12: A dielectric layer (e.g., an oxide film) 131 is formed on the surface of the third trench. The oxide film 131 can protect the sidewalls of the third trench 130 and ensure that the trench linewidth is not too large during further etching.

[0038] Step S13: Continue etching the bottom of the third trench 130 to deepen the third trench 130, forming a first trench 110 that is not interconnected, such as... Figure 3 As shown.

[0039] Preferably, when etching the semiconductor substrate 100 to form a plurality of third trenches 130, negative angle etching can be used so that the opening linewidth of the third trench 130 is smaller than the bottom linewidth.

[0040] Step S2: As Figure 4 As shown, by lateral etching, the bottoms of several first trenches 110 are interconnected to form a second trench 120, the second trench 120 being wider than the first trenches 110.

[0041] Step S3: As Figure 5 As shown, an epitaxial layer 111 is formed through at least one epitaxial process, which closes the top of the first trench 110 and forms a cavity 121 in the second trench 120, thus forming a mid-space gap structure.

[0042] Through the above steps, the present invention forms a mid-space gap structure with a small upper opening linewidth and multiple "cantilever beams" connecting the bottoms of the two semiconductor substrates. This mid-space gap structure can be etched into a small opening using existing masks with small linewidths, and because the bottom trench is relatively wide, it can effectively reduce abnormal phenomena such as cross-sectional delamination and serpentine patterns, improve wafer cutting performance, and reduce cutting defects.

[0043] Those skilled in the art will understand that, in other embodiments not shown in this invention, after etching the semiconductor substrate 100 to form the first trench 110, step S2 can be omitted, and at least one epitaxial layer 111 can be directly formed on the surface of the first trench 110 through an epitaxial process, so that the top of the first trench 110 is closed and a cavity is formed in the lower part of the first trench 110, thereby forming a mid-space gap structure. However, due to the limitations of existing etching and epitaxial process conditions, the width of the first trench 110 to which this method is applicable is greatly limited, because if the opening of the first trench 110 is wide, it is difficult to achieve the process of closing the first trench 110 to form a cavity through epitaxy.

[0044] Preferably, in one embodiment, forming a cavity 121 in the second trench 120 in step S3 can be further achieved through the following steps:

[0045] Step S31: A dielectric layer 122 is formed on the surface of the second trench 120 to close the top of the first trench 110 and form a cavity 121 in the second trench 120;

[0046] Step S32: Etch the top of the dielectric layer 122 to open the dielectric layer 122 at the top of the first trench 110;

[0047] Step S33: Perform at least one epitaxial process on the surface of the first trench 110 to form an epitaxial layer 111, thereby closing the top of the first trench 110 and re-forming a cavity 121 in the second trench 120.

[0048] Furthermore, in one embodiment, after forming the cavity 121 in the second trench 120 in step S3, the back side of the semiconductor substrate 100 can be thinned.

[0049] In one embodiment, the epitaxial layer 111 includes a first sub-epitaxy layer 112 and a second sub-epitaxy layer 113, and the epitaxial layer 111 can be formed in step S33 in the following manner:

[0050] Step S331: Epitaxial intrinsic semiconductors are formed on the surfaces of the first trench 110 and the second trench 120 to form the first sub-epitaxy layer 112;

[0051] Step S332: Epitaxially grow semiconductor material on the surface of the first sub-epitaxial layer 112 to form the second sub-epitaxial layer 113. Preferably, the doping type of the second sub-epitaxial layer 113 is opposite to that of the semiconductor substrate 100. If the semiconductor substrate 100 is P-type doped, the second sub-epitaxial layer 113 is N-type doped; if the semiconductor substrate 100 is N-type doped, the second sub-epitaxial layer 113 is P-type doped.

[0052] Furthermore, after the spatial gap structure is formed in step S3, the following steps can be performed:

[0053] Step S41: The surface of the semiconductor substrate 100 is planarized;

[0054] Step S42: As Figure 6 As shown, a device layer 200 is epitaxially formed on the surface of the semiconductor substrate 100.

[0055] Subsequently, using conventional FSI or BSI image sensor processes, semiconductor devices such as photodiodes are formed in device layer 200. Then, a dielectric layer and multiple metal layers within the dielectric layer are formed on device layer 200. Next, optical structures such as filter layers and microlenses are formed on the front or back side of the wafer, thereby forming multiple front-illuminated or back-illuminated image sensor chips on wafer 10. Here, four image sensor chips 300a, 300b, 300c, and 300d are shown. Adjacent image sensor chips 300a, 300b, 300c, and 300d are separated by cleaving channels. Pre-embedded mid-space gap structures 400a and 400b in the semiconductor substrate 100 are located within these cleaving channels. Figure 1 As shown.

[0056] Therefore, when wafer 10 is cut by means of laser slicing or mechanical cutting, the intermediate space gap structure 400a corresponding to the cut guides wafer 10 to crack along the intermediate space gap structure 400a. The intermediate space gap structure 400b surrounding semiconductor chips 300a, 300b, 300c, and 300d prevents the cracks of wafer 10 from extending into the semiconductor chips 300a, 300b, 300c, and 300d, thereby reducing abnormal phenomena such as cross-section delamination and serpentine patterns, improving wafer cutting performance, reducing cutting defects, and being compatible with the existing process flow of FSI and BSI image sensor chips. While taking cost into consideration, the cutting yield is greatly improved.

[0057] In summary, the method and wafer structure for improving wafer dicing performance of the present invention form trenches by etching the semiconductor substrate of the wafer, and then forming at least one epitaxial layer on the surface of the trenches through an epitaxial process, thereby closing the trench openings and forming a mid-space gap structure. This results in a mid-space gap structure being pre-embedded in the semiconductor substrate. The mid-space gap structure is located in the dicing path between adjacent semiconductor chips subsequently formed on the wafer. When dicing the wafer, the mid-space gap structure corresponding to the dicing cut guides the wafer to cleave along the mid-space gap structure. The mid-space gap structure surrounding the semiconductor chip prevents the cracks from extending into the semiconductor chip, thereby improving wafer dicing performance, reducing dicing defects, and being compatible with existing FSI and BSI image sensor chip process flows. While considering cost, it significantly improves dicing yield.

[0058] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plural. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for improving wafer dicing performance, characterized in that, include: The wafer includes a semiconductor substrate; According to a preset photolithography pattern, the semiconductor substrate is etched to form multiple third trenches; A dielectric layer is formed on the surface of the third trench to protect the sidewalls of the third trench; Continue etching the bottom of the third trench to deepen the third trench, forming multiple first trenches; By lateral etching, the bottoms of several first trenches are interconnected to form a second trench; At least one epitaxial layer is formed by at least one epitaxial process, so that the top of the first trench is closed and a cavity is formed in the second trench, thereby pre-embedding a mid-space gap structure in the semiconductor substrate; Multiple semiconductor chips are formed on the wafer, and the space gap structure is located in the dicing channel between adjacent semiconductor chips.

2. The method for improving wafer dicing performance as described in claim 1, characterized in that, When the wafer is cut, a space gap structure corresponding to the cut guides the wafer to split along the space gap structure.

3. The method for improving wafer dicing performance as described in claim 1, characterized in that, When the wafer is cut, a space gap structure surrounding the semiconductor chip prevents cracks in the wafer from extending into the semiconductor chip.

4. The method for improving wafer dicing performance as described in claim 1, characterized in that, The width of the second groove is greater than the width of the first groove.

5. The method for improving wafer dicing performance as described in claim 1, characterized in that, The space gap structure is arranged continuously or discontinuously along the length of the cutting channel.

6. The method for improving wafer dicing performance as described in claim 1, characterized in that, The width of the space gap structure occupies part or all of the width of the cutting channel.

7. A wafer structure for improving wafer dicing performance, characterized in that, The wafer includes a semiconductor substrate; According to a preset photolithography pattern, the semiconductor substrate is etched to form multiple third trenches; A dielectric layer is formed on the surface of the third trench to protect the sidewalls of the third trench; Continue etching the bottom of the third trench to deepen the third trench, forming multiple first trenches; By lateral etching, the bottoms of several first trenches are interconnected to form a second trench; At least one epitaxial layer is formed by at least one epitaxial process to close the top of the first trench and form a cavity in the second trench, thereby pre-embedding a mid-space gap structure in the semiconductor substrate, the mid-space gap structure being located in the dicing channel between adjacent semiconductor chips subsequently formed on the wafer.

8. The wafer structure for improving wafer dicing performance as described in claim 7, characterized in that, The space gap structure is configured to correspond to the notch, and is used to guide the wafer to split along the space gap structure.

9. The wafer structure for improving wafer dicing performance as described in claim 7, characterized in that, The space gap structure is arranged around the semiconductor chip to prevent cracks in the wafer from extending into the semiconductor chip.

10. The wafer structure for improving wafer dicing performance as described in claim 7, characterized in that, The space gap structure is arranged continuously or discontinuously along the length of the cutting channel.

11. The wafer structure for improving wafer dicing performance as described in claim 7, characterized in that, The width of the space gap structure occupies part or all of the width of the cutting channel.

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