Fabrication method and structure of a germanium-silicon HBT emitter-base region

Abstract

The application provides a manufacturing method and structure of a germanium-silicon HBT emitter-base structure, and the method comprises the following steps: providing a base region stack; providing an oxide sacrificial layer on the base region stack and manufacturing a contact hole penetrating through the oxide sacrificial layer; sequentially forming a nitride protective layer, an oxide protective layer and an emitter region at the contact hole of the oxide sacrificial layer, wherein the emitter region is in contact with the base region stack through the contact hole, the nitride protective layer and the oxide protective layer form a wrapping structure wrapping the top and side of the emitter region, and the top of the emitter region is the side of the emitter region facing away from the base region stack; and removing the oxide sacrificial layer and the nitride sacrificial layer to form an outer base region on the side of the base region stack where the emitter region is arranged. The application breaks through the limitation of photolithography precision and reduces the size of the emitter region.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit manufacturing, and in particular to a manufacturing method and structure of a germanium-silicon HBT emitter-base region structure. BACKGROUND

[0002] The germanium-silicon HBT (heterojunction bipolar transistor) can be integrated with a silicon CMOS (Complementary Metal-Oxide-Semiconductor Transistor) integrated circuit on a large scale, and has excellent frequency characteristics and noise characteristics. The germanium-silicon HBT uses germanium-silicon material as a base region, and the silicon / germanium-silicon heterojunction emitter junction formed thereby can obtain a larger injection efficiency; the heterojunction base region can be heavily doped, thereby greatly relieving the Early effect, the large injection Webster effect, and the Kirk effect, and reducing the base series resistance, and the obtained device has the advantages of high characteristic frequency, low noise, and high linearity. In the current non-selective germanium-silicon epitaxy and raised base region manufacturing process, a nitride sacrificial layer is generally used as a deposition window for raising the outer base region, and in order to ensure that the silicon oxide side wall is not etched completely, the etching time of the oxide needs to be accurately controlled in the wet etching, and the robustness of this process is poor. SUMMARY

[0003] In view of the problems existing in the prior art, the present application provides a manufacturing method and structure of a germanium-silicon HBT emitter-base region structure, which mainly solves the problem of high etching time control precision requirement and poor process robustness in the existing etching process.

[0004] In order to achieve the above-mentioned purpose and other purposes, the technical scheme adopted by the present application is as follows.

[0005] The present application provides a manufacturing method of a germanium-silicon HBT emitter-base region structure, comprising:

[0006] providing a base region stack;

[0007] forming an oxide sacrificial layer on the base region stack, and forming a contact hole penetrating through the oxide sacrificial layer;

[0008] forming a nitride protective layer, an oxide protective layer, and an emitter region in the contact hole of the oxide sacrificial layer in sequence, wherein the emitter region is in contact with the base region stack through the contact hole, the nitride protective layer and the oxide protective layer form a wrapping structure wrapping the top and side of the emitter region, and the top of the emitter region is a side of the emitter region facing away from the base region stack;

[0009] The oxide sacrificial layer and the nitride sacrificial layer are removed to form an outer base region on the side of the base region stack where the emitter region is provided.

[0010] In an embodiment of the present application, the oxide sacrificial layer has a thickness between 200 angstroms and 1200 angstroms.

[0011] In an embodiment of the present application, a nitride protection layer, an oxide protection layer and an emitter region are sequentially formed at the contact hole of the oxide sacrificial layer, comprising:

[0012] A first nitride sub-layer and a first oxide sub-layer are sequentially formed on the side of the oxide sacrificial layer away from the base region stack;

[0013] A first nitride side wall and a first oxide side wall are sequentially formed on the sidewall of the contact hole, wherein the first nitride side wall is connected to the first nitride sub-layer and the first oxide side wall is connected to the first oxide sub-layer;

[0014] The emitter region is formed on the basis of the first oxide side wall;

[0015] A second oxide sub-layer and a second nitride sub-layer are sequentially formed on the top of the emitter region;

[0016] The second nitride sub-layer, the second oxide sub-layer, the emitter region, the first oxide sub-layer and the first nitride sub-layer are sequentially etched along the circumferential direction of the contact hole;

[0017] A second oxide side wall and a second nitride side wall are sequentially formed on the side of the emitter region away from the emitter region, wherein the first oxide sub-layer, the first oxide side wall, the second oxide sub-layer and the second oxide side wall are connected to form the oxide protection layer, and the first nitride sub-layer, the first nitride side wall, the second nitride sub-layer and the second nitride side wall are connected to form the nitride protection layer.

[0018] In an embodiment of the present application, a first nitride side wall and a first oxide side wall are sequentially formed on the sidewall of the contact hole, comprising:

[0019] Nitride is deposited at the contact hole, and the nitride is etched to form the first nitride side wall, wherein the etched thickness is greater than the thickness of the nitride deposited on the sidewall of the contact hole, so that the first nitride side wall is connected to the first nitride sub-layer in an arc shape;

[0020] Oxide is deposited at the contact hole, and the oxide is etched to form the first oxide side wall, wherein the etched thickness is greater than the thickness of the oxide deposited on the first nitride side wall, so that the first oxide side wall is connected to the first oxide sub-layer in an arc shape.

[0021] In an embodiment of the present application, the first oxide sub-layer, the first nitride sub-layer, the first oxide side wall and the first nitride side wall each have a thickness between 200 angstroms and 600 angstroms.

[0022] In an embodiment of the present application, the emitter region is in-situ doped, and has a doping concentration between 5e 19 and 2e 20 cm -3 and a thickness between 1000 angstroms and 2500 angstroms.

[0023] In an embodiment of the present application, the second oxide side wall has a thickness between 50 angstroms and 200 angstroms, and the second nitride side wall has a thickness between 100 angstroms and 300 angstroms.

[0024] In an embodiment of the present application, the second oxide sub-layer and the second nitride sub-layer each have a thickness between 100 angstroms and 400 angstroms.

[0025] The present application also provides a GeSi HBT emitter-base structure, comprising:

[0026] a base region stack;

[0027] an emitter region extending outward from the base region stack;

[0028] an oxide protective layer extending outward from the base region stack and wrapping the emitter region;

[0029] an outer base region disposed on a side of the oxide protective layer facing away from the emitter region and in contact with the base region stack.

[0030] In an embodiment of the present application, the emitter region has a smaller diameter on a side closer to the base region stack than on a side farther from the base region stack, and the connection between the two sides has an arc shape.

[0031] As described above, the present application provides a method for manufacturing a GeSi HBT emitter-base structure and the structure itself, which has the following advantages.

[0032] The present application can better control the etching process through the oxide sacrificial layer and the nitride protective layer, further breaking through the limitation of photolithography precision to reduce the size of the emitter region, and has a low requirement for the control of etching time, which is conducive to improving the yield of finished products. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 FIG. 1 is a flowchart of a method for manufacturing a GeSi HBT emitter-base structure according to an embodiment of the present application.

[0034] Figure 2Structure diagram of a base region stack in an embodiment of the present application.

[0035] Figure 3 Structure diagram of a stack with an oxide sacrificial layer in an embodiment of the present application.

[0036] Figure 4 Structure diagram of depositing a first nitride sidewall in a contact hole in an embodiment of the present application.

[0037] Figure 5 Structure diagram of depositing a first oxide sidewall in a contact hole in an embodiment of the present application.

[0038] Figure 6 Structure diagram of a stack with an emitter region in an embodiment of the present application.

[0039] Figure 7 Structure diagram of a stack with a second oxide sublayer and a second nitride sublayer in an embodiment of the present application.

[0040] Figure 8 Structure diagram of a stack after etching away part of the emitter region in an embodiment of the present application.

[0041] Figure 9 Structure diagram of a stack with a second oxide sidewall and a second nitride sidewall in an embodiment of the present application.

[0042] Figure 10 Structure diagram of a stack after removing the oxide sacrificial layer in an embodiment of the present application.

[0043] Figure 11 Structure diagram of a stack after removing the nitride protective layer in an embodiment of the present application.

[0044] Figure 12 Structure diagram of a stack with an outer base region in an embodiment of the present application.

[0045] BRIEF DESCRIPTION OF DRAWINGS

[0046] 101 - base region stack, 201 - oxide sacrificial layer, 202 - first nitride sublayer, 203 - first oxide sublayer, 301 - first nitride sidewall, 401 - first oxide sidewall, 501 - emitter region, 502 - second oxide sublayer, 503 - second nitride sublayer, 601 - second oxide sidewall, 602 - second nitride sidewall, 701 - outer base region. DETAILED DESCRIPTION

[0047] Following make the embodiments of the present application specific, specific examples can be easily understood by those skilled in the art from the disclosure of the present application, the advantages and effects of the present application. The present application can also be implemented or applied by means of different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0048] It should be noted that the diagrams provided in the following examples only illustrate the basic concept of the present application in a schematic manner, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be a random change, and the component layout pattern may be more complex.

[0049] Please refer to Figure 1 , the present application provides a method for manufacturing a germanium-silicon HBT emitter-base structure, which comprises the following steps:

[0050] Step S100, providing a base region stack 101;

[0051] Step S110, providing an oxide sacrificial layer 201 on the base region stack 101, and forming a contact hole through the oxide sacrificial layer 201;

[0052] Step S120, sequentially forming a nitride protective layer, an oxide protective layer and an emitter region 501 at the contact hole of the oxide sacrificial layer 201, wherein the emitter region 501 is in contact with the base region stack 101 through the contact hole, and the nitride protective layer and the oxide protective layer form a wrapping structure wrapping the top and side of the emitter region 501, the top of the emitter region 501 being the side of the emitter region 501 away from the base region stack 101;

[0053] Step S130, removing the oxide sacrificial layer 201 and the nitride sacrificial layer, and forming an outer base region 701 on the side of the base region stack 101 where the emitter region 501 is provided.

[0054] Please refer to Figure 2 , Figure 2 is a structural schematic diagram of the base region stack 101 in an embodiment of the present application. In step S100, the base region stack 101 can be obtained by depositing Si / SiGe / Si base region on the substrate, which can be used as a silicon buffer layer, a germanium-silicon cap layer or a silicon cap layer.

[0055] Please refer to Figure 3 , Figure 3The stack structure with the oxide sacrificial layer 201 is shown in an embodiment of the present application. In step S110, the oxide sacrificial layer 201 is formed on the base region stack 101, and a contact hole is formed through the oxide sacrificial layer 201 by the following steps:

[0056] First, the oxide sacrificial layer 201 is deposited on the base region stack 101, and the first nitride sub-layer 202 and the first oxide sub-layer 203 are sequentially deposited on the side of the oxide sacrificial layer 201 away from the base region stack 101.

[0057] The contact hole is formed through the oxide sacrificial layer 201 by a photolithography process. The contact hole sequentially penetrates the first oxide sub-layer 203, the first nitride sub-layer 202, and the oxide sacrificial layer 201. The contact hole is used to form the emission region 501, and the emission region 501 can contact the base region stack 101 through the contact hole.

[0058] In an embodiment, the thickness of the oxide sacrificial layer 201 can be set to 200 angstroms to 1200 angstroms.

[0059] In an embodiment, the thickness of the first oxide sub-layer 203 and the first nitride sub-layer 202 can be set to 200 angstroms to 600 angstroms.

[0060] In step S120, the nitride protective layer, the oxide protective layer, and the emission region 501 are sequentially formed at the contact hole of the oxide sacrificial layer 201, including the following steps:

[0061] Step S121, the first nitride sub-layer 202 and the first oxide sub-layer 203 are sequentially formed on the side of the oxide sacrificial layer 201 away from the base region stack 101. Based on the stack structure of the oxide sacrificial layer 201, the first nitride sub-layer 202, and the first oxide sub-layer 203, a contact hole is formed by a photolithography process.

[0062] Step S122, the first nitride side wall 301 and the first oxide side wall 401 are sequentially formed on the sidewall of the contact hole. The first nitride side wall 301 is connected to the first nitride sub-layer 202, and the first oxide side wall 401 is connected to the first oxide sub-layer 203. Specifically, please refer to Figure 4 and Figure 5 , Figure 4 The structure diagram of the first nitride side wall 301 deposited in the contact hole in an embodiment of the present application is shown. Figure 5Figure 6 is a schematic diagram of a structure in which a first oxide sidewall 401 is deposited in a contact hole in an embodiment of the present application. Nitride is deposited in the contact hole by chemical vapor deposition, and the nitride and the base region stack 101 are etched by an etching process, leaving only the nitride on the sidewall of the contact hole as a first nitride sidewall 301. During the etching process, the etching depth can be greater than the thickness of the deposited nitride, so that the first nitride sidewall 301 is connected to the first nitride sublayer 202 in an arc shape. The thickness of the first nitride sidewall 301 can be set to be between 200 and 600 angstroms. Further, oxide can be deposited on the first nitride sidewall 301, and an etching process is performed to form the first oxide sidewall 401 as shown in Figure 7. During the etching of the deposited oxide, the etching depth can be set to be greater than the thickness of the deposited oxide, so that the first oxide sidewall 401 is connected to the first oxide sublayer 203 in an arc shape. The thickness of the first oxide sidewall 401 can also be set to be between 200 and 600 angstroms. Figure 5

[0063] Step S123, forming the emitter region 501 on the basis of the first oxide sidewall 401. Please refer to Figure 8. Figure 6 Figure 6 Figure 9 is a schematic diagram of a stack structure in which the emitter region 501 is provided in an embodiment of the present application. After the first oxide sidewall 401 is completed, single crystal silicon or polycrystalline silicon is deposited as the emitter region 501 on the basis of the obtained stack structure. The doping concentration of the emitter region 501 can be set to be between 5e 19 and 2e 20 cm -3 . The thickness of the emitter region 501 can be set to be between 1000 angstroms and 2500 angstroms.

[0064] Step S124, sequentially forming a second oxide sublayer 502 and a second nitride sublayer 503 on the top of the emitter region 501. Please refer to Figure 10. Figure 7 Figure 7 Figure 11 is a schematic diagram of a stack structure in which the second oxide sublayer 502 and the second nitride sublayer 503 are provided in an embodiment of the present application. The second oxide sublayer 502 and the second nitride sublayer 503 can be sequentially deposited on the side of the emitter region 501 away from the base region stack 101. The thickness of the second oxide sublayer 502 and the second nitride sublayer 503 can both be set to be between 100 angstroms and 400 angstroms.

[0065] Step S125, sequentially etching the second nitride sublayer 503, the second oxide sublayer 502, the emitter region 501, the first oxide sublayer 203, and the first nitride sublayer 202 in the circumferential direction of the contact hole. Please refer to Figure 12. Figure 8 Figure 8 ​​​​Figure 6 is a schematic diagram of a stack structure after etching part of the emission region 501 in an embodiment of the present application. Part of the region can be etched from the outermost oxide sacrificial layer 201 in the direction of the contact hole, leaving only the first nitride sub-layer 202, the first oxide sub-layer 203, the emission region 501, the second oxide sub-layer 502 and the second nitride sub-layer 503 near the contact hole, and exposing the side surface of the emission region 501.

[0066] Step S126, a second oxide side wall 601 and a second nitride side wall 602 are formed successively outward from the emission region 501 on the side surface of the emission region 501, wherein the first oxide sub-layer 203, the first oxide side wall 401, the second oxide sub-layer 502 and the second oxide side wall 601 form the oxide protective layer in communication, and the first nitride sub-layer 202, the first nitride side wall 301, the second nitride sub-layer 503 and the second nitride side wall 602 form the nitride protective layer in communication. Please refer to Figure 9 Figure 9 Figure 7 is a schematic diagram of a stack structure provided with the second oxide side wall 601 and the second nitride side wall 602 in an embodiment of the present application. Specifically, the second oxide side wall 601 on the side surface of the emission region 501 can be formed by oxidation, and the thickness of the second oxide side wall 601 can be set between 50 angstroms and 200 angstroms. Further, the nitride can be deposited on the side of the second oxide side wall 601 away from the emission region 501, and the second nitride side wall 602 can be formed by etching. The thickness of the third dilute side wall can be set between 100 angstroms and 300 angstroms.

[0067] Please refer to Figure 10 Figure 10 Figure 8 is a schematic diagram of a stack structure after removing the oxide sacrificial layer 201 in an embodiment of the present application. In step S130, the oxide sacrificial layer 201 can be etched by physical etching, and the side surface of the emission region 501 is not etched due to the blocking of the nitride protective layer, so the requirement for the control of the physical etching time is lower.

[0068] Please refer to Figure 11 Figure 11 Figure 9 is a schematic diagram of a stack structure after removing the nitride protective layer in an embodiment of the present application. The nitride protective layer can be removed by wet etching, i.e. Figure 11 the first nitride sub-layer 202, the first nitride side wall 301, the second nitride sub-layer 503 and the second nitride side wall 602 in Figure 6. Since there is the oxide protective layer, the possibility of shorting the emission region 501 and the outer base region 701 in the subsequent process can be effectively avoided.

[0069] Please refer to Figure 12 Figure 12 ​​​​A schematic diagram of the stack structure with the outer base region 701 is shown in an embodiment of the present application. After etching away the nitride protective layer, the original oxide sacrificial layer 201 is used as a window to form the outer base region 701 by chemical vapor deposition.

[0070] In an embodiment, the oxide in the foregoing steps can include silicon oxide, and the nitride can include silicon nitride. Of course, other materials can be used for the oxide and the nitride according to actual production needs, which are not limited herein.

[0071] Based on the above technical solutions, the process of the emitter-base structure of the germanium-silicon HBT of the present application uses the oxide sacrificial layer 201 and the nitride protective layer to better control the process of wet etching, further break through the limitation of the lithography precision to reduce the size of the emitter region 501, and has low requirements for the time control of the wet etching, which is beneficial to improve the yield.

[0072] Please refer to Figure 12 The present application also provides a germanium-silicon HBT emitter-base structure, which includes a base region stack 101; an emitter region 501 extending outward from the base region stack 101; an oxide protective layer extending outward from the base region stack 101 and wrapping the emitter region 501; and an outer base region 701 arranged on the side of the oxide protective layer away from the emitter region 501 and in contact with the base region stack 101. The oxide protective layer includes a first oxide sub-layer 203, a first oxide sidewall 401, a second oxide sub-layer 502, and a second oxide sidewall 601.

[0073] In an embodiment, the diameter of the circumscribed circle of the emitter region 501 near one side of the base region stack 101 is smaller than the diameter of the circumscribed circle of the emitter region 501 far from the base region stack 101, and the connection between the two sides with different diameters is an arc-shaped connection.

[0074] The above embodiments are only illustrative of the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A method for manufacturing a silicon-germanium HBT emitter-base structure, characterized in that: include: providing a base region stack; forming an oxide sacrificial layer on the base region stack and making a contact hole through the oxide sacrificial layer; A nitride protective layer, an oxide protective layer, and an emitter region are sequentially formed at the contact hole of the oxide sacrificial layer, wherein the emitter region contacts the base region stack through the contact hole, and the nitride protective layer and the oxide protective layer form a wrapping structure wrapping the top and side surfaces of the emitter region, wherein the top of the emitter region is the side of the emitter region facing away from the base region stack; the thickness of the oxide sacrificial layer is between 200 angstroms and 1200 angstroms; the nitride protective layer, the oxide protective layer, and the emitter region are sequentially formed at the contact hole of the oxide sacrificial layer, including: sequentially forming a first nitride sublayer and a first oxide sublayer on the side of the oxide sacrificial layer facing away from the base region stack; A first nitride sidewall and a first oxide sidewall are sequentially formed on the sidewall of the contact hole, wherein the first nitride sidewall is connected to the first nitride sublayer, and the first oxide sidewall is connected to the first oxide sublayer; the emitter region is formed on the basis of the first oxide sidewall; a second oxide sublayer and a second nitride sublayer are sequentially formed on the top of the emitter region; the second nitride sublayer, the second oxide sublayer, the emitter region, the first oxide sublayer and a partial area of ​​the first nitride sublayer along the circumference of the contact hole are sequentially etched; a second oxide sidewall and a second nitride sidewall are sequentially formed on the side of the emitter region from the emitter region outward, wherein the first oxide sublayer, the first oxide sidewall, the second oxide sublayer and the second oxide sidewall are connected to form the oxide protective layer, and the first nitride sublayer, the first nitride sidewall, the second nitride sublayer and the second nitride sidewall are connected to form the nitride protective layer The oxide sacrificial layer and the nitride protection layer are removed, and an external base region is formed on a side of the base region stack where the emitter region is disposed.

2. The method for manufacturing the SiGe HBT emitter-base structure according to claim 1, wherein: Sequentially forming a first nitride sidewall spacer and a first oxide sidewall spacer on the sidewall of the contact hole, comprising: Depositing nitride at the contact hole, and etching the nitride to form the first nitride sidewall spacer, wherein the etching thickness is greater than the thickness of the nitride deposited on the sidewall of the contact hole, so that the first nitride sidewall spacer is connected to the first nitride sub-layer in an arc shape; Oxide is deposited at the contact hole and etched to form the first oxide sidewall spacer, wherein the etching thickness is greater than the thickness of the oxide deposited on the first nitride sidewall spacer, so that the first oxide sidewall spacer forms an arc connection with the first oxide sublayer.

3. The method for manufacturing the emitter-base structure of a silicon-germanium HBT according to claim 2, characterized in that: The thickness of the first oxide sub-layer, the first nitride sub-layer, the first oxide spacer, and the first nitride spacer are all between 200 angstroms and 600 angstroms.

4. The method for manufacturing the emitter-base structure of a silicon-germanium HBT according to claim 1, characterized in that: The emitter region is in-situ doped with a doping concentration of 5e 19 to 2e 20 cm -3 The thickness of the emission region is between 1000 angstroms and 2500 angstroms.

5. The method for manufacturing the SiGe HBT emitter-base structure according to claim 1, wherein: The thickness of the second oxide sidewall spacer is between 50 and 200 angstroms, and the thickness of the second nitride sidewall spacer is between 100 and 300 angstroms.

6. The method for manufacturing the SiGe HBT emitter-base structure according to claim 1, wherein: The thickness of the second oxide sub-layer and the second nitride sub-layer are both between 100 angstroms and 400 angstroms.

7. A silicon-germanium HBT emitter-base structure, characterized in that: The SiGe HBT emitter-base structure is prepared by the method for manufacturing the SiGe HBT emitter-base structure according to any one of claims 1 to 6, comprising: Base stack; an emitter region extending outward from the base region stack; an oxide protection layer extending outward from the base region stack and wrapping the emitter region; An external base region is provided on a side of the oxide protection layer away from the emitter region and in contact with the base region stack; The diameter of the circumscribed circle of the emitter region close to the base region stack is smaller than the diameter of the circumscribed circle of the emitter region away from the base region stack, and the connection between the sides with different diameters is an arc connection.

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