A MOSFET drive circuit for power management

Abstract

The application belongs to the field of integrated circuits, and particularly relates to a MOSFET driving circuit for power management, comprising a Vref_LS internal power module, a buffer module, a first inverter group, an nmos acceleration circuit, an nmos tube N1, a Vref_HS internal power module, a level shift module, a second inverter group, a pmos acceleration circuit and a pmos tube P1; the nmos acceleration circuit and the pmos acceleration circuit are introduced on the basis of a conventional MOSFET driving circuit, the opening speed of the nmos tube N1 and the transient stability speed of the Vref_LS internal power module are accelerated through the nmos acceleration circuit, the opening speed of the pmos tube P1 and the transient stability speed of the Vref_HS internal power module are accelerated through the pmos acceleration circuit, and the driving effect of the MOSFET driving circuit is improved.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and in particular relates to a MOSFET driving circuit for power management. Background Art

[0002] MOSFET driver circuits are widely used in power management circuits to achieve switching between logic level signals and power signals. Power management circuits are widely used, and most power management circuits require built-in or external MOSFETs.

[0003] Figure 1 It is a commonly used MOSFET drive circuit, including: low-side drive part and high-side drive part;

[0004] The low-side driver includes: a Vref_LS internal power supply module, a buffer module, inverters INV1 to INV3, and an NMOS transistor N1. The Vref_LS internal power supply module provides power to the buffer module, inverters INV1 to INV3, and NMOS transistor N1. The buffer module receives an external square wave signal, shapes the square wave signal, and outputs it to the inverter INV1 and level shift module. Inverters INV1 to INV3 gradually amplify the shaped signal output by the buffer module to turn on / off the NMOS transistor N1.

[0005] The high-side driver part includes: Vref_HS internal power supply module, level shift module, inverters INV4~INV6 and pmos tube P1; Vref_HS internal power supply module provides power supply for the level shift module, inverters INV4~INV6 and pmos tube P1; the level shift module converts the output signal of the buffer module into Vref_HS~Vdd; inverters INV4~INV6 gradually amplify the level shift output signal to realize the opening / closing of the output stage pmos tube P1.

[0006] Figure 1During normal operation of the conventional MOSFET driver circuit shown, pMOS transistor P1 is turned on and off by INV6. When the gate input of INV6 is low, pMOS transistor P3 of INV6 turns on and nmos transistor N3 turns off, pulling the gate of pMOS transistor P1 up to Vdd through pMOS transistor P3, turning pMOS transistor P1 off. When the gate input of INV6 is high, pMOS transistor P3 of INV6 turns off and nmos transistor N3 turns on, pulling the gate of pMOS transistor P1 down to Vref_HS through nmos transistor N3, turning pMOS transistor P1 on. As the gate voltage of pMOS transistor P1 decreases, the charge on the gate of pMOS transistor P1 is discharged to GND through nmos transistor N3 and pMOS transistor P2 of Vref_HS. To achieve a certain driving capability in the MOSFET driver circuit, pMOS transistor P1 is large in size and has a large gate charge. However, due to the limited response speed of Vref_HS under steady-state conditions, the Vref_HS voltage stabilization speed is limited. During this process, the waveform diagram of the Vref_HS output voltage and the gate voltage of the pmos tube P1 is as follows Figure 2 shown.

[0007] Figure 1 During normal operation of the conventional MOSFET driver circuit shown, NMOS transistor N1 is turned on and off by INV3. When the gate input of INV3 is high, pMOS transistor P4 of INV3 is turned off, while NMOS transistor N4 is turned on. This pulls the gate of NMOS transistor N1 down to GND through NMOS transistor N4, turning off NMOS transistor N1. When the gate input of INV3 is low, pMOS transistor P4 of INV3 is turned on, while NMOS transistor N4 is turned off. This pulls the gate of NMOS transistor N1 up to Vref_LS through pMOS transistor P4, turning on NMOS transistor N1. As the gate voltage of NMOS transistor N1 rises, the power supply charge reaches the gate of NMOS transistor N1 through NMOS transistor N2 of Vref_LS and pMOS transistor P4 of inverter INV3. To achieve a certain driving capability in the MOSFET driver circuit, NMOS transistor N1 is large in size and has a large gate charge. However, due to the limited response speed of Vref_LS under steady-state conditions, the voltage stabilization speed of Vref_LS is limited. During this process, the waveform diagram of the Vref_LS output voltage and the gate voltage of the nmos tube N1 is as follows Figure 3 shown.

[0008] See Figure 2 and Figure 3 The internal power supplies Vref_LS and Vref_HS have limited response speed under steady-state conditions, which results in limited turn-on speed of the output-stage devices N1 / P1 of the driver circuit, affecting the rise / fall speed of the output voltage, limiting the peak output current of the output-stage devices, and resulting in low driving effect of the MOSFET driver circuit. Summary of the Invention

[0009] In order to solve the problems existing in the background technology, the present invention provides a MOSFET driving circuit for power management. On the basis of the conventional MOSFET driving circuit, an nmos acceleration circuit and a pmos acceleration circuit are introduced. The nmos acceleration circuit accelerates the turn-on speed of the nmos tube N1 and the transient stability speed of the Vref_LS internal power module. The pmos acceleration circuit accelerates the turn-on speed of the pmos tube P1 and the transient stability speed of the Vref_HS internal power module, thereby improving the driving effect of the MOSFET driving circuit. The MOSFET driving circuit includes:

[0010] Vref_HS internal power supply module, Vref_LS internal power supply module, level shift module, buffer module, first inverter group, second inverter group, nmos acceleration circuit, nmos tube N1, pmos acceleration circuit and pmos tube P1;

[0011] The buffer module is used to receive an external square wave signal, and to shape the external square wave signal so that the amplitude of the square wave signal reaches a preset amplitude before sending it to the first inverter group, the level shift module and the pmos acceleration circuit;

[0012] The first inverter group gradually amplifies the square wave signal output by the buffer module to control the gate opening / closing of the NMOS transistor N1;

[0013] The Vref_LS internal power supply module is used to provide power to the pmos acceleration circuit, the buffer module and the first inverter group;

[0014] The Vref_HS internal power supply module is used to provide power to the second inverter group and the nmos acceleration circuit;

[0015] The level shift module is used to convert the square wave signal output by the buffer unit from 0 to Vref_LS to Vref_HS to Vdd according to the output signals of the Vref_LS internal power supply module and the Vref_HS internal power supply module, and provide it to the second inverter group and the nmos acceleration circuit;

[0016] The second inverter group gradually amplifies the square wave signal output by the level shift to control the gate opening / closing of the pmos transistor P1;

[0017] The nmos acceleration circuit injects current into the Vref_LS internal power module and the gate of the nmos tube N1 at the falling edge of the input signal, thereby accelerating the turn-on speed of the nmos tube N1 and improving the voltage transient stabilization speed of the Vref_LS internal power module;

[0018] The pmos acceleration circuit extracts current from the Vref_HS internal power module and the gate of the pmos tube P1 at the rising edge of the input signal, thereby accelerating the turn-on speed of the pmos tube P1 and improving the voltage transient stabilization speed of the Vref_HS internal power module;

[0019] The drain of nmos tube N1 and the source of pmos tube P1 are connected as the output of MOSFET drive circuit;

[0020] The source of the nmos tube N1 is connected to GND; the source of the pmos tube P1 is connected to Vdd.

[0021] Preferably, the nmos acceleration circuit includes: an inverter INV9, an inverter INV10, a NAND gate NAND1, a pmos tube P5 and a pmos tube P6;

[0022] The input end of the inverter INV9 is connected to the output end of the level shift module; the output end of the inverter INV9 is connected to the input end of the inverter INV10; the output end of the inverter INV10 is connected to the first input end of the NAND gate NAND1; the output end of the inverter INV9 is connected to the second input end of the NAND gate NAND1; the output end of the NAND gate NAND1 is connected to the gate of the pmos transistor P5 and the gate of the pmos transistor P6; the source of the pmos transistor P5 and the source of the pmos transistor P6 are connected to the common power supply Vdd; the drain of the pmos transistor P5 is connected to the output end of the Vref_LS internal power supply module; and the drain of the pmos transistor P6 is connected to the gate of the nmos transistor N1.

[0023] Preferably, a first common terminal of the NAND gate NAND1, the inverter INV9 and the inverter INV10 is connected to the common power supply Vdd; a second common terminal of the NAND gate NAND1, the inverter INV9 and the inverter INV10 is connected to the output terminal of the Vref_HS internal power supply module.

[0024] Preferably, the pmos acceleration circuit includes: an inverter INV7, an inverter INV8, a NOR gate NOR1, an nmos tube N5 and an nmos tube N6;

[0025] The input end of the inverter INV7 is connected to the output end of the buffer module; the output end of the inverter INV7 is connected to the input end of the inverter INV8; the output end of the inverter INV8 is connected to the first input end of the NOR gate NOR1; the output end of the inverter INV7 is connected to the second input end of the NOR gate NOR1; the output end of the NOR gate NOR1 is connected to the gate of the nmos tube N5 and the gate of the nmos tube N6; the drain of the nmos tube N5 is connected to the output end of the Vref_HS internal power supply module; the source of the nmos tube N5 and the source of the nmos tube N6 are connected to GND; the drain of the nmos tube N6 is connected to the gate of the pmos tube P1.

[0026] Preferably, a first common terminal of the NOR gate NOR1, the inverter INV7 and the inverter INV8 is connected to the output terminal of the Vref_LS internal power supply module; a second common terminal of the NOR gate NOR1, the inverter INV7 and the inverter INV8 is connected to GND.

[0027] Preferably, the first inverter group includes: an inverter INV1, an inverter INV2 and an inverter INV3;

[0028] The input end of the inverter INV1 is connected to the output end of the buffer module; the output end of the inverter INV1 is connected to the input end of the inverter INV2; the output end of the inverter INV2 is connected to the input end of the inverter INV3; and the output end of the inverter INV3 is connected to the gate of the nmos tube N1.

[0029] Preferably, a first common terminal of the inverter INV1 , the inverter INV2 and the inverter INV3 is connected to GND; a second common terminal of the inverter INV1 , the inverter INV2 and the inverter INV3 is connected to the output terminal of the Vref_LS internal power supply module.

[0030] Preferably, the second inverter group includes: an inverter INV4, an inverter INV5 and an inverter INV6;

[0031] The input end of the inverter INV4 is connected to the output end of the level shift module; the output end of the inverter INV4 is connected to the input end of the inverter INV5; the output end of the inverter INV5 is connected to the input end of the inverter INV6; and the output end of the inverter INV6 is connected to the gate of the pmos tube P1.

[0032] Preferably, a first common terminal of the inverter INV4, the inverter INV5 and the inverter INV6 is connected to the output terminal of the Vref_HS internal power supply module; a second common terminal of the inverter INV4, the inverter INV5 and the inverter INV6 is connected to the common power supply Vdd.

[0033] The present invention has at least the following beneficial effects:

[0034] The present invention injects current into the Vref_LS internal power module and the NMOS transistor N1 at the falling edge of the NMOS acceleration circuit input signal by adding an NMOS acceleration circuit, thereby reducing the downward fluctuation amplitude of the Vref_LS internal power module, increasing the rising edge speed of the gate of the NMOS transistor N1, and ultimately increasing the turn-on speed of the NMOS transistor N1. The present invention also extracts current from the Vref_HS internal power module and the PMOS transistor P1 at the rising edge of the PMOS acceleration circuit input signal by adding a PMOS acceleration circuit, thereby reducing the upward fluctuation amplitude of the Vref_HS, increasing the voltage transient stabilization speed of the Vref_HS internal power module and increasing the falling edge speed of the gate of the PMOS transistor P1, ultimately increasing the turn-on speed of the PMOS transistor P1, and achieving the goal of accelerating PMOS. The NMOS acceleration circuit and the PMOS acceleration circuit of the present invention improve the driving effect of the MOSFET driving circuit.

[0035] Figures in the specification

[0036] Figure 1 This is a diagram of the commonly used MOSFET drive circuit structure;

[0037] Figure 2 This is the waveform of the Vref_LS output voltage of a commonly used MOSFET drive circuit during actual operation;

[0038] Figure 3 This is the waveform of the Vref_HS output voltage of a commonly used MOSFET drive circuit during actual operation;

[0039] Figure 4 A structural diagram of a MOSFET driving circuit for power management according to the present invention;

[0040] Figure 5 This is a common Vref_LS circuit structure diagram;

[0041] Figure 6 This is a common Vref_HS circuit structure diagram;

[0042] Figure 7 It is a structural diagram of the pmos acceleration circuit of the present invention;

[0043] Figure 8 The working signal waveform of the pmos acceleration circuit of the present invention is

[0044] Figure 9 This is a structural diagram of the nmos acceleration circuit of the present invention;

[0045] Figure 10 Schematic diagram of the working signal waveform of the nmos acceleration circuit of the present invention;

[0046] Figure 11Schematic diagram of the working signal waveform of the driving circuit of the present invention during actual operation;

[0047] Figure 12 Schematic diagram of the working signal waveform of the driving circuit of the present invention during actual operation;

[0048] Figure 13 This is a schematic diagram of a common buffer module structure;

[0049] Figure 14 This is a schematic diagram of the common level shift module structure. Specific implementation methods

[0050] The following describes the embodiments of the present invention by means of specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0051] Among them, the accompanying drawings are only for illustrative purposes and represent only schematic diagrams rather than actual pictures, and should not be understood as limiting the present invention. In order to better illustrate the embodiments of the present invention, some parts of the accompanying drawings may be omitted, enlarged or reduced, and do not represent the dimensions of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions may be omitted in the accompanying drawings.

[0052] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "back", etc. indicating directions or positional relationships, they are based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0053] See also Figure 4 The present invention provides a MOSFET driving circuit for power management, the MOSFET driving circuit comprising:

[0054] Vref_HS internal power supply module, Vref_LS internal power supply module, level shift module, buffer module, first inverter group, second inverter group, nmos acceleration circuit, nmos tube N1, pmos acceleration circuit and pmos tube P1;

[0055] The buffer module is used to receive an external square wave signal (i.e., an externally input power control signal), and to shape the external square wave signal so that the amplitude of the square wave signal reaches a preset amplitude (i.e., the signal amplitude meets the requirements of the subsequent circuit) and then send it to the first inverter group, the level shift module and the pmos acceleration circuit; wherein, those skilled in the art can set the preset amplitude based on the input requirements of the subsequent circuit.

[0056] The first inverter group gradually amplifies the square wave signal output by the buffer module to control the gate opening / closing of the NMOS transistor N1;

[0057] The Vref_LS internal power supply module is used to provide power to the pmos acceleration circuit, the buffer module and the first inverter group;

[0058] The Vref_HS internal power supply module is used to provide power to the second inverter group and the nmos acceleration circuit;

[0059] The level shift module is used to convert the square wave signal output by the buffer unit from 0 to Vref_LS to Vref_HS to Vdd according to the output signals of the Vref_LS internal power supply module and the Vref_HS internal power supply module, and provide it to the second inverter group and the nmos acceleration circuit;

[0060] The second inverter group gradually amplifies the square wave signal output by the level shift to control the gate opening / closing of the pmos transistor P1;

[0061] The nmos acceleration circuit injects current into the Vref_LS internal power module and the gate of the nmos tube N1 at the falling edge of the input signal, thereby accelerating the turn-on speed of the nmos tube N1 and improving the voltage transient stabilization speed of the Vref_LS internal power module;

[0062] The pmos acceleration circuit extracts current from the Vref_HS internal power module and the gate of the pmos tube P1 at the rising edge of the input signal, thereby accelerating the turn-on speed of the pmos tube P1 and improving the voltage transient stabilization speed of the Vref_HS internal power module;

[0063] The drain of nmos tube N1 and the source of pmos tube P1 are connected as the output of MOSFET drive circuit;

[0064] The source of the nmos tube N1 is connected to GND; the source of the pmos tube P1 is connected to Vdd.

[0065] Inverter

[0066] The inverter includes: an NMOS transistor and a PMOS transistor, wherein the gates of the NMOS transistor and the PMOS transistor are connected as the input end of the inverter; the drains of the NMOS transistor and the PMOS transistor are connected as the output end of the inverter; the source of the NMOS transistor serves as the first common end of the inverter, and the source of the PMOS transistor serves as the second common end of the inverter.

[0067] NAND gate NAND1

[0068] The NAND gate NAND1 includes: a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, and a second PMOS transistor, wherein the gates of the first NMOS transistor and the first PMOS transistor are connected as a first input terminal of the NAND gate NAND1, and the gates of the second NMOS transistor and the second PMOS transistor are connected as a second input terminal of the NAND gate NAND1; the drain of the first NMOS transistor is connected to the source of the second NMOS transistor, and the drain of the second NMOS transistor, the drain of the first PMOS transistor, and the drain of the second PMOS transistor are connected as an output terminal of the NAND gate NAND1; the source of the first NMOS transistor serves as a first common terminal (VDD) of the NAND gate NAND1, and the source of the first PMOS transistor and the source of the second PMOS transistor are connected as a second common terminal (Vref_HS) of the NAND gate NAND1.

[0069] NOR gate NOR1

[0070] The NOR gate NOR1 includes: a first NMOS transistor, a first PMOS transistor, a second NMOS transistor and a second PMOS transistor, wherein the gates of the first NMOS transistor and the first PMOS transistor are connected as a first input terminal of the NOR gate NOR1, and the gates of the second NMOS transistor and the second PMOS transistor are connected as a second input terminal of the NOR gate NOR1;

[0071] The drain of the first PMOS transistor is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor, the drain of the first NMOS transistor, and the drain of the second NMOS transistor are connected as the output end of the NOR gate NOR1; the source of the first PMOS transistor serves as the first common end (Vref_LS) of the NAND gate NAND1, and the source of the first NMOS transistor and the source of the second NMOS transistor are connected as the second common end (GND) of the NAND gate NAND1.

[0072] Vref_LS internal power module

[0073] Figure 5This is the circuit structure of a conventional Vref_LS internal power supply module. The Zener diode Z1 and resistor R1 provide a gate bias voltage equal to the Zener diode's regulated voltage, VZ1, for the gate of NMOS transistor N2. NMOS transistor N2 and resistor R2 form a source-follower circuit, buffering the gate voltage of NMOS transistor N2. The source-follower output voltage is VZ1-Vgs_N2. In typical processes, VZ1 is greater than 5.5V, and Vgs is approximately 0.9V. This results in an output voltage of the internal power supply Vref_LSV greater than 4.5V, typically around 5V. To ensure the output capacity of the internal power supply, the NMOS transistor N2 is appropriately oversized. Furthermore, a stabilizing capacitor C1 is placed between the source of NMOS transistor N2 and ground GND to ensure the transient response of the Vref_LS internal power supply module.

[0074] In the Vref_LS internal power supply module, the upper end of the resistor R1 is connected to the power supply Vdd of the MOSFET drive circuit, the lower end of the resistor R1 and the gate of the nmos tube N2 are connected to the N pole of the Zener tube Z1; the drain of the nmos tube N2 is connected to the power supply Vdd of the MOSFET drive circuit, the source of the nmos tube N2, the upper end of the resistor R2 and the upper end of the capacitor C1 are connected as the output end of the Vref_LS internal power supply module, and the P pole of the Zener tube Z1, the lower end of the resistor R2 and the lower end of the capacitor C1 are connected to GND.

[0075] Vref_HS internal power module

[0076] Figure 6 This is the circuit structure of a conventional Vref_HS internal power supply module. The Zener diode Z2 and resistor R3 provide a gate bias voltage for the gate of the PMSO transistor P2. The bias voltage is Vdd-VZ1, where VZ1 is the Zener diode's regulated voltage. The PMSO transistor P2 and resistor R4 form a source-follower circuit, buffering the gate voltage of the PMSO transistor P2. The source-follower output voltage is Vdd-VZ1-Vgs_P2. In typical processes, VZ1 is greater than 5.5V, and P2's Vgs is approximately -0.9V. As a result, the output voltage of the internal power supply Vref_HS is greater than Vdd-4.5V, typically around Vdd-5V. To ensure the output capacity of the internal power supply, the PMSO transistor P2 is appropriately oversized. Furthermore, a stabilizing capacitor C2 is placed between the source of the PMSO transistor P2 and the power supply Vdd to ensure the transient response of the Vref_HS internal power supply module.

[0077] In the Vref_HS internal power supply module, the lower end of the resistor R3 and the drain of the pmos tube P2 are connected to GND, the upper end of the resistor R3, the gate of the pmos tube P2 and the P pole of the Zener tube Z2 are connected; the N pole of the Zener tube Z2, the upper end of the resistor R4 and the upper end of the capacitor C2 are connected to the power supply Vdd of the MOSFET drive circuit; the source of the pmos tube P2, the lower end of the resistor R4 and the lower end of the capacitor C2 are connected as the output end of the Vref_HS internal power supply module.

[0078] Buffer module

[0079] The buffer module, located at the port of the MOSFET driver circuit, receives external logic signals and drives the internal subsequent sub-circuit modules. In actual circuit operation, the amplitude and rise / fall times of the external logic signal often differ from those of the ideal logic signal. Therefore, the buffer module is introduced at the port of the MOSFET driver circuit. The buffer module shapes the external logic signal to meet the signal amplitude requirements of the subsequent circuitry. Furthermore, the buffer module accelerates the rise / fall time of the logic signal, ensuring a fast response from the subsequent modules.

[0080] See also Figure 13 The common implementation structure of the buffer module is to implement it in a cascade manner of a Schmitt trigger and an inverter. The input end of the Schmitt trigger is the input end of the buffer module, the output end of the Schmitt trigger is connected to the input end of the inverter, the output end of the inverter serves as the output end of the buffer module, the first common end of the Schmitt trigger and the first common end of the inverter are connected as the first common end (Vdd) of the buffer module, and the second common end of the Schmitt trigger and the second common end of the inverter are connected as the second common end (GND) of the buffer module.

[0081] The Schmitt trigger includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; wherein the gate of the first PMOS transistor, the gate of the second PMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor are connected as input terminals of the Schmitt trigger;

[0082] The drain of the first NMOS transistor, the source of the second NMOS transistor and the source of the third NMOS transistor are connected;

[0083] The drain of the first PMOS transistor, the source of the second PMOS transistor, and the source of the third PMOS transistor are connected; the drain of the second PMOS transistor, the drain of the second NMOS transistor, the gate of the third PMOS transistor, and the gate of the third NMOS transistor are connected as the output end of the Schmitt trigger; the drain of the third PMOS transistor and the source of the first NMOS transistor are connected as the first common end (VDD) of the Schmitt trigger; the drain of the third NMOS transistor and the source of the first PMOS transistor are connected as the second common end (GND) of the Schmitt trigger.

[0084] Level shift module

[0085] See also Figure 14 The input signal of the level shift module comes from the buffer module, and the signal amplitude range is 0~Vref_LS; the power supply range of the level shift module is Vref_HS~Vdd; the level shift module receives the logic signal in the voltage range of 0~Vref_LS from the buffer module and converts it into a logic signal in the voltage range of Vref_HS~Vdd.

[0086] The level shift module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor.

[0087] The gate of the first NMOS transistor serves as the input terminal IN+ of the level shift module; the gate of the second NMOS transistor serves as the input terminal IN- of the level shift module; the input signal at the input terminal IN+ is in phase with the input signal at the input terminal IN-;

[0088] The source of the first NMOS transistor and the source of the second NMOS transistor are connected to serve as a second common terminal (GND) of the level shift module;

[0089] The gate of the third NMOS transistor and the gate of the fourth NMOS transistor are connected as the first power input terminal of the level shift module; in the present invention, the first power input terminal is connected to the output terminal of the Vref_LS internal power module;

[0090] The source of the third NMOS tube is connected to the drain of the first NMOS tube; the source of the fourth NMOS tube is connected to the drain of the second NMOS tube; the drain of the third NMOS tube is connected to the drain of the first PMOS tube; and the drain of the fourth NMOS tube is connected to the drain of the second PMOS tube.

[0091] The gate of the first PMOS transistor and the gate of the second PMOS transistor are connected as the second power input terminal of the level shift module; in the present invention, the second power input terminal is connected to the output terminal of Vref_HS;

[0092] The source of the first PMOS tube, the drain of the third PMOS tube and the gate of the fourth PMOS tube are connected; the source of the second PMOS tube, the gate of the third PMOS tube and the drain of the fourth PMOS tube are connected as the output end of the level shift module;

[0093] The source of the third PMOS transistor and the source of the fourth PMOS transistor are connected to serve as the first common terminal (VDD) of the level shift module;

[0094] In the level shift module, when the input signal IN+ is high and IN- is low, the first NMOS tube is turned on and the second NMOS tube is turned off; the first NMOS tube and the third NMOS tube are in the same current branch, and the first NMOS tube is turned on, causing the third NMOS tube to be turned on, so that the drain of the first NMOS tube and the source of the third NMOS tube are 0V; the second NMOS tube and the fourth NMOS tube are in the same current branch, and the second NMOS tube is turned off, causing the third NMOS tube to be turned off, so that the drain of the second NMOS tube and the source of the fourth NMOS tube are Vref_LS; the third NMOS tube and the first PMOS tube are in the same current branch, and the turning on of the third NMOS tube causes the turning on of the first PMOS The fourth NMOS tube / the second PMOS tube form the same current branch, and the fourth NMOS tube is turned off, which causes the second PMOS tube to be turned off. The gate of the third PMOS tube is connected to the drain of the fourth PMOS tube, and the gate of the fourth PMOS tube is connected to the drain of the third PMOS tube. The first PMOS tube / the third PMOS tube form the same current branch, and the second PMOS tube / the fourth PMOS tube form the same current branch. The first PMOS tube is turned on / the second PMOS tube is turned off, which causes the third PMOS tube to be turned on / the fourth PMOS tube to be turned off. Therefore, the voltage of the drain of the third PMOS tube is Vdd, and the voltage of the drain of the fourth PMOS tube is Vref_HS. Therefore, the voltage at the output end of the level shift module is Vref_HS.

[0095] In the level shift module, when the input signal IN+ is low and IN- is high, the first NMOS tube is turned off and the second NMOS tube is turned on; the first NMOS tube and the third NMOS tube are in the same current branch, and the first NMOS tube is turned off, causing the third NMOS tube to be turned off, so that the voltage of the drain of the first NMOS tube and the source of the third NMOS tube is Vref_LS; the second NMOS tube and the fourth NMOS tube are in the same current branch, and the second NMOS tube is turned on, causing the third NMOS tube to be turned on, so that the voltage of the drain of the second NMOS tube and the source of the fourth NMOS tube is 0V; the third NMOS tube and the first PMOS tube are in the same current branch, and the third NMOS tube is turned off, causing The first PMOS transistor is turned off; the fourth NMOS transistor and the second PMOS transistor form the same current branch, and turning on the fourth NMOS transistor causes the second PMOS transistor to turn on; the gate of the third PMOS transistor is connected to the drain of the fourth PMOS transistor, and the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor; the first PMOS transistor and the third PMOS transistor form the same current branch, and the second PMOS transistor and the fourth PMOS transistor form the same current branch, and the first PMOS transistor is turned off / the second PMOS transistor is turned on, causing the third PMOS transistor to be turned off / the fourth PMOS transistor to be turned on, so that the voltage at the drain of the third PMOS transistor is Vref_HS, the voltage at the drain of the fourth PMOS transistor is Vdd, and the output voltage is Vdd.

[0096] See also Figure 9 Preferably, the nmos acceleration circuit includes: an inverter INV9, an inverter INV10, a NAND gate NAND1, a pmos tube P5 and a pmos tube P6;

[0097] The input end of the inverter INV9 is connected to the output end of the level shift module; the output end of the inverter INV9 is connected to the input end of the inverter INV10; the output end of the inverter INV10 is connected to the first input end of the NAND gate NAND1; the output end of the inverter INV9 is connected to the second input end of the NAND gate NAND1; the output end of the NAND gate NAND1 is connected to the gate of the pmos transistor P5 and the gate of the pmos transistor P6; the source of the pmos transistor P5 and the source of the pmos transistor P6 are connected to the common power supply Vdd; the drain of the pmos transistor P5 is connected to the output end of the Vref_LS internal power supply module; and the drain of the pmos transistor P6 is connected to the gate of the nmos transistor N1.

[0098] The input signal of the nmos acceleration circuit is buffered by the cascaded INV9 and INV10 and reaches the NAND gate NAND1. The output signal of the NAND gate NAND1 forms a narrow pulse at the falling edge of the INV9 input signal, turning on the pmos tube P5 / P6 at the output end of the nmos acceleration circuit, maintaining the stability of the output voltage of the Vref_LS internal power module, and accelerating the rise of the gate of the nmos tube N1 at the output stage of the MOSFET drive circuit, thereby accelerating the response speed of the nmos tube at the output stage of the MOSFET drive circuit.

[0099] See also Figure 10 At the moment the input signal to the NMOS acceleration circuit falls, INV9 outputs a rising edge, and INV10 outputs a falling edge. Due to the delay in the inverter transmission process, there is a delay between the rising edge of INV9 and the falling edge of INV10. During this delay, both INV9 and INV10 output a high level, causing the output of NAND gate NAND1 to be low. The low output of NAND gate NAND1 turns on PMOS transistors P5 and P6, injecting current into the Vref_LS internal power supply module and NMOS transistor N1, respectively. This reduces the downward fluctuation of the Vref_LS internal power supply module and increases the rising edge speed of NMOS transistor N1's gate. Ultimately, this increases the turn-on speed of NMOS transistor N1, accelerating NMOS transistor N1.

[0100] Preferably, a first common terminal of the NAND gate NAND1, the inverter INV9 and the inverter INV10 is connected to the common power supply Vdd; a second common terminal of the NAND gate NAND1, the inverter INV9 and the inverter INV10 is connected to the output terminal of the Vref_HS internal power supply module.

[0101] See also Figure 7 Preferably, the pmos acceleration circuit includes: an inverter INV7, an inverter INV8, a NOR gate NOR1, an nmos tube N5 and an nmos tube N6;

[0102] The input end of the inverter INV7 is connected to the output end of the buffer module; the output end of the inverter INV7 is connected to the input end of the inverter INV8; the output end of the inverter INV8 is connected to the first input end of the NOR gate NOR1; the output end of the inverter INV7 is connected to the second input end of the NOR gate NOR1; the output end of the NOR gate NOR1 is connected to the gate of the nmos tube N5 and the gate of the nmos tube N6; the drain of the nmos tube N5 is connected to the output end of the Vref_HS internal power supply module; the source of the nmos tube N5 and the source of the nmos tube N6 are connected to GND; the drain of the nmos tube N6 is connected to the gate of the pmos tube P1.

[0103] The input signal of the pmos acceleration circuit is buffered by the cascade inverter INV7 and the inverter INV8 in sequence and reaches the NOR gate circuit NOR1. The output signal of the NOR gate NOR1 forms a narrow pulse at the rising edge of the input signal of the input INV7, so that the output end nmos tube N5 / N6 of the pmos acceleration circuit is turned on, maintaining the stability of the output end voltage of the Vref_HS internal power module, thereby accelerating the decline of the gate of the pmos tube P1 of the output stage of the MOSFET drive circuit, and further accelerating the response speed of the pmos tube of the output stage of the MOSFET drive circuit.

[0104] See also Figure 8 At the moment the input signal of the pmos acceleration circuit rises, the output signal of INV7 is falling, and the output signal of INV8 is rising. Due to the delay in the inverter transmission process, there is a delay between the falling edge of INV7 and the rising edge of INV8. During this delay period, both INV7 and INV8 output a low level, causing the output of NOR gate NOR1 to be high. The high output of NOR gate NOR1 turns on NMOS transistors N5 and N6, drawing current from the Vref_HS internal power module and pmos transistor P1, respectively. This reduces the upward fluctuation of Vref_HS, increases the transient voltage stabilization speed of the Vref_HS internal power module, and improves the falling edge speed of the pmos transistor P1 gate. Ultimately, this increases the turn-on speed of pmos transistor P1, achieving the goal of accelerating pmos.

[0105] Preferably, a first common terminal of the NOR gate NOR1, the inverter INV7 and the inverter INV8 is connected to the output terminal of the Vref_LS internal power supply module; a second common terminal of the NOR gate NOR1, the inverter INV7 and the inverter INV8 is connected to GND.

[0106] Preferably, the first inverter group includes: an inverter INV1, an inverter INV2 and an inverter INV3;

[0107] The input end of the inverter INV1 is connected to the output end of the buffer module; the output end of the inverter INV1 is connected to the input end of the inverter INV2; the output end of the inverter INV2 is connected to the input end of the inverter INV3; and the output end of the inverter INV3 is connected to the gate of the nmos tube N1.

[0108] Preferably, a first common terminal of the inverter INV1 , the inverter INV2 and the inverter INV3 is connected to GND; a second common terminal of the inverter INV1 , the inverter INV2 and the inverter INV3 is connected to the output terminal of the Vref_LS internal power supply module.

[0109] Preferably, the second inverter group includes: an inverter INV4, an inverter INV5 and an inverter INV6;

[0110] The input end of the inverter INV4 is connected to the output end of the level shift module; the output end of the inverter INV4 is connected to the input end of the inverter INV5; the output end of the inverter INV5 is connected to the input end of the inverter INV6; and the output end of the inverter INV6 is connected to the gate of the pmos tube P1.

[0111] Preferably, a first common terminal of the inverter INV4, the inverter INV5 and the inverter INV6 is connected to the output terminal of the Vref_HS internal power supply module; a second common terminal of the inverter INV4, the inverter INV5 and the inverter INV6 is connected to the common power supply Vdd.

[0112] See also Figure 11 When the output voltage of the level shift unit switches from high to low, a narrow pulse voltage is generated within the NMOS acceleration circuit. Using this narrow pulse voltage, the acceleration circuit provides instantaneous current to Vref_LS and the gate of NMOS transistor N1, respectively. This reduces the fluctuation of the Vref_LS voltage and speeds up the rising edge of the NMOS transistor N1 gate voltage, thereby accelerating the turn-on speed of NMOS transistor N1 and the output voltage drop rate.

[0113] See also Figure 12 When the buffer unit output voltage transitions from a low level to a high level, a narrow pulse voltage is generated within the pmos acceleration circuit. This pulse voltage then provides instantaneous current to Vref_HS and the gate of pmos transistor P1, reducing the fluctuations in Vref_HS voltage and accelerating the falling edge of pmos transistor P1's gate voltage. This accelerates the turn-on speed of pmos transistor P1 and the rise of the output voltage.

[0114] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limiting. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions, which should all be included in the scope of the claims of the present invention.

Claims

1. A MOSFET driving circuit for power management, characterized in that: The MOSFET driving circuit includes: a Vref_HS internal power supply module, a Vref_LS internal power supply module, a level shift module, a buffer module, a first inverter group, a second inverter group, an nmos acceleration circuit, an nmos tube N1, a pmos acceleration circuit and a pmos tube P1; The buffer module is used to receive an external square wave signal, and to shape the external square wave signal so that the amplitude of the square wave signal reaches a preset amplitude before sending it to the first inverter group, the level shift module and the pmos acceleration circuit; The first inverter group gradually amplifies the square wave signal output by the buffer module to control the gate opening / closing of the NMOS transistor N1; The Vref_LS internal power supply module is used to provide power to the pmos acceleration circuit, the buffer module and the first inverter group; The Vref_HS internal power supply module is used to provide power to the second inverter group and the nmos acceleration circuit; The level shift module is used to convert the square wave signal output by the buffer unit from 0 to Vref_LS to Vref_HS to Vdd according to the output signals of the Vref_LS internal power supply module and the Vref_HS internal power supply module, and provide it to the second inverter group and the nmos acceleration circuit; The second inverter group gradually amplifies the square wave signal output by the level shift module to control the gate opening / closing of the pmos transistor P1; The nmos acceleration circuit injects current into the Vref_LS internal power module and the gate of the nmos tube N1 at the falling edge of the input signal, thereby accelerating the turn-on speed of the nmos tube N1 and improving the voltage transient stabilization speed of the Vref_LS internal power module; The pmos acceleration circuit extracts current from the Vref_HS internal power module and the gate of the pmos tube P1 at the rising edge of the input signal, thereby accelerating the turn-on speed of the pmos tube P1 and improving the voltage transient stabilization speed of the Vref_HS internal power module; The drain of nmos tube N1 and the source of pmos tube P1 are connected as the output of MOSFET drive circuit; The source of the nmos tube N1 is connected to GND; the source of the pmos tube P1 is connected to Vdd.

2. A MOSFET driving circuit for power management according to claim 1, characterized in that: The nmos acceleration circuit includes: an inverter INV9, an inverter INV10, a NAND gate NAND1, a pmos tube P5 and a pmos tube P6; The input end of the inverter INV9 is connected to the output end of the level shift module; the output end of the inverter INV9 is connected to the input end of the inverter INV10; the output end of the inverter INV10 is connected to the first input end of the NAND gate NAND1; the output end of the inverter INV9 is connected to the second input end of the NAND gate NAND1; the output end of the NAND gate NAND1 is connected to the gate of the pmos transistor P5 and the gate of the pmos transistor P6; the source of the pmos transistor P5 and the source of the pmos transistor P6 are connected to the common power supply Vdd; the drain of the pmos transistor P5 is connected to the output end of the Vref_LS internal power supply module; and the drain of the pmos transistor P6 is connected to the gate of the nmos transistor N1.

3. A MOSFET driving circuit for power management according to claim 2, characterized in that: A first common terminal of the NAND gate NAND1, the inverter INV9 and the inverter INV10 is connected to the common power supply Vdd; a second common terminal of the NAND gate NAND1, the inverter INV9 and the inverter INV10 is connected to the output terminal of the Vref_HS internal power supply module.

4. A MOSFET driving circuit for power management according to claim 1, characterized in that: The pmos acceleration circuit includes: an inverter INV7, an inverter INV8, a NOR gate NOR1, an nmos tube N5 and an nmos tube N6; The input end of the inverter INV7 is connected to the output end of the buffer module; the output end of the inverter INV7 is connected to the input end of the inverter INV8; the output end of the inverter INV8 is connected to the first input end of the NOR gate NOR1; the output end of the inverter INV7 is connected to the second input end of the NOR gate NOR1; the output end of the NOR gate NOR1 is connected to the gate of the nmos tube N5 and the gate of the nmos tube N6; the drain of the nmos tube N5 is connected to the output end of the Vref_HS internal power supply module; the source of the nmos tube N5 and the source of the nmos tube N6 are connected to GND; the drain of the nmos tube N6 is connected to the gate of the pmos tube P1.

5. A MOSFET driving circuit for power management according to claim 4, characterized in that: A first common terminal of the NOR gate NOR1, the inverter INV7 and the inverter INV8 is connected to the output terminal of the Vref_LS internal power supply module; a second common terminal of the NOR gate NOR1, the inverter INV7 and the inverter INV8 is connected to GND.

6. The MOSFET driving circuit for power management according to claim 1, characterized in that: The first inverter group includes: an inverter INV1, an inverter INV2 and an inverter INV3; The input end of the inverter INV1 is connected to the output end of the buffer module; the output end of the inverter INV1 is connected to the input end of the inverter INV2; the output end of the inverter INV2 is connected to the input end of the inverter INV3; and the output end of the inverter INV3 is connected to the gate of the nmos tube N1.

7. A MOSFET driving circuit for power management according to claim 6, characterized in that: A first common terminal of the inverter INV1 , the inverter INV2 , and the inverter INV3 is connected to GND; a second common terminal of the inverter INV1 , the inverter INV2 , and the inverter INV3 is connected to the output terminal of the Vref_LS internal power supply module.

8. The MOSFET driving circuit for power management according to claim 1, wherein: The second inverter group includes: inverter INV4, inverter INV5 and inverter INV6; The input end of the inverter INV4 is connected to the output end of the level shift module; the output end of the inverter INV4 is connected to the input end of the inverter INV5; the output end of the inverter INV5 is connected to the input end of the inverter INV6; and the output end of the inverter INV6 is connected to the gate of the pmos tube P1.

9. A MOSFET driving circuit for power management according to claim 8, characterized in that: A first common terminal of the inverter INV4 , the inverter INV5 , and the inverter INV6 is connected to the output terminal of the Vref_HS internal power module; a second common terminal of the inverter INV4 , the inverter INV5 , and the inverter INV6 is connected to the common power supply Vdd.

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