Method for manufacturing a mim device structure

Abstract

This invention provides a method for fabricating a MIM device structure, comprising the following steps: providing a semiconductor substrate, wherein a first dielectric layer is formed on the semiconductor substrate, and a first conductive plug is formed in the first dielectric layer; sequentially forming a first electrode layer, an HK material layer, and a second electrode layer on the first dielectric layer, wherein the first electrode layer is electrically connected to the first conductive plug; photolithographically etching the first electrode layer, the HK material layer, and the second electrode layer to define a ferroelectric memory region, wherein the first electrode layer of the ferroelectric memory region serves as the lower electrode, the HK material layer of the ferroelectric memory region serves as the intermediate dielectric layer, and the second electrode layer of the ferroelectric memory region serves as the upper electrode. This invention provides a method for fabricating a MIM device structure containing HK material, which is compatible with traditional CMOS manufacturing lines and does not contaminate the production line, resulting in high-performance devices and effectively improving device yield, reliability, and product market competitiveness.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a MIM device structure. Background Technology

[0002] In recent years, in response to the need for further miniaturization of electronic components, research, development and practical application of ferroelectric thin films in electronic components such as capacitors and piezoelectric elements are underway.

[0003] Traditional ferroelectric PZT (containing heavy metals such as lead) processes are complex and expensive, have process line contamination problems, and are incompatible with traditional CMOS (Complementary Metal Oxide Semiconductor) manufacturing processes, resulting in high manufacturing costs. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a MIM device structure that is compatible with traditional CMOS manufacturing lines and does not contaminate the production line.

[0005] To achieve the above and other related objectives, the present invention provides a method for preparing a MIM device structure, comprising the following steps:

[0006] A semiconductor substrate is provided, on which a first dielectric layer is formed, and a first conductive plug is formed in the first dielectric layer;

[0007] A first electrode layer, an HK material layer, and a second electrode layer are sequentially formed on the first dielectric layer, and the first electrode layer is electrically connected to the first conductive plug.

[0008] The first electrode layer, the HK material layer, and the second electrode layer are photolithographically etched to define the ferroelectric memory region. The first electrode layer of the ferroelectric memory region serves as the lower electrode, the HK material layer of the ferroelectric memory region serves as the intermediate dielectric layer, and the second electrode layer of the ferroelectric memory region serves as the upper electrode.

[0009] Optionally, in the fabrication method of the MIM device structure, the material of the HK material layer includes HfO2.

[0010] Optionally, in the fabrication method of the MIM device structure, before photolithography and etching of the first electrode layer, the HK material layer, and the second electrode layer, the method includes: forming an intermediate dielectric antireflective layer on the second electrode layer; the photolithography and etching of the first electrode layer, the HK material layer, and the second electrode layer includes:

[0011] A first patterned photoresist layer is formed on the intermediate dielectric antireflective layer;

[0012] Using the first patterned photoresist layer as a mask, the intermediate dielectric antireflective layer, the second electrode layer, the HK material layer, and the first electrode layer are etched.

[0013] Optionally, in the fabrication method of the MIM device structure, the photolithography and etching of the first electrode layer, the HK material layer, and the second electrode layer includes:

[0014] The first dielectric layer is partially etched, and the thickness of the partially etched first dielectric layer is 15% to 30% of the total thickness of the first electrode layer, the HK material layer, and the second electrode layer.

[0015] Optionally, in the fabrication method of the MIM device structure, the photolithography and etching of the first electrode layer, the HK material layer, and the second electrode layer includes:

[0016] Set the power of the etching equipment to 0 and maintain it at a preset pressure and preset mixed gas flow rate for a preset duration;

[0017] Set the etching equipment to high power mode.

[0018] Optionally, in the method for fabricating the MIM device structure, the preset pressure is 6mT to 10mT.

[0019] Optionally, in the method for fabricating the MIM device structure, the mixed gas includes a mixture of one or more halogen-containing gases and inert gases.

[0020] Optionally, in the method for fabricating the MIM device structure, the mixed gas comprises Cl2:BCl3:Ar in a gas ratio of 8:2:7.

[0021] Optionally, in the fabrication method of the MIM device structure, the photolithography and etching of the first electrode layer, the HK material layer, and the second electrode layer to define the ferroelectric memory region, wherein the first electrode layer of the ferroelectric memory region serves as the lower electrode, the HK material layer of the ferroelectric memory region serves as the intermediate dielectric layer, and the second electrode layer of the ferroelectric memory region serves as the upper electrode, comprising:

[0022] The etching equipment adopts a high-power mode, wherein the high-power mode is characterized by an RF power greater than 850W and a bias power greater than 120W.

[0023] Optionally, in the fabrication method of the MIM device structure, after photolithography and etching of the first electrode layer, the HK material layer, and the second electrode layer to define the ferroelectric memory region, wherein the first electrode layer of the ferroelectric memory region serves as the lower electrode, the HK material layer of the ferroelectric memory region serves as the intermediate dielectric layer, and the second electrode layer of the ferroelectric memory region serves as the upper electrode, the method further includes:

[0024] A second dielectric layer is formed, and the second dielectric layer covers the first dielectric layer and the upper electrode. The second dielectric layer includes, from bottom to top, a silicon nitride layer, a second plasma-enhanced oxide film, and a top dielectric anti-reflection layer.

[0025] A second conductive plug is formed, which sequentially penetrates the top dielectric antireflective layer, the second plasma-enhanced oxide film, and the silicon nitride layer from the upper surface of the second dielectric layer and is then electrically connected to the upper electrode.

[0026] Optionally, in the fabrication method of the MIM device structure, the first dielectric layer comprises, from bottom to top, a silicon-rich oxide thin film, a fluorinated silicon glass, a first plasma-enhanced oxide film, and a bottom dielectric anti-reflection layer. The provision of a semiconductor substrate, on which the first dielectric layer is formed, and prior to the formation of the first conductive plug in the first dielectric layer, includes:

[0027] Transistors are pre-formed on the semiconductor substrate;

[0028] A bottom dielectric layer is formed, which covers the semiconductor substrate and the transistor;

[0029] A first metal layer is formed on the bottom dielectric layer, and a bottom conductive plug is formed through the bottom dielectric layer. The first metal layer is electrically connected to one electrode of the transistor via the bottom conductive plug.

[0030] Optionally, in the method for fabricating the MIM device structure, the step of sequentially forming a first electrode layer, an HK material layer, and a second electrode layer on the first dielectric layer includes:

[0031] TiN material was deposited using physical vapor deposition to form the first TiN layer;

[0032] Atomic layer deposition is used to deposit TiN material on the first TiN layer to form a second TiN layer. The first TiN layer and the second TiN layer constitute the first electrode layer.

[0033] An atomic layer deposition process is used to deposit HK material on the second TiN layer to form the HK material layer;

[0034] TiN material was deposited on the HK material layer using a physical vapor deposition process to form a third TiN layer;

[0035] Atomic layer deposition (ALD) is used to deposit TiN material on the third TiN layer to form a fourth TiN layer. The third TiN layer and the fourth TiN layer together form the second electrode layer.

[0036] Optionally, in the fabrication method of the MIM device structure, the thickness of the first TiN layer is [missing information]. The thickness of the second TiN layer is And / or,

[0037] The thickness of the third TiN layer is The thickness of the fourth TiN layer is And / or,

[0038] The thickness of the HK material layer is

[0039] This invention provides a method for fabricating MIM device structures incorporating novel ferroelectric materials (i.e., HighK materials, or HK materials, high-k materials, high-dielectric-coefficient materials, such as HfO2, etc.), which is compatible with traditional CMOS manufacturing processes and does not pollute the production line. Moreover, the etching method used in defining the ferroelectric memory region in this invention produces few byproducts that are easy to remove, enabling the device to obtain excellent CV electrical performance and PV hysteresis characteristics, effectively improving device yield, reliability, and product market competitiveness. Attached Figure Description

[0040] Figure 1 This is a flowchart of a method for fabricating a MIM device structure according to an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of a MIM device structure according to an embodiment of the present invention;

[0042] Figures 3-4 This is a schematic diagram of the photolithography and etching steps of a MIM device structure according to an embodiment of the present invention;

[0043] Figure 5 This is the CV characteristic curve of a MIM device structure according to an embodiment of the present invention;

[0044] Figure 6 This is the PV hysteresis loop of a MIM device structure according to an embodiment of the present invention;

[0045] Figures 1-6 middle,

[0046] 101-Semiconductor substrate, 1011-Shallow trench isolation structure, 1012-Source, 1013-Drain, 102-Bottom dielectric layer, 1031-Gate oxide layer, 1032-Gate, 1033-Sidewall, 1034-Metal silicide, 1041-Bottom conductive plug, 1042-First conductive plug, 1043-Second conductive plug, 105-First metal layer, 106-First dielectric layer, 201-Ferroelectric memory, 2011-First electrode layer, 2012-HK material layer, 2013-Second electrode layer, 2014-Intermediate dielectric antireflective layer, 2015-First patterned photoresist layer, 202-Second dielectric layer, 301-Second metal layer. Detailed Implementation

[0047] The fabrication method of the MIM device structure proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0048] Traditional ferroelectric PZT (containing lead and other heavy metals) processes are complex and expensive, suffer from line contamination issues, and are incompatible with traditional CMOS manufacturing lines, resulting in high manufacturing costs. The inventors have discovered that ferroelectric memory (HfO2 FRAM Cap MIM) incorporating novel ferroelectric materials (i.e., HighK materials, or HK materials, high-k materials, high-dielectric-coefficient materials, such as HfO2) uses HK material as the capacitor dielectric layer, avoiding the traditional ferroelectric PZT (containing lead and other heavy metals) process and thus the heavy metal contamination problems associated with it. Furthermore, ferroelectric memory incorporating these novel ferroelectric materials has enormous potential in the low-power, high-reliability embedded memory market.

[0049] Further research by the inventors revealed that, due to the limitations of HK material properties, etching of ferroelectric memories containing novel ferroelectric materials cannot be completed in the BEOL (Back-End Process) metal processing, which is compatible with traditional CMOS manufacturing lines. Furthermore, currently, no fab (fab) in China can fabricate ferroelectric memories containing novel ferroelectric materials in the BEOL metal processing. While etching of ferroelectric memories containing novel ferroelectric materials can be achieved in the front-end process with some difficulty, it introduces severe metal contamination problems. Metal contamination is difficult to eliminate, and the introduced metal ions affect the entire front-end process. Metal ions are highly mobile in semiconductor materials, constituting mobile ion contamination that moves throughout the silicon wafer. This leads to increased leakage current, reduced minority carrier lifetime, and changes in the device's threshold voltage, resulting in structural defects in the semiconductor device structure and severely impairing its electrical performance and long-term reliability. Therefore, etching of any metal materials must be strictly avoided in the front-end process of semiconductor fabrication; that is, etching of ferroelectric memories containing novel ferroelectric materials cannot be incorporated into the front-end process.

[0050] Further research by the inventors revealed that while adapting ferroelectric memory containing novel ferroelectric materials to a back-end metal processing step (BEOL) avoids metal contamination issues from the front-end process, it prevents the etching of the HK material. This is because BEOL back-end metal processing typically uses etching agents such as Cl2, BCl3, N2, or CHF3. The byproducts generated from the reaction with the HK material, due to their poor volatility, adhere to the material surface, easily causing etching termination and preventing the complete etching of the HK material, thus hindering the fabrication of ferroelectric memory containing the novel ferroelectric material. Furthermore, the etching byproducts are difficult to remove using conventional stripping processes, again preventing the etching of ferroelectric memory containing the novel ferroelectric material within existing BEOL back-end metal processing steps. Therefore, the etching of ferroelectric memory containing the novel ferroelectric material is incompatible with existing CMOS manufacturing lines.

[0051] In order to achieve compatibility with existing CMOS manufacturing lines without contaminating the production line and to obtain high-performance devices, this invention provides a method for fabricating a MIM device structure. In the embodiments of this application, it is a method for fabricating a ferroelectric memory (HfO2 FRAM Cap MIM) containing novel ferroelectric materials (i.e., High K materials or high dielectric constant materials, such as HfO2).

[0052] See Figures 1-3 The method for fabricating the MIM device structure includes the following steps:

[0053] Step S1: Provide a semiconductor substrate 101, on which a first dielectric layer 106 is formed, and a first conductive plug 1042 is formed in the first dielectric layer 106;

[0054] Step S2: A first electrode layer 2011, an HK material layer 2012, and a second electrode layer 2013 are sequentially formed on the first dielectric layer 106, and the first electrode layer 2011 is electrically connected to the first conductive plug 1042.

[0055] Step S3: Photolithography and etching of the first electrode layer 2011, the HK material layer 2012, and the second electrode layer 2013 to define the ferroelectric memory region. The first electrode layer 2011 of the ferroelectric memory region serves as the lower electrode, the HK material layer 2012 of the ferroelectric memory region serves as the intermediate dielectric layer, and the second electrode layer 2013 of the ferroelectric memory region serves as the upper electrode.

[0056] See Figure 2 In step S1, the semiconductor substrate 101 includes a unit region A and a peripheral region B. The semiconductor substrate 101 can be at least one of the following materials: single crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc.

[0057] The provision of the semiconductor substrate 101, wherein a first dielectric layer 106 is formed on the semiconductor substrate 101, and before the formation of a first conductive plug 1042 in the first dielectric layer 106, includes:

[0058] Step S01: A transistor is formed on the semiconductor substrate 101 in advance;

[0059] Step S02: Form a bottom dielectric layer 102, which covers the semiconductor substrate 101 and the transistor;

[0060] Step S03: A first metal layer 105 is formed on the bottom dielectric layer 102, and a bottom conductive plug 1041 is formed through the bottom dielectric layer 102. The first metal layer 105 is electrically connected to one electrode of the transistor via the bottom conductive plug 1041.

[0061] In step S01, the transistor in this embodiment can be a MOS, while in other embodiments the transistor can be CMOS, VDMOS, LDMOS, IGBT, BJT, etc. The step of pre-forming the transistor on the semiconductor substrate 101 specifically refers to pre-forming the transistor on the semiconductor substrate 101 in unit region A, including:

[0062] Step S011: Form a gate oxide layer 1031 on the semiconductor substrate 101;

[0063] Step S012: Form a gate 1032 on the gate oxide layer 1031;

[0064] Step S013: Form sidewalls 1033 on both sides of the gate 1032;

[0065] Step S014: Ion implantation is performed on the semiconductor substrate 101 to form a source 1012 and a drain 1013 in the semiconductor substrate 101 on both sides of the gate 1032.

[0066] After forming the source 1012 and drain 1013, the method further includes: step S015: forming metal silicide 1034 on the gate 1032, source 1012 and drain 1013.

[0067] In step S03, a portion of the first metal layer 105 in the cell region A can serve as a bit line BL, and the bit line BL is electrically connected to the electrode of the drain 1013 through the bottom conductive plug 1041. The electrode of the source 1012 of the transistor is electrically connected to the ferroelectric memory 201 through the bottom conductive plug 1041, the remaining first metal layers 105 in the cell region A (excluding the bit line BL), and the first conductive plug 1042.

[0068] The peripheral region B of the semiconductor substrate 101 is separated from the unit region A by a shallow trench isolation structure 1011. The bottom dielectric layer 102 and the first metal layer 105 are formed on the semiconductor substrate 101 in the peripheral region B.

[0069] The shallow trench isolation structure 1011, source 1012, drain 1013, gate oxide layer 1031, gate 1032, sidewall 1033, metal silicide 1034, bottom dielectric layer 102, bottom conductive plug 1041, and first metal layer 105 on the semiconductor substrate 101 can be manufactured using conventional CMOS front-end processes and first metal layer manufacturing processes, which will not be elaborated here. That is, the fabrication method of the MIM device structure of the present invention is partly similar to the conventional CMOS front-end process, the difference being the addition of the first conductive plug and ferroelectric memory fabrication in the BEOL (back-end processing) back-end metal process.

[0070] The first dielectric layer 106 covers the bottom dielectric layer 102 and the first metal layer 105. Specifically, the first dielectric layer 106 covers the bottom dielectric layer and the first metal layer in the unit region A and the peripheral region B. The first dielectric layer 106 comprises, from bottom to top, a silicon-rich oxide thin film, a fluorinated silicon glass, a first plasma-enhanced oxide film, and a bottom dielectric anti-reflection layer. The method for forming the first dielectric layer 106 may include the following steps:

[0071] Step S101: A silicon-rich oxide film (SRO) is formed on the first metal layer 105, and the silicon-rich oxide film also covers the bottom dielectric layer 102;

[0072] Step S102: Form fluorinated silicon glass (FSG) on the silicon-rich oxide film;

[0073] Step S103: Form a first plasma-enhanced oxide film (PEOX) on the fluorinated silicon glass;

[0074] Step S104: Perform chemical mechanical polishing (CMP) on the first plasma-enhanced oxide film;

[0075] Step S105: Form a bottom dielectric antireflective layer (DARC) on the first plasma-enhanced oxide film after chemical mechanical polishing.

[0076] In steps S101 to S105, the thickness of the silicon-rich oxide film is preferably... The preferred thickness of the fluorinated silicon glass is... The thickness of the first plasma-enhanced oxide film is preferably... The thickness of the bottom dielectric antireflective layer is preferably... The method for forming each structural layer in the first dielectric layer 106 includes either chemical deposition or physical deposition.

[0077] In step S104, the first plasma-enhanced oxide film is subjected to chemical mechanical polishing (CMP). The thickness of the remaining first dielectric layer (comprising a silicon-rich oxide film, fluorinated silicon glass, and the first plasma-enhanced oxide film) after polishing is a target value.

[0078] The method for forming the first conductive plug 1042 includes:

[0079] Step S111: Form a third patterned photoresist layer on the first dielectric layer 106;

[0080] Step S112: Using the third patterned photoresist layer as a mask, the first dielectric layer 106 is etched to form a first through hole penetrating the first dielectric layer 106, and the first through hole exposes the first metal layer 105.

[0081] Step S113: Fill and chemically mechanically grind the first through hole to form the first conductive plug 1042.

[0082] In step S112, the position and number of the first through hole and the first conductive plug 1042 can be set according to process requirements. For example, Figure 2 Two first conductive plugs 1042 are formed, one in the unit area A and the other in the peripheral area B, and the first conductive plugs 1042 in the unit area A and the peripheral area B are electrically connected to the first metal layer 105.

[0083] In step S113, the filling material of the first through hole is preferably tungsten, but is not limited thereto.

[0084] See Figure 3 In step S2, a first electrode layer 2011, an HK material layer 2012, and a second electrode layer 2013 are sequentially formed on the first dielectric layer 106, and the first electrode layer 2011 is electrically connected to the first conductive plug 1042. After forming the second electrode layer 2013, the fabrication method may further include forming an intermediate dielectric antireflective layer (DARC) 2014 on the second electrode layer 2013.

[0085] The first electrode layer 2011 is formed through a two-stage deposition process, specifically including:

[0086] Step S21: Deposit TiN material to form the first TiN layer;

[0087] Step S22: Deposit TiN material on the first TiN layer to form a second TiN layer.

[0088] In step S21, the thickness of the first TiN layer is preferably... The preferred deposition method is physical vapor deposition (PVD), but it is not limited to this.

[0089] In step S22, the thickness of the second TiN layer is preferably... The preferred deposition method is atomic layer deposition (ALD), but it is not limited to this.

[0090] The HK material layer 2012 can be made of any HK material, but is preferably HfO2. For example, the HK material layer 2012 is an HfO2 layer.

[0091] The method for forming the HK material layer 2012 includes:

[0092] Step S23: Deposit HK material, such as HfO2 material, on the second TiN layer to form the HK material layer 2012.

[0093] In step S23, the thickness of the HK material layer is preferably... The preferred deposition method is atomic layer deposition (ALD), but it is not limited to this.

[0094] The second electrode layer 2013 is also formed through a two-stage deposition process, specifically including:

[0095] Step S24: Deposit TiN material on the HK material layer 2012 to form a third TiN layer;

[0096] Step S25: Deposit TiN material on the third TiN layer to form a fourth TiN layer.

[0097] In step S24, the thickness of the third TiN layer is preferably... The preferred deposition method is physical vapor deposition (PVD), but it is not limited to this.

[0098] In step S25, the thickness of the fourth TiN layer is preferably... The preferred deposition method is atomic layer deposition (ALD), but it is not limited to this.

[0099] Therefore, the first electrode layer 2011 and the second electrode layer 2013 are grown in two different ways, which can significantly improve the device performance.

[0100] The intermediate dielectric antireflective layer 2014 can be fabricated using physical vapor deposition (PVD), but is not limited to this method. The thickness of the intermediate dielectric antireflective layer 2014 is preferably...

[0101] In step S3, the photolithography and etching of the first electrode layer 2011, HK material layer 2012, second electrode layer 2013, and intermediate dielectric antireflective layer 2014 includes: over-etching a portion of the first dielectric layer 106, wherein the thickness of the portion of the first dielectric layer 106 is 15% to 30% of the total thickness of the first electrode layer 2011, HK material layer 2012, and second electrode layer 2013.

[0102] See Figure 4 In step S3, the ferroelectric memory 201 is fabricated by photolithography and etching processes.

[0103] Before photolithography and etching of the first electrode layer 2011, HK material layer 2012, and second electrode layer 2013, the process includes forming an intermediate dielectric anti-reflection layer 2014 on the second electrode layer 2013 to effectively control the device linewidth and further improve device performance. Therefore, the photolithography and etching of the first electrode layer 2011, HK material layer 2012, and second electrode layer 2013 also includes photolithography and etching of the intermediate dielectric anti-reflection layer 2014. The photolithography and etching of the first electrode layer 2011, HK material layer 2012, second electrode layer 2013, and intermediate dielectric anti-reflection layer 2014 includes:

[0104] Step S31: Form a first patterned photoresist layer 2015 on the intermediate dielectric antireflective layer 2014;

[0105] Step S32: Using the first patterned photoresist layer 2015 as a mask, etch the second electrode layer 2013, the HK material layer 2012, and the first electrode layer 2011.

[0106] In step S31, the specific steps for forming the first patterned photoresist layer 2015 on the intermediate dielectric antireflective layer 2014 include:

[0107] Step S311: Form a photoresist layer on the intermediate dielectric antireflective layer 2014;

[0108] Step S312: Perform photolithography on the photoresist layer to form a first patterned photoresist layer 2015, defining the ferroelectric memory region.

[0109] In step S32, the etching is preferably dry etching, but is not limited thereto.

[0110] Conventional dry etching of metals typically involves five steps: Step 1 – Stable (preparation step), Step 2 – Breakthrough (BT, abrupt change step), Step 3 – Main Etch (ME, the main etching step), Step 4 – OverEtch1 (OE1, the first over-etching step), and Step 5 – OverEtch2 (OE2, the second over-etching step).

[0111] The etching in this embodiment differs from conventional metal etching. The etching in this embodiment only requires two steps, and the specific etching method is as follows:

[0112] Step S321: Set the power of the etching equipment to 0 and maintain it at a preset pressure and preset mixed gas flow rate for a preset duration;

[0113] Step S322: Set the power of the etching equipment to high power mode.

[0114] In step S321, the preset pressure is preferably 6 mT to 10 mT, and the mixed gas is preferably a mixture of one or more halogen-containing gases and inert gases, such as Cl2:BCl3:Ar with a gas ratio of 8:2:7 (Cl2 reference value 75 sccm to 90 sccm), but not limited thereto. The preset duration is preferably the time of Step 1 (preparation step) in conventional dry etching of metals, generally ≤45s, preferably 15s to 30s.

[0115] In step S322, a mixed gas, such as Cl2:BCl3:Ar with a gas ratio of 8:2:7, is used to complete the etching of all structural layers, including the intermediate dielectric antireflective layer 2014, the second electrode layer 2013, the HK material layer 2012, and the first electrode layer 2011. A certain amount of over-etching is added to cause a certain degree of loss in the first dielectric layer 106, so as to ensure that the etching window can meet the process requirements.

[0116] Conventional metal etching does not require a high-power mode due to the chemical nature of the metal etching process; it is usually performed in a normal power mode. However, the etching equipment in this embodiment requires a high-power mode, meaning that the RF required for etching is set to a high-power mode, where the RF power needs to be greater than 850W and the bias power needs to be greater than 120W.

[0117] The intermediate dielectric antireflective layer 2014, the second electrode layer 2013, the HK material layer 2012, and the first electrode layer 2011 are photolithographically etched to define a ferroelectric memory region. The first electrode layer 2011 of the ferroelectric memory region serves as the lower electrode, the HK material layer 2012 of the ferroelectric memory region serves as the intermediate dielectric layer, and the second electrode layer 2013 of the ferroelectric memory region serves as the upper electrode.

[0118] The unique etching method for the ferroelectric memory region in this embodiment, combined with low-temperature (<45°C) etching gases of Cl2, BCl3, and AR, ensures both minimal and easily removable byproducts, and compatibility of the ferroelectric memory region etching method with CMOS metal etching processes. The resulting device exhibits excellent CV electrical performance and PV hysteresis characteristics, as detailed in [reference needed]. Figure 5 and Figure 6 .

[0119] After photolithography and etching of the intermediate dielectric antireflective layer 2014, the second electrode layer 2013, the HK material layer 2012, and the first electrode layer 2011, the fabrication method further includes: performing an ashing and stripping process on the first patterned photoresist layer 2015 to remove the first patterned photoresist layer 2015. The ashing and stripping process removes the photoresist and etching byproducts simultaneously.

[0120] After performing an ashing and stripping process on the first patterned photoresist layer 2015, the process may further include:

[0121] A second dielectric layer 202 is formed, and the second dielectric layer 202 covers the first dielectric layer 106 and the upper electrode. The second dielectric layer 202 includes, from bottom to top, a silicon nitride layer, a second plasma-enhanced oxide film, and a top dielectric anti-reflection layer.

[0122] A second conductive plug 1043 is formed, which extends from the upper surface of the second dielectric layer 202 through the top dielectric antireflective layer, the second plasma-enhanced oxide film, and the silicon nitride layer, and is then electrically connected to the upper electrode.

[0123] The method for forming the second dielectric layer 202 includes:

[0124] A Si3N4 layer is formed on the intermediate dielectric antireflective layer 2014 and the first dielectric layer 106, and the thickness of the Si3N4 layer is preferably...

[0125] A second plasma-enhanced oxide film is formed on the Si3N4 layer, and the thickness of the second plasma-enhanced oxide film is preferably...

[0126] A top dielectric antireflective layer is formed on the second plasma-enhanced oxide film, and the thickness of the top dielectric antireflective layer is preferably...

[0127] The method for forming the second conductive plug 1043 includes:

[0128] A second patterned photoresist layer is formed on the second dielectric layer 202;

[0129] The second dielectric layer 202 is etched using the second patterned photoresist layer as a mask to form the second via of the second dielectric layer 202;

[0130] The second through-hole is filled and chemically mechanically masked to form the second conductive plug 1043.

[0131] The material of the second conductive plug 1043 is preferably tungsten, but it is not limited to this. The number and position of the second conductive plug 1043 can be set according to process requirements. For example, Figure 2 In this configuration, there are two second conductive plugs 1043, one located in the unit area A and the other located in the peripheral area B. The second conductive plug 1043 located in the unit area A is connected to the upper electrode, and the second conductive plug 1043 located in the peripheral area B is electrically connected to the first conductive plug 1042.

[0132] After forming the second conductive plug 1043 in the second dielectric layer 202, the remaining CMOS back-end process steps are completed to fabricate the MIM device structure. For example, the formation of the second metal layer 301. That is, after forming the second conductive plug 1043 in the second dielectric layer 202, the formation of the second metal layer 301 on the second dielectric layer 202 may also be included. A portion of the second metal layer 301 is located in the cell region A, serving as the electrode line PL, and this second metal layer 301 is connected to the upper electrode through the second conductive plug 1043. The remaining portion of the second metal layer 301 is located in the peripheral region B, and is electrically connected to the first metal layer 105 in the peripheral region B through the second conductive plug 1043 and the first conductive plug 1042.

[0133] The MIM device structure fabrication method provided by this invention is compatible with traditional CMOS manufacturing lines and does not pollute the production line, resulting in high-performance devices and effectively improving device yield, reliability, and market competitiveness. Furthermore, the unique etching method for the ferroelectric storage region of this invention, combined with the use of low-temperature (<45°C) etching gases Cl2, BCl3, and AR, ensures minimal and easily removed byproducts while maintaining compatibility with CMOS metal etching processes. The resulting device exhibits excellent CV electrical performance and PV hysteresis characteristics. Therefore, this invention successfully develops MIM devices based on traditional CMOS devices that incorporate novel ferroelectric materials (i.e., HighK materials, or HK materials, high-k materials, high-dielectric-coefficient materials, such as HfO2) on CMOS production lines, and develops a ferroelectric storage region etching program compatible with CMOS metal etching processes. In addition, the above fabrication method can produce 3D highly integrated and high-performance MIM device structures, effectively improving device yield, reliability, and market competitiveness.

[0134] Furthermore, it is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0135] Furthermore, it should be understood that the invention is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which can vary. It should also be understood that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a,” “an,” and “the” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. Thus, for example, a reference to “a step” means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in the broadest sense. Therefore, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive”, unless the context clearly indicates otherwise. Structures described herein will be understood to also refer to functional equivalents of that structure. Language that can be interpreted as approximate should be understood in that way unless the context clearly indicates otherwise.

Claims

1. A method for fabricating a MIM device structure, characterized in that, Includes the following steps: A semiconductor substrate is provided, on which a first dielectric layer is formed, and a first conductive plug is formed in the first dielectric layer; A first electrode layer, an HK material layer, and a second electrode layer are sequentially formed on the first dielectric layer, and the first electrode layer is electrically connected to the first conductive plug. Photolithography is used to etch the first electrode layer, the HK material layer, and the second electrode layer to define a ferroelectric memory region. The first electrode layer of the ferroelectric memory region serves as the lower electrode, the HK material layer of the ferroelectric memory region serves as the intermediate dielectric layer, and the second electrode layer of the ferroelectric memory region serves as the upper electrode. The etching method for the first electrode layer, the HK material layer, and the second electrode layer includes only the following steps: setting the power of the etching equipment to 0 and maintaining it at a preset pressure and a preset mixed gas flow rate for a preset time; setting the power of the etching equipment to a high-power mode; and the temperature of the etching method is <45°C.

2. The method for fabricating the MIM device structure as described in claim 1, characterized in that, The material of the HK material layer includes HfO2.

3. The method for fabricating the MIM device structure as described in claim 1, characterized in that, Before photolithography and etching of the first electrode layer, the HK material layer and the second electrode layer, the method includes: forming an intermediate dielectric antireflection layer on the second electrode layer; The photolithography and etching of the first electrode layer, the HK material layer, and the second electrode layer includes: A first patterned photoresist layer is formed on the intermediate dielectric antireflective layer; Using the first patterned photoresist layer as a mask, the intermediate dielectric antireflective layer, the second electrode layer, the HK material layer, and the first electrode layer are etched.

4. The method for fabricating the MIM device structure as described in claim 1, characterized in that, The photolithography and etching of the first electrode layer, the HK material layer, and the second electrode layer includes: The first dielectric layer is etched over a portion, and the thickness of the portion of the first dielectric layer is 15% to 30% of the total thickness of the first electrode layer, the HK material layer and the second electrode layer.

5. The method for fabricating the MIM device structure as described in claim 1, characterized in that, The preset pressure is 6mT~10mT.

6. The method for fabricating the MIM device structure as described in claim 1, characterized in that, The mixed gas includes a mixture of one or more halogenated gases and inert gases.

7. The method for fabricating the MIM device structure as described in claim 6, characterized in that, The mixed gas comprises Cl2: BCl3:Ar in a gas ratio of 8:2:

7.

8. The method for fabricating the MIM device structure as described in claim 1, characterized in that, The photolithography and etching of the first electrode layer, the HK material layer, and the second electrode layer define a ferroelectric memory region. The first electrode layer of the ferroelectric memory region serves as the lower electrode, the HK material layer of the ferroelectric memory region serves as the intermediate dielectric layer, and the second electrode layer of the ferroelectric memory region serves as the upper electrode. The etching equipment adopts a high-power mode, wherein the high-power mode is characterized by an RF power greater than 850W and a bias power greater than 120W.

9. The method for fabricating the MIM device structure as described in claim 1, characterized in that, The process of photolithography and etching the first electrode layer, the HK material layer, and the second electrode layer to define the ferroelectric memory region, wherein the first electrode layer of the ferroelectric memory region serves as the lower electrode, the HK material layer of the ferroelectric memory region serves as the intermediate dielectric layer, and the second electrode layer of the ferroelectric memory region serves as the upper electrode, includes: A second dielectric layer is formed, and the second dielectric layer covers the first dielectric layer and the upper electrode. The second dielectric layer includes, from bottom to top, a silicon nitride layer, a second plasma-enhanced oxide film, and a top dielectric anti-reflection layer. A second conductive plug is formed, which sequentially penetrates the top dielectric antireflective layer, the second plasma-enhanced oxide film, and the silicon nitride layer from the upper surface of the second dielectric layer and is then electrically connected to the upper electrode.

10. The method for fabricating the MIM device structure as described in claim 1, characterized in that, The first dielectric layer, from bottom to top, comprises a silicon-rich oxide thin film, a fluorinated silicon glass, a first plasma-enhanced oxide film, and a bottom dielectric anti-reflection layer. The semiconductor substrate, on which the first dielectric layer is formed, and prior to the formation of the first conductive plug in the first dielectric layer, includes: Transistors are pre-formed on the semiconductor substrate; A bottom dielectric layer is formed, which covers the semiconductor substrate and the transistor; A first metal layer is formed on the bottom dielectric layer, and a bottom conductive plug is formed through the bottom dielectric layer. The first metal layer is electrically connected to one electrode of the transistor via the bottom conductive plug.

11. The method for fabricating the MIM device structure as described in claim 1, characterized in that, The step of sequentially forming a first electrode layer, an HK material layer, and a second electrode layer on the first dielectric layer includes: TiN material was deposited using physical vapor deposition to form the first TiN layer; Atomic layer deposition is used to deposit TiN material on the first TiN layer to form a second TiN layer. The first TiN layer and the second TiN layer constitute the first electrode layer. An atomic layer deposition process is used to deposit HK material on the second TiN layer to form the HK material layer; TiN material was deposited on the HK material layer using a physical vapor deposition process to form a third TiN layer; Atomic layer deposition (ALD) is used to deposit TiN material on the third TiN layer to form a fourth TiN layer. The third TiN layer and the fourth TiN layer together form the second electrode layer.

12. The method for fabricating the MIM device structure as described in claim 11, characterized in that, The thickness of the first TiN layer is 200 Å to 300 Å, and the thickness of the second TiN layer is 65 Å to 75 Å; and / or, The thickness of the third TiN layer is 200 Å to 300 Å, and the thickness of the fourth TiN layer is 65 Å to 75 Å; and / or, The thickness of the HK material layer is 90 Å to 100 Å.

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