Clock tree architecture, clock signal transmission method and device

Abstract

The application provides a clock tree architecture, a clock signal transmission method and equipment. The clock tree architecture comprises a clock source, a frequency divider and a clock tree. The clock source is used to generate a clock signal. The frequency divider is used to reduce a target clock frequency of the clock signal generated by the clock source to a first clock frequency to obtain a to-be-transmitted clock signal. The first clock frequency is half of the target frequency. The clock tree is used to receive the to-be-transmitted clock signal and transmit the to-be-transmitted clock signal to a target module. A timing logic circuit of the clock tree is implemented by using double-edge registers and double-edge gate units. The application can save power consumption of clock signal transmission, enhance reliability of clock signal transmission and have higher applicability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a clock network, a clock signal transmission method and equipment. BACKGROUND

[0002] With the increase of chip size and the increase of clock frequency, the long-distance transmission of high-frequency clock signals may cause risks of clock signal integrity, and the delay of long-distance transmission of high-frequency clock signals may also cause difficulties in timing convergence of global synchronization design. At the same time, for a large-scale digital system chip (SOC), the power consumption on the clock will also increase significantly. Therefore, as Figure 1 the industry usually adopts H clock tree (H-tree) technology to enhance the quality of clock signals by using specially customized clock tree buffer units (triangles in the figure) and high-level metal traces, while significantly reducing the delay of the clock tree and the cost of timing convergence of global synchronization design. However, the specially customized clock tree buffer and high-level metal trace will significantly increase the power consumption of the clock tree, and the risk of clock signal integrity will increase significantly after the continuous increase of clock frequency.

[0003] The present application provides a clock tree architecture, a clock signal transmission method and equipment, which can save the power consumption of clock signal transmission, enhance the reliability of clock signal transmission, and have higher applicability. Figure 2 In the prior art, low-frequency clock signals are directly generated by a clock source, and after the low-frequency clock signals are transmitted to modules (such as module 1 and module 2) that need to use the clock signals, high-frequency clock signals (such as high-frequency clock signal 1 and high-frequency clock signal 2) are generated in the modules through frequency multiplication circuits (such as frequency multiplication circuit 1 and frequency multiplication circuit 2). However, the cost of generating high-frequency clock signals in the modules is high, which leads to a significant increase in the power consumption of the chip, and the high-frequency clock signals generated by different modules are difficult to synchronize, which has poor applicability. SUMMARY

[0004] The present application provides a clock tree architecture, a clock signal transmission method and equipment, which can save the power consumption of clock signal transmission, enhance the reliability of clock signal transmission, and have higher applicability.

[0005] In a first aspect, the application provides a clock tree architecture, which comprises a clock source, a frequency divider and a clock tree. The clock source is configured to generate a clock signal, the frequency divider is configured to reduce a target clock frequency of the clock signal generated by the clock source to a first clock frequency to obtain a to-be-transmitted clock signal. The first clock frequency is half of the target clock frequency. The clock tree is configured to receive the to-be-transmitted clock signal and transmit the to-be-transmitted clock signal to a target module. The clock tree is implemented by using double-edge registers and double-edge gating units. In the application, the high-frequency clock signal generated by the clock source can be adjusted to a half-frequency clock signal by the frequency divider. The half-frequency clock signal can be transmitted on the clock tree to save the power consumption of clock signal transmission. The clock tree is implemented by using double-edge registers and double-edge gating units, so that the half-frequency clock transmission has engineering practicability, the reliability of clock signal transmission is enhanced, and the applicability is higher.

[0006] In combination with the first aspect, in a first possible implementation manner, the target module comprises a clock pulse width adjustable frequency multiplier, which is configured to adjust the clock frequency of the to-be-transmitted clock signal from the first clock frequency to the target frequency. In the application, the frequency multiplier in the target module is used to generate a frequency-multiplied clock signal, so that the synchronization of different frequency multipliers can be realized, the power consumption of the frequency multiplier can be reduced, the reliability of half-frequency clock signal transmission is enhanced, and the applicability is higher.

[0007] In combination with the first possible implementation manner of the first aspect, in a second possible implementation manner, the clock pulse width adjustable frequency multiplier comprises a delay selection end and at least one pulse width adjustment unit. The number of pulse width adjustment units can be determined according to the bit width adjustment requirement of the delay selection. The input signal of the delay selection end can be used to determine whether to access the pulse width adjustment unit or bypass the pulse width adjustment unit, so that the high-level pulse width of the frequency-multiplied clock signal can be adjusted, the operation is flexible, and the applicability is high.

[0008] In combination with the second possible implementation manner of the first aspect, in a third possible implementation manner, the pulse width adjustment unit comprises a plurality of buffers or a plurality of inverters. In the application, the number of buffers or inverters in the pulse width adjustment unit can be determined according to the adjustment requirement of the high pulse width of the frequency-multiplied clock signal. The number of buffers or inverters in the pulse width adjustment unit can be flexibly adjusted, and the applicability is high.

[0009] In a fourth possible implementation manner of the first aspect, the target module includes a target double-edge gate unit and a target double-edge register, and the timing logic circuit of the target module is implemented by the target double-edge gate unit and the target double-edge register. In the present application, the target module can receive the half-frequency clock signal transmitted on the clock tree through the double-edge gate unit and the double-edge register, and the timing logic circuit of the target module is implemented based on the double-edge gate unit and the double-edge register of the target module, so that the function of the target module can be implemented based on the half-frequency clock signal, without the need of a frequency multiplier, and the structure of the target module is simple and highly applicable.

[0010] In the second aspect, the present application provides a clock signal transmission method, which is applicable to the frequency divider in the clock tree architecture provided in any one of the first aspect to the fourth possible implementation manner of the first aspect. The method comprises: receiving a clock signal from a clock source; and reducing the target clock frequency of the clock signal generated by the clock source to a first clock frequency to obtain a to-be-transmitted clock signal. Here, the first clock frequency is half of the target clock frequency. The to-be-transmitted clock signal is input into the clock tree, and the to-be-transmitted clock signal is transmitted to the target module through the clock tree. Here, the timing logic circuit of the clock tree is implemented by using a double-edge register and a double-edge gate unit.

[0011] In the first possible implementation manner of the second aspect, the method further comprises adjusting the clock frequency of the to-be-transmitted clock signal from the first clock frequency to the target frequency by using the clock pulse-width adjustable frequency multiplier of the target module.

[0012] In the second possible implementation manner of the second aspect, the method further comprises receiving the to-be-transmitted clock signal by using the target double-edge gate unit and the target double-edge register included in the target module, so as to implement the timing logic circuit of the target module by using the target double-edge gate unit and the target double-edge register.

[0013] In the third aspect, the present application provides a chip, which comprises the clock tree architecture provided in any one of the first aspect to the fourth possible implementation manner of the first aspect.

[0014] In the fourth aspect, the present application provides an electronic device, which comprises the clock tree architecture provided in any one of the first aspect to the fourth possible implementation manner of the first aspect or the chip provided in the third aspect.

[0015] In the present application, the high-frequency clock signal generated by the clock source can be adjusted to a half-frequency clock signal by using the frequency divider, and the half-frequency clock signal can be transmitted on the clock tree, so as to save the power consumption of the clock signal transmission. Meanwhile, the timing logic circuit of the clock tree is implemented based on the double-edge register and the double-edge gate unit, so that the half-frequency clock transmission has engineering practicability, the reliability of the clock signal transmission is enhanced, and the applicability is higher. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a structural diagram of a clock tree;

[0017] Figure 2 is another structural diagram of a clock tree;

[0018] Figure 3 is a structural diagram of a clock tree architecture provided by the present application;

[0019] Figure 4 is a waveform diagram of a frequency divider provided by the present application;

[0020] Figure 5 is a structural diagram of a clock tree architecture and a conventional clock tree architecture provided by the present application;

[0021] Figure 6 is a timing model diagram of a single-edge register;

[0022] Figure 7 is a timing check diagram of a send register and a capture register;

[0023] Figure 8 is a timing model diagram of a double-edge register provided by the present application;

[0024] Figure 9 is a structural diagram of a timing check between a double-edge register and a double-edge gated cell;

[0025] Figure 10 is a diagram of a timing check between a double-edge register and a double-edge gated cell;

[0026] Figure 11 is another diagram of a timing check between a double-edge register and a double-edge gated cell;

[0027] Figure 12 is a timing check diagram between a double-edge register and a single-edge register;

[0028] Figure 13 is a timing check diagram between a single-edge register and a double-edge register / gated cell;

[0029] Figure 14 is a corresponding relationship diagram between a double-edge register and a double-edge gated cell and a pseudo single-edge register and a pseudo single-edge gated cell;

[0030] Figure 15 is a design flow diagram of a digital integrated circuit provided by the present application;

[0031] Figure 16 is a circuit diagram of a conventional clock frequency multiplication unit;

[0032] Figure 17 is a circuit schematic diagram of a clock pulse width adjustable frequency multiplier provided by the present application;

[0033] Figure 18 is another structural schematic diagram of a clock tree architecture provided by the present application;

[0034] Figure 19 is another structural schematic diagram of a clock tree architecture provided by the present application;

[0035] Figure 20 is another structural schematic diagram of a clock tree architecture provided by the present application;

[0036] Figure 21 is a flow schematic diagram of a clock signal transmission method improved by the present application. DETAILED DESCRIPTION

[0037] The clock tree architecture provided by the present application can be applied to a large digital SOC, which can be applied to a computer system or a server, which can operate with numerous other general-purpose or special-purpose computing systems, environments or configurations. Here, the computing systems, environments and / or configurations suitable for use with the computer system or server described above include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, minicomputer systems, mainframe computer systems and distributed cloud computing technology environments including any of the above systems, and the like. Here, the computer system or server can be described in the general context of computer system executable instructions, such as program modules, executed by the computer system. Generally, program modules can include routines, programs, objects, components, logic, data structures, and the like, which perform specific tasks or implement specific abstract data types. The computer system or server can be implemented in a distributed cloud computing environment, in which tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media, including storage devices.

[0038] Referring to Figure 3 , Figure 3 is a structural schematic diagram of a clock tree architecture provided by the present application. In the clock tree architecture provided by the present application, a clock source, a frequency divider and a clock tree are included, which can reduce the clock frequency to half of the target clock frequency when transmitting the clock at a long distance, can significantly reduce the dynamic power consumption of the clock tree, and enhance the reliability of clock signal transmission. As shown in Figure 3As shown, in the clock tree architecture provided in this application, the clock source is connected to a frequency divider, and then connected to the clock tree via the frequency divider. The clock signal generated by the clock source can output a clock signal to be transmitted after passing through the frequency divider. The clock tree can then transmit the signal to be transmitted to the target module (such as module 1 and module 2). The sequential logic circuits of the clock tree are implemented using dual-edge registers and dual-edge gate units. Here, the clock source can be a phase-locked loop (PLL), or other functional modules besides the PLL used to generate clock signals. The specific choice depends on the actual application scenario and is not limited here. It can be understood that the clock source is used to generate clock signals. At this time, the clock signal generated by the clock source can be a high-frequency clock signal. For ease of description, it can be assumed that the clock frequency of the clock signal generated by the clock source is the target frequency. That is to say, in the clock tree architecture provided in this application, the clock source can directly generate a high-frequency clock signal without directly generating a low-frequency clock. This avoids the impact of the non-1:1 duty cycle of the clock output clock on the clock of subsequent circuits in the clock tree architecture, making the operation simple and highly applicable.

[0039] In some feasible implementations, a frequency divider is added to the high-frequency clock output. This frequency divider halves the clock frequency of the high-frequency clock signal generated by the clock source, resulting in a half-frequency clock signal. Specifically, after the clock source generates a high-frequency clock signal, this signal can be output to a frequency divider. The frequency divider reduces the clock frequency of the high-frequency clock signal generated by the clock source to half the target frequency, thus obtaining the clock signal to be transmitted. In other words, the clock frequency of the clock signal to be transmitted is half the target frequency. Here, the frequency divider can be a register divider, where the waveform allocated by the register is as follows... Figure 4 As shown. Figure 4 This is a waveform diagram of the frequency divider provided in this application. For example... Figure 4 As can be seen from the waveform of the frequency divider, the transitions of the output clock Q are all generated by the rising edge of the input clock CLK. Common electronic design automation (EDA) tools can accurately calculate the change in the output clock duty cycle caused by the frequency divider. It is understandable that in practical applications, other types of frequency dividers besides register allocation can be used, as long as they can avoid the impact of a non-1:1 duty cycle of the clock source output clock on the clock of subsequent circuits. Therefore, the type of frequency divider can be selected based on the actual application scenario and is not restricted here.

[0040] In some feasible implementations, after the frequency divider processes the high-frequency clock signal generated by the clock source into a clock signal with a frequency only half that of the target frequency, the clock signal can be input into the clock tree. The clock tree then transmits the clock signal to the target module. Converting the transmission of the high-frequency clock signal into a half-frequency clock signal (i.e., a clock signal with a frequency half that of the target frequency) reduces the power consumption of clock signal transmission and enhances the reliability of clock signal transmission. In other words, the clock tree can receive the clock signal to be transmitted from the frequency divider and transmit it to the target module. Here, the target module can be any functional module in a computer system and / or server used to perform specific tasks and driven by the clock transmitted from the clock tree. The specific module can be determined according to the actual application scenario and is not limited here.

[0041] In some feasible implementations, the clock frequency of the clock signal to be transmitted output by the frequency divider is half of the target frequency. In this case, in order to better transmit the clock signal to the target module, the sequential logic circuits carried on the clock tree can be implemented using dual-edge registers and dual-edge gate units. This makes the transmission of the half-frequency clock signal on the clock tree more practical in engineering and has greater applicability. See also Figure 5 , Figure 5 This is a schematic diagram of the clock tree architecture provided in this application and a traditional clock tree architecture. For example... Figure 5 As shown, in a traditional clock tree architecture, a clock source generates a high-frequency clock signal and inputs it into a full-frequency clock tree. The full-frequency clock tree then transmits the high-frequency clock signal to modules (such as module 1 and module 2). The sequential logic circuits carried on the full-frequency clock tree are implemented using registers and gating units. However, long-distance transmission of high-frequency clock signals on the full-frequency clock tree can introduce clock signal integrity risks. The clock tree architecture provided in this application can convert the long-distance transmission of high-frequency clock signals on the full-frequency clock tree into the transmission of half-frequency clock signals on the half-frequency clock tree. In this case, the sequential logic circuits on the half-frequency clock tree can be implemented using dual-edge registers and dual-edge gating units, which can enhance the feasibility of half-frequency clock signal transmission and save power consumption during clock signal transmission.

[0042] In some feasible implementations, because the transmission distance of the half-frequency clock signal on the clock tree is relatively long and the sequential logic circuits of the divided clock are widely distributed, the half-frequency clock is usually without sequential logic circuits to reduce design complexity. If, in practical applications, the half-frequency clock does indeed require sequential logic circuits from a functional design perspective, then to ensure that the logic function of the sequential logic circuits is consistent with that in the full-frequency clock signal transmission mode, the clock frequency of the sequential logic circuits at different locations must be restored from the half-frequency to the full-frequency. However, this implementation method leads to the addition of a large number of clock multiplier units to the clock tree architecture, resulting in a significant increase in the power consumption of the clock tree architecture, making long-distance transmission of the half-frequency clock signal impractical in engineering. In the clock tree architecture provided in this application, the sequential logic circuits carried on the half-frequency clock tree can be implemented using dual-edge registers and dual-edge gate units, avoiding the addition of a large number of clock multiplier units to the clock tree architecture, thus offering high applicability.

[0043] In some feasible implementations, different models can be used for registers and gated units at different design and implementation stages in the integrated circuit design and implementation process. Therefore, in the clock tree architecture design and implementation process provided in this application, the aforementioned dual-edge registers and dual-edge gated units can be modeled, and modeled as two corresponding models, including one model as a real dual-edge register and dual-edge gated unit, and the other model as a pseudo-single-edge register and pseudo-single-edge gated unit model. Here, the pseudo-single-edge register and pseudo-single-edge gated unit can be understood as virtual single-edge registers and virtual single-edge gated units. The pseudo-single-edge register and pseudo-single-edge gated unit are virtual models (or pseudo-models) designed to implement the functions of real dual-edge registers and dual-edge gated units, and this pseudo-model is modeled in the same way as the traditional register and gated unit models. In the specific design and implementation process, the types of models required for traditional registers and gating units can include functional models, timing models, physical models, and Scan test models (as shown in the first column of Table 1, which is a modeling relationship table for traditional registers and gating units, dual-edge registers and dual-edge gating units, and pseudo-single-edge registers and pseudo-single-edge gating units). The models required for dual-edge registers and dual-edge gating units, and pseudo-single-edge registers and pseudo-single-edge gating units, as well as the model building methods, are not entirely the same as those required for traditional registers and gating units, as shown in Table 1 below:

[0044] Table 1

[0045]

[0046] As shown in Table 1, in the traditional register and gating unit model types, functional modules can be implemented using the industry-leading Very-High-Speed ​​Integrated Circuit Hardware Description Language (VHDL) or Verilog, timing models can be implemented using timing libraries, physical models can be implemented using the Library Exchange Format (LEF), and test models can be implemented using the Scan test model. It is understood that the implementation method of each model in the above-mentioned traditional register and gating unit models can be determined according to the actual application scenario, and no restrictions are imposed here. For dual-edge registers and dual-edge gating units, the functional model can also be implemented using the industry-leading VHDL or Verilog, the timing model can use the timing modeling method provided in this application, and there is no need to establish a physical model (i.e., the physical model is empty) and a test model (i.e., the test model is empty). As shown in Table 1, for pseudo-single-edge registers and pseudo-single-edge gating units, the models that need to be established also include a functional model, a timing model, a physical model, and a test model. Similarly, functional modules can be implemented using industry-standard VHDL or Verilog languages, timing models can be implemented using industry-standard register description methods, physical models only contain the information required for physical implementation and do not include dual-edge information, and these physical models can be implemented using industry-standard physical model description methods. Test models are used to generate test logic and test vectors, and these test models can be implemented using the Scan test model. Furthermore, the implementation methods for each model required for pseudo-single-edge registers and pseudo-single-edge gating units can be determined according to the actual application scenario and are not restricted here.

[0047] In some feasible implementations, see Figure 6 , Figure 6 This is a schematic diagram of the timing model of a single-edge register. For example... Figure 6 As shown, the timing model of a traditional register (i.e., a single-edge register) typically includes the following timing information (Timing Arcs):

[0048] 1. Clock (CLK) and input data (D) setup time;

[0049] 2. Clock (CLK) and input data (D) hold time;

[0050] 3. Clock (CLK) to output data (Q) output time (CLK-to-Q delay, or simply output time).

[0051] Traditional timing checks for digital integrated circuits primarily involve setup time and hold time checks. These checks occur between the preceding register (such as the transmit register, or launch register) and the following register (such as the capture register). See also Figure 7 , Figure 7 This is a timing check diagram of the transmit register and capture register. (Example) Figure 7 As shown, the output data Q1 of the transmit register is connected to the input data D2 of the capture register. Assume both the transmit and capture registers are rising-edge triggered registers, such as... Figure 7 As shown, timing checks of the transmit register and capture register may include checks on the setup time and hold time corresponding to the transmit register to the capture register. The arrowed curves labeled setup time and hold time represent checks on the setup time and hold time corresponding to the transmit register to the capture register.

[0052] In some feasible implementations, the timing model of the dual-edge register provided in this application can establish two sets of timing checks for two different clock edges (including rising and falling edges), wherein each set of timing checks includes setup time checks and hold time checks. See Figure 8 , Figure 8 This is a schematic diagram of the timing model of the dual-edge register provided in this application. For example... Figure 8 As shown, the timing model of the dual-edge register provided in this application includes a rising-edge triggered timing model. Figure 8 (shown by the dashed line) and the timing model triggered by the falling edge ( Figure 8 (As shown by the solid line), and both the rising edge-triggered timing model and the falling edge-triggered timing model include the following timing information:

[0053] 1. Clock (CLK) and input data (D) setup time;

[0054] 2. Clock (CLK) and input data (D) hold time;

[0055] 3. Clock (CLK) to output data (Q) output time.

[0056] In some feasible implementations, since there are currently no timing analysis tools in the industry that directly target dual-edge registers and dual-edge gated units, the timing modeling provided in this application can utilize commonly used timing analysis tools (hereinafter referred to as timing analysis tools) to achieve the purpose of timing checks for dual edges. Specific proof is as follows:

[0057] Assuming that the timing modeling implementation provided in this application simultaneously includes dual-edge registers, dual-edge gating units, traditional single-edge registers, and traditional single-edge gating units, then in a practical design, the following two timing checks related to dual-edge registers may exist:

[0058] 1) Timing check between dual-edge registers and dual-edge gated units

[0059] See Figure 9 , Figure 9 This is a schematic diagram illustrating the timing check structure between the dual-edge register and the dual-edge gating unit. (Example:) Figure 9 As shown, assuming the transmit register is a dual-edge register and the capture register is a dual-edge register / gating unit, the output data Q1 of the transmit register is connected to the input data D2 of the capture register. Since a dual-edge register can be triggered on both the rising and falling edges, timing checks need to consider both in-phase and out-of-phase clocks for the Launch and Capture registers. See [link to relevant documentation] Figure 10 , Figure 10 This is a schematic diagram of timing checks between a dual-edge register and a dual-edge gate cell. For example... Figure 10 As shown in Figure a, when the clocks of the Launch register and the Capture register are in phase, the timing analysis tool will perform four different setup time (setup) / hold time (hold) timing checks for the timing modeling of the aforementioned dual-edge registers, represented by four different lines. Figure 10 The 'b' indicates the correct setup time / hold time timing check required for a dual-edge register / gated unit. It can be seen that the timing analysis tool's check can cover the correct timing checks required for dual-edge registers / gated units. In other words, timing checks for dual-edge registers can be achieved using traditional timing analysis tools combined with timing modeling methods. The case of inverted clocks for Launch and Capture registers is similar to that of in-phase clocks. See also... Figure 11 , Figure 11 This is another schematic diagram illustrating the timing check between the dual-edge register and the dual-edge gate cell. For example... Figure 11 As shown, timing analysis tools can cover the correct timing checks required for dual-edge registers / gated units. Similarly, it can be seen that for cases where the clocks of the Launch and Capture registers are out of phase, timing checks for dual-edge registers can still be achieved using traditional timing analysis tools combined with timing modeling methods.

[0060] 2) Timing check between dual-edge registers / dual-edge gates and single-edge registers / single-edge gates.

[0061] There are two possible scenarios for checking between dual-edge registers / gating units and traditional single-edge registers: one is that the Launch register (i.e., the transmit register) is a dual-edge register, and the Capture register (i.e., the capture register) is a single-edge register, such as... Figure 12 , Figure 12 This is a timing check diagram between dual-edge registers and single-edge registers. In another scenario, the Launch register is a single-edge register, and the Capture register is a dual-edge register / gating unit, such as... Figure 13 , Figure 13 This is a timing check diagram between single-edge registers and dual-edge registers / gated units. As can be seen, for the timing modeling of the aforementioned dual-edge registers / gated units, the setup time / hold time check by the timing check tool is the correct timing check method.

[0062] In some feasible implementations, different models are used at different stages of the design for dual-edge registers / dual-edge gated units. See also Figure 14 , Figure 14 This is a diagram showing the correspondence between dual-edge registers and dual-edge gating units and pseudo-single-edge registers and pseudo-single-edge gating units. For convenience, as shown... Figure 14 As shown, shaded boxes represent real two-edge registers and real two-edge gated cell models, while unshaded boxes represent pseudo-single-edge registers and pseudo-single-edge gated cell models. The following mainly describes how to utilize these models at various stages of digital integrated circuit design, enabling two-edge registers and two-edge gated cells to be used for functions and DFT logic within the clock tree.

[0063] See Figure 15 , Figure 15 This is a design flowchart of the digital integrated circuit provided in this application. Figure 15 As shown, the design flow of digital integrated circuits includes logic design, functional verification, logic synthesis, formal verification and timing analysis of logic synthesis, design for testability, formal verification and timing analysis of design for testability, physical design, test vector generation, and physical verification and test vector verification. The design flow for each of these parts includes:

[0064] 1) First, start with the logic function design, such as logic design based on pseudo-single-edge registers.

[0065] This part is usually described using classic industry languages ​​such as Verilog or VHDL.

[0066] 2) After the logic design is completed, functional verification will be performed on the logic design.

[0067] 3) After the functional verification is completed, logic synthesis will be performed.

[0068] At this point, the Verilog hardware description language code can be used to convert the design into logic gates.

[0069] 4) After logic synthesis, formal verification and timing analysis will be performed, followed by design for testability.

[0070] After testability design, formal verification and timing analysis will be performed on the testability design.

[0071] 5) After the testability design is inserted, physical design will be performed. After the physical design is implemented, formal verification will be performed. Finally, the design will be converted into the final file required by the manufacturing plant. At the same time, test vectors will be generated on the final logical netlist.

[0072] like Figure 15 As shown, formal verification and timing analysis are integrated throughout the entire design process. Formal verification ensures functional consistency across different stages of design implementation; timing analysis ensures that the timing of the entire design meets the original design requirements. Furthermore, netlist functional simulation and DFT vector verification, netlist functional simulation, post-simulation, and test vector verification are used to ensure the correctness of the logic function and test vectors. Physical verification and power integrity analysis ensure the correctness of the physical implementation.

[0073] In some feasible implementations, since there is no implementation flow for dual-edge registers and dual-edge gates in the industry, the use of dual-edge registers and dual-edge gates can be achieved by using the different implementation flows of dual-edge registers and dual-edge gates models at different stages provided in this application, with the help of traditional digital integrated circuit design flow.

[0074] During the design and implementation phase, timing analysis in all stages, including logic design based on pseudo-cell registers, functional verification, logic synthesis, design for testability, physical design, test vector generation, and formal verification, adopts the pseudo-single-edge register model, enabling seamless integration of dual-edge registers and dual-edge gated units with traditional process and timing analysis tools.

[0075] The netlist functional simulation, DFT vector verification, test vector verification, physical verification, power integrity analysis, and final timing analysis stages employ real dual-edge register and dual-edge gated unit models.

[0076] The above implementation method enables the half-frequency clock scheme to be directly practical in engineering without the need for additional frequency multiplier circuits. The design and implementation methods for dual-edge registers and dual-edge gated units described above are not limited to the timing logic inherent in half-frequency clocks; they can also be extended to general timing logic designs. The specific application scenario will determine the appropriate approach, and no restrictions are imposed here.

[0077] In some feasible implementations, after the clock tree transmits the half-frequency clock signal to the target module, the target module can restore the clock of the half-frequency clock signal to the full frequency using a clock pulse-width adjustable frequency multiplier. In other words, the target module may include a clock pulse-width adjustable frequency multiplier to adjust the clock frequency of the clock signal to be transmitted from a first clock frequency to the target frequency. Figure 16 , Figure 16 This is a circuit diagram of a traditional clock multiplier unit. (Example:) Figure 16 As shown, traditional clock multiplier units are implemented using delay-XOR units. However, due to variations in pulse width caused by process technology, voltage, and temperature, using only traditional clock multiplier units results in different clock tree lengths after the multiplier due to variations in the number of registers in different multiplier units. This poses a reliability risk for long-distance clock pulse width transmission with traditional multiplier units. Furthermore, if the design has a large voltage range requirement, traditional multiplier units suffer from clock pulse width risks, limiting the usable voltage range of the design. The clock multiplier unit with adjustable clock pulse width provided in this application allows for clock pulse width adjustment and offers high applicability. See [link to relevant documentation]. Figure 17 , Figure 17 This is a circuit diagram of the clock pulse width adjustable frequency multiplier provided in this application. Figure 17 As shown, a clock pulse width adjustable frequency multiplier includes a delay selection terminal and one or more pulse width adjustment units (assuming two pulse width adjustment units). Each pulse width adjustment unit includes multiple buffers or multiple inverters. The input signal from the delay selection terminal determines whether to connect to or bypass the pulse width adjustment unit. For example... Figure 17 As shown, the delay is adjusted via the delay selection terminal (DSEL), as follows. Figure 17 As shown, the delay selection pin can be adjusted to 3 levels using two bits. In actual design, more levels can be added as needed, i.e., by increasing the bit width of DSEL. When DSEL is 00, it is the default level; when DSEL is 01, it increases the pulse width level; when DSEL is 10, it decreases the pulse width level.

[0078] In some feasible implementations, when DSEL is 00, the high pulse width of the multiplied clock is determined by the number of buffers or inverters within the dotted frame. That is, the pulse width adjustment unit shown in the dotted frame is active (connected to the adjustable clock pulse width multiplier), while the buffer within the dashed frame (the pulse width adjustment unit shown in the dashed frame) is bypassed. This setting is the default pulse width setting. When DSEL is 01, both the buffers or inverters within the dotted and dashed frames are active simultaneously. Both the dotted and dashed pulse width adjustment units are connected to the adjustable clock pulse width multiplier and are active at the same time. The high-level pulse width of the multiplied clock reaches its maximum. When DSEL is 10, both the buffers or inverters within the dotted and dashed frames are bypassed. Both the dotted and dashed pulse width adjustment units are bypassed, and the high-level pulse width of the multiplied clock is minimized. Frequency multiplication bypass control can be achieved through the EDGE_MODE signal.

[0079] Default delay (DSEL=00, Figure 17 The number of buffers or inverters in the midpoint frame is determined by the clock frequency. Commonly, the delay can be designed to be half the clock cycle under low voltage. It can also be determined according to the actual design requirements, and there is no restriction here.

[0080] Structure 1 of the target module:

[0081] join Figure 18 , Figure 18 This is another schematic diagram of the clock tree architecture provided in this application.

[0082] In some feasible implementations, such as Figure 18 A clock source (assuming a PLL) generates a high-frequency clock. Before the clock enters the clock tree, it is divided by two. That is, the high-frequency clock signal generated by the clock source can be divided by two to obtain a half-frequency clock signal. The half-frequency clock signal can be input into the clock tree and transmitted to the target module based on the clock tree. At this time, the registers and gating units in the functional logic and DFT OCC logic of the clock tree-driven circuit adopt dual-edge registers and dual-edge gating units. The target module (such as module 1 and module 2) may include a frequency multiplier (such as a clock pulse width adjustable frequency multiplier) to recover the high-frequency clock in module 1 and module 2.

[0083] Structure 2 of the target module:

[0084] See Figure 19 , Figure 19 This is another schematic diagram of the clock tree architecture provided in this application.

[0085] In some feasible implementations, such as Figure 19As shown, this is an application scenario where clock power consumption can be reduced. Figure 19 In the clock tree architecture shown, all clocks use half-frequency mode until the timing unit at the end of the clock tree multiplies and restores the half-frequency clock. The frequency multiplier and register 1 can be applied to target module 1, and the frequency multiplier and register 2 can be applied to target module 2. Because the distance between the frequency multiplier and its associated register unit is very short, the pulse width of the frequency multiplier can be reduced. Optionally, Figure 19 In the clock tree architecture shown, the register following the frequency multiplier can be replaced with a latch, which can be determined according to the actual application scenario and is not restricted here.

[0086] Structure 3 of the target module:

[0087] See Figure 20 , Figure 20 This is another schematic diagram of the clock tree architecture provided in this application.

[0088] In some feasible implementations, this application provides a complete implementation scheme for dual-edge registers and dual-edge gating units. Therefore, dual-edge registers and dual-edge gating units can be directly used in the target module without using frequency multipliers, which is simple to operate and highly applicable. In other words, the target module may include target dual-edge gating units and target dual-edge registers, and the sequential logic circuit of the target module is implemented by target dual-edge gating units and target dual-edge registers. Figure 20 As shown, the dual-edge gating unit and dual-edge register 1 can be applied to target module 1, and the dual-edge gating unit and dual-edge register 2 can be applied to target module 2.

[0089] In this application, a frequency divider is used to adjust the high-frequency clock signal generated by the clock source into a half-frequency clock signal, instead of directly outputting a low-frequency clock from a traditional clock source such as a PLL. This avoids the impact of the non-1:1 duty cycle of the PLL output clock on the clock in subsequent circuits. Transmitting the half-frequency clock signal on the clock tree saves power consumption during clock signal transmission. Furthermore, the timing logic circuit of the clock tree, implemented based on dual-edge registers and dual-edge gating units, makes the half-frequency clock transmission practical in engineering, enhances the reliability of clock signal transmission, and increases its applicability.

[0090] See Figure 21 , Figure 21 This is a flowchart illustrating the clock signal transmission method improved in this application. The clock signal transmission method provided in this application is applicable to the frequency divider in the clock data architecture provided in this application, and the method includes the following steps:

[0091] S210, the frequency divider receives the clock signal from the clock source.

[0092] S211, reduce the target clock frequency of the clock signal generated by the clock source to the first clock frequency to obtain the clock signal to be transmitted.

[0093] Here, the first clock frequency is half of the target clock frequency.

[0094] S212 inputs the clock signal to be transmitted into the clock tree, and transmits the clock signal to the target module through the clock tree.

[0095] Here, the sequential logic circuit of the clock tree is implemented using dual-edge registers and dual-edge gate units.

[0096] In some feasible implementations, the method further includes:

[0097] The clock frequency of the clock signal to be transmitted is adjusted from the first clock frequency to the target frequency by the clock pulse width adjustable frequency multiplier of the target module.

[0098] In some feasible implementations, the method further includes:

[0099] The target module receives the clock signal to be transmitted through the target dual-edge gating unit and the target dual-edge register, and implements the timing logic circuit of the target module through the target dual-edge gating unit and the target dual-edge register.

[0100] In the specific implementation, the implementation methods of each module in each of the above steps can be found in the implementation methods of each functional module in the clock tree architecture provided in this application, and will not be repeated here.

[0101] In this application, the frequency divider can adjust the high-frequency clock signal generated by the clock source into a half-frequency clock signal, instead of directly outputting a low-frequency clock from a traditional clock source such as a PLL. This avoids the impact of the non-1:1 duty cycle of the PLL output clock on the clock in subsequent circuits. Transmitting the half-frequency clock signal on the clock tree can save power consumption during clock signal transmission. At the same time, the timing logic circuit of the clock tree based on dual-edge registers and dual-edge gate units makes the half-frequency clock transmission practical in engineering, enhances the reliability of clock signal transmission, and has greater applicability.

[0102] In some feasible implementations, this application also provides a chip that includes the clock tree architecture provided in this application described above.

[0103] In some feasible implementations, this application provides an electronic device that includes the clock tree architecture or the chip described above.

[0104] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A clock tree architecture, characterized in that, The clock tree architecture includes: Clock source, used to generate clock signals; A frequency divider is used to reduce the target clock frequency of the clock signal generated by the clock source to a first clock frequency to obtain the clock signal to be transmitted. The first clock frequency is half of the target clock frequency. The frequency divider is a register frequency divider. The transition of the output clock of the frequency divider is generated by the rising edge of the input clock signal. The clock tree is used to receive the clock signal to be transmitted and transmit the clock signal to the target module. The timing logic circuit of the clock tree is implemented using a dual-edge register and a dual-edge gate unit.

2. The clock tree architecture according to claim 1, characterized in that, The target module includes a clock pulse width adjustable frequency multiplier, which is used to adjust the clock frequency of the clock signal to be transmitted from a first clock frequency to the target clock frequency.

3. The clock tree architecture according to claim 2, characterized in that, The clock pulse width adjustable frequency multiplier includes a delay selection terminal and at least one pulse width adjustment unit; The input signal of the delay selection terminal is used to determine whether to access the pulse width adjustment unit or bypass the pulse width adjustment unit.

4. The clock tree architecture according to claim 3, characterized in that, The pulse width adjustment unit includes multiple buffers or multiple inverters.

5. The clock tree architecture according to claim 1, characterized in that, The target module includes a target dual-edge gating unit and a target dual-edge register, and the timing logic circuit of the target module is implemented by the target dual-edge gating unit and the target dual-edge register.

6. A clock signal transmission method, characterized in that, The clock signal transmission method is applicable to the clock tree architecture divider according to any one of claims 1-5, and the method includes: Receive clock signals from the clock source; The target clock frequency of the clock signal generated by the clock source is reduced to a first clock frequency to obtain the clock signal to be transmitted, wherein the first clock frequency is half of the target clock frequency; The clock signal to be transmitted is input into the clock tree, and the clock signal to be transmitted is transmitted to the target module through the clock tree. The timing logic circuit of the clock tree is implemented using a dual-edge register and a dual-edge gate unit.

7. The method according to claim 6, characterized in that, The method further includes: The clock frequency of the clock signal to be transmitted is adjusted from the first clock frequency to the target clock frequency by the clock pulse width adjustable frequency multiplier of the target module.

8. The method according to claim 6, characterized in that, The method further includes: The clock signal to be transmitted is received by the target dual-edge gating unit and the target dual-edge register included in the target module, so as to realize the timing logic circuit of the target module through the target dual-edge gating unit and the target dual-edge register.

9. A chip, characterized in that, The chip includes the clock tree architecture as described in any one of claims 1-5.

10. An electronic device, characterized in that, The electronic device includes a clock tree architecture as described in any one of claims 1-5 or a chip as described in claim 9.

Images