Display panel, manufacturing method thereof, and display device

Abstract

The present application relates to a display panel, a manufacturing method thereof, and a display device. The display panel includes an array substrate, a color filter substrate, and a liquid crystal layer. The first fabricated color resist and the second fabricated color resist on the array substrate form a raised area corresponding to the metal layer for arranging a spacer. The metal layer of the array substrate is disposed on the side of the first fabricated color resist and the second fabricated color resist facing away from the liquid crystal layer and corresponds to the spacer for arranging a data line or a scanning line. The insulating layer of the array substrate is disposed on the surfaces of the first fabricated color resist, the spacer, and the second fabricated color resist facing the liquid crystal layer. The conductive layer of the array substrate is disposed on a partial surface of the insulating layer on the side facing away from the first fabricated color resist and the second fabricated color resist. In the display panel of the present application, a spacer is arranged in the raised area, fundamentally solving the problem that the thickness of the overlapping area is small due to the horns existing in the first fabricated color resist and the second fabricated color resist, avoiding a large capacitance between the conductive layer and the data line or the scanning line, and reducing the load of the data line or the scanning line.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a display panel, a display device having the display panel, and a manufacturing method of the display panel. Background Art

[0002] With the update and replacement of e-sports industry projects, e-sports competitions based on e-sports games and with information technology as the core have put forward higher requirements for display devices. In the existing market, the display quality of display devices is often improved by reducing the load of pixels. At the same time, the color filter is disposed on the Array substrate (Color Filter on Array, COA) technology, or the COA technology is combined with the technology of disposing spacers on the Array substrate (PS on Array, POA) to achieve the design of an e-sports screen compatible with a curved screen.

[0003] In the current COA technology, to adapt to the curved screen design, there is no Black Matrix (BM) design on the data line (Dataline). The signal of the data line is mainly shielded by setting a DBS (Dataline BM Less, no black matrix above the data line) conductive layer to achieve the light-shielding effect. However, the color filter has a tap angle, and the adjacent two color filters are relatively thin at the overlapping position. The insulating layer disposed on the color filter is also very thin, which results in a very close distance between the DBS conductive layer at the overlapping position and the data line, generating a large capacitance, and further causing the problem of increased loading of the data line.

[0004] Therefore, how to solve the problem that in the curved screen design of the prior art, due to the relatively thin thickness of the color filter at the overlapping position, the distance between the DBS conductive layer at this overlapping position and the data line is relatively close, resulting in an increased load on the data line is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the deficiencies of the prior art, the purpose of the present application is to provide a display panel, a manufacturing method thereof, and a display device. By arranging spacers in the elevation area, the problem that the thickness of the overlapping area is small due to the horns in the first manufactured color filter and the second manufactured color filter is fundamentally solved, avoiding the generation of a large capacitance between the conductive layer and the data line or the scanning line, and reducing the load of the data line or the scanning line.

[0006] In a first aspect, the present application provides a display panel, which includes an array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate. The array substrate includes a plurality of first fabricated color resistors, a plurality of second fabricated color resistors, a metal layer, an insulating layer, a plurality of conductive layers, and a plurality of spacers. Among them, the first fabricated color resistors and the second fabricated color resistors form a raised area at a position corresponding to the metal layer, and the raised area is used to arrange the spacers; the metal layer is disposed on a side of the first fabricated color resistors and the second fabricated color resistors facing away from the liquid crystal layer, and at a position corresponding to the spacers, and the metal layer is used to arrange data lines or scan lines; the insulating layer is disposed on a surface of the first fabricated color resistors, the spacers, and the second fabricated color resistors facing the liquid crystal layer; the conductive layer is disposed on a partial surface of the insulating layer facing away from the first fabricated color resistors and the second fabricated color resistors.

[0007] In some embodiments, the array substrate further includes a first color resistor, a second color resistor, and a third color resistor. Among them, the first fabricated color resistor and the second fabricated color resistor are respectively the first color resistor and the second color resistor; or, the first fabricated color resistor and the second fabricated color resistor are respectively the second color resistor and the third color resistor; or, the first fabricated color resistor and the second fabricated color resistor are respectively the first color resistor and the third color resistor.

[0008] In some embodiments, when the first fabricated color resistor is the first color resistor and the second fabricated color resistor is the second color resistor, the first color resistor and the second color resistor are partially overlapped at the position of the metal layer, and the first color resistor and the second color resistor form the raised area at the overlapping position, and the spacers are arranged in the raised area. Among them, the spacers are white color resistors, third color resistors, or spacers.

[0009] In some embodiments, when the first fabricated color resistor is the second color resistor and the second fabricated color resistor is the third color resistor, the second color resistor and the third color resistor are arranged side by side, and the raised area is between the second color resistor and the third color resistor, and the spacers are arranged in the raised area. Among them, the spacers are the first color resistor.

[0010] In some embodiments, when the first fabricated color resistor is the first color resistor and the second fabricated color resistor is the third color resistor, the first color resistor and the second color resistor are arranged side by side, and a gap is formed between the first color resistor and the third color resistor. The gap corresponds to the position of the metal layer. The raised area includes a partial area of the surface of the first color resistor away from the metal layer and the gap, and the spacers are arranged in the raised area. Among them, the spacers are the second color resistor.

[0011] In a second aspect, the present application provides a method for manufacturing a display panel, the manufacturing method including:

[0012] Manufacture a metal layer and dispose data lines or scan lines on the metal layer;

[0013] Dispose a plurality of first manufacturing color filters, a plurality of second manufacturing color filters, and a plurality of spacers on an array substrate, wherein the first manufacturing color filters and the second manufacturing color filters form a raised area at positions corresponding to the metal layer, and the spacers are disposed in the raised area;

[0014] Dispose an insulating layer on a side of the first manufacturing color filters, the second manufacturing color filters, and the spacers facing away from the metal layer;

[0015] Dispose a conductive layer on a partial surface of the insulating layer on a side facing away from the first manufacturing color filters and the second manufacturing color filters;

[0016] Dispose a pixel unit and a common electrode on a side of each of the first manufacturing color filters and each of the second manufacturing color filters facing away from a liquid crystal layer, wherein the pixel unit is disposed closer to the conductive layer than the common electrode.

[0017] In some embodiments, the disposing a plurality of first manufacturing color filters, a plurality of second manufacturing color filters, and a plurality of spacers on an array substrate, wherein the first manufacturing color filters and the second manufacturing color filters form a raised area at positions corresponding to the metal layer, and the spacers are disposed in the raised area, includes: respectively using a first color filter and a second color filter of the display panel as the first manufacturing color filters and the second manufacturing color filters, and partially overlapping them at positions corresponding to the metal layer to form the raised area; filling the raised area with the spacers.

[0018] In some embodiments, the disposing a plurality of first manufacturing color filters, a plurality of second manufacturing color filters, and a plurality of spacers on an array substrate, wherein the first manufacturing color filters and the second manufacturing color filters form a raised area at positions corresponding to the metal layer, and the spacers are disposed in the raised area, includes: disposing the spacers in the raised area, wherein the spacers are a first color filter; using a second color filter and a third color filter as the first manufacturing color filters and the second manufacturing color filters respectively, and disposing them on opposite sides of the spacers and in contact with the spacers.

[0019] In some embodiments, arranging a plurality of first fabricated color filters, a plurality of second fabricated color filters, and a plurality of spacers on an array substrate, wherein the first fabricated color filter and the second fabricated color filter form a raised area at a position corresponding to the metal layer, and the spacer is disposed in the raised area, includes: disposing a first color filter as the first fabricated color filter on the metal layer, and disposing the spacer in the raised area, wherein the raised area includes a partial area of a surface of the first color filter away from the metal layer and the gap; disposing a third color filter as the second fabricated color filter on a side of the spacer away from the first color filter and in contact with the spacer.

[0020] In a third aspect, the present application provides a display device, which includes a power supply module and the above-mentioned display panel, and the power supply module provides electric energy for the display panel to perform screen display.

[0021] In summary, in the display panel, its manufacturing method, and the display device of the present application, according to the manufacturing sequence of the first color filter, the second color filter, and the third color filter, corresponding spacers, i.e., spacers or color filters of a third color other than the corresponding colors of the two overlapping color filters, are arranged between the two overlapping color filters to increase the thickness at the overlapping position of the two overlapping color filters, so that the overall thickness of the color filter between the metal layer and the conductive layer is consistent, thereby increasing the distance between the conductive layer and the metal layer to avoid generating a large capacitance between the conductive layer and the data line or the scan line, and further effectively reducing the load of the data line or the scan line, thereby improving the display quality and performance of the display panel and the display device. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 It is a schematic structural diagram of a display panel of the prior art;

[0024] Figure 2 It is a schematic structural diagram of a display panel disclosed in an embodiment of the present application;

[0025] Figure 3 is Figure 2 Another partial structural diagram of the shown display panel;

[0026] Figure 4 is Figure 2 Another partial structural diagram of the shown display panel;

[0027] Figure 5 It is a schematic flow chart of a method for manufacturing a display panel disclosed in an embodiment of the present application;

[0028] Figure 6 is Figure 5 a schematic flow chart of the first embodiment of step S2 in the shown manufacturing method;

[0029] Figure 7 is Figure 5 a schematic flow chart of the second embodiment of step S2 in the shown manufacturing method;

[0030] Figure 8 is Figure 5 a schematic flow chart of the third embodiment of step S2 in the shown manufacturing method.

[0031] Explanation of reference numerals:

[0032] 100, 200 - display panel; 10, 120 - array substrate; 20, 130 - color filter substrate; 50, 140 - liquid crystal layer; 121 - pixel unit; 121a - first color resistor; 121b - second color resistor; 122 - insulating layer; 123 - conductive layer; 124 - metal layer; 126 - common electrode; 1 - first color resistor for manufacturing; 51, 141 - liquid crystal molecules; 2 - second color resistor for manufacturing; 13 - metal layer; 14 - insulating layer; 16 - conductive layer; 15 - spacer; 11 - first color resistor; 12 - second color resistor; 19 - third color resistor; 17 - pixel unit; 18 - common electrode; a - overlapping area; S1 to S5 - steps of the manufacturing method; S11 to S12, S21 to S22, S31 to S32 - steps of manufacturing method S2. Detailed embodiments

[0033] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0034] The descriptions of the following embodiments refer to the attached drawings for illustrating specific embodiments in which the present application can be implemented. The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meanings. The terms "connection" and "coupling" as used in the present application, unless otherwise specified, both include direct and indirect connections (couplings). The directional terms mentioned in the present application, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are only with reference to the directions in the attached drawings. Therefore, the directional terms are used to better and more clearly illustrate and understand the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present application.

[0035] In the description of the present application, it should be noted that unless otherwise clearly defined and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances. It should be noted that the terms "first", "second", etc. in the description, claims, and drawings of the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include", "may include", "contain", or "may contain" used in the present application indicate the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit the existence of one or more other functions, operations, elements, etc. In addition, the term "include" or "contain" means the existence of the corresponding features, numbers, steps, operations, elements, components, or their combinations disclosed in the specification, and does not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components, or their combinations, and is intended to cover non-exclusive inclusion. It should also be understood that the meaning of "at least one" described herein is one and above, such as one, two, or three, etc., and the meaning of "multiple" is at least two, such as two or three, etc., unless otherwise specifically defined. The terms "step 1", "step 2", etc. in the description, claims, and drawings of the present application are used to distinguish different objects, rather than to describe a specific order.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the description of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0037] Please refer to Figure 1, Figure 1 is a schematic structural diagram of a display panel in the prior art. As Figure 1 shown, in the prior art, the display panel 100 generally includes an array substrate (Array Substrate, AS) 120, a color filter substrate (Color Film Substrate, CF) 130, and a liquid crystal layer 140 sandwiched between the array substrate 120 and the color filter substrate 130. Among them, driving elements are provided on the array substrate 120 and the color filter substrate 130, and different-sized electric fields are generated according to data signals, so as to drive the deflection angle of the liquid crystal molecules 141 in the liquid crystal layer 140 to emit light of corresponding brightness, so as to perform image display.

[0038] Specifically, the array substrate 120 includes a plurality of pixel units 121, a plurality of first color filters 121a, a plurality of second color filters 121b, an insulating layer 122, a plurality of conductive layers 123, a metal layer 124, and a plurality of common electrodes 126. Among them, the first color filter 121a and the second color filter 121b are partially overlapped, and an overlapping area a is formed at the overlapping position, and the opening direction of the overlapping area a faces the liquid crystal layer 140. The metal layer 124 is disposed on the sides of the first color filter 121a and the second color filter 121b facing away from the liquid crystal layer 140 and corresponds to the overlapping area a, that is, the first color filter 121a and the second color filter 121b are partially overlapped at the position of the metal layer 124. The metal layer 124 is used to lay data lines or scan lines to transmit control signals.

[0039] The insulating layer 122 is covered on the surface of the first color filter 121a and the second color filter 121b facing away from the metal layer 124. The conductive layer 123 is partially covered on the surface of the insulating layer 122 facing away from the first color filter 121a and the second color filter 121b. The pixel unit 121 and the common electrode 126 are respectively disposed on the sides of the first color filter 121a and the second color filter 121b facing away from the liquid crystal layer 140, and the pixel unit 121 is closer to the conductive layer 123 than the common electrode 126, that is, the pixel unit 121 is closer to the conductive layer 123 than the common electrode 126.

[0040] In the prior art, the thickness of the insulating layer 122 is smaller than the thicknesses of the first color resist 121a and the second color resist 121b. A partial overlap between the first color resist 121a and the second color resist 121b forms an overlapping area a. At the same time, both the first color resist 121a and the second color resist 121b have horns (i.e., tap angles), resulting in a smaller thickness of the overlapping area a, such that the distance between the conductive layer 123 and the data line or the scan line is relatively close, thereby generating a relatively large capacitance therebetween, and further causing a problem of increased loading of the data line or the scan line.

[0041] Based on this, the present application provides a display panel. By arranging a spacer at the position where the overlapping area a is formed, the problem that both the first color resist 121a and the second color resist 121b have tap angles resulting in a smaller thickness of the overlapping area a is fundamentally solved. Furthermore, the distance between the conductive layer 123 and the data line or the scan line is effectively increased to avoid generating a relatively large capacitance between the conductive layer 123 and the data line or the scan line, and to reduce the loading of the data line or the scan line.

[0042] Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of a display panel 200 disclosed in an embodiment of the present application. As Figure 2 shown, in the embodiment of the present application, the display panel 200 includes an array substrate 10, a color filter substrate 20, and a liquid crystal layer 50 sandwiched between the array substrate 10 and the color filter substrate 20. Driving elements are provided on the array substrate 10 and the color filter substrate 20, and different magnitudes of electric fields can be generated according to data signals, so as to drive the liquid crystal molecules 51 in the liquid crystal layer 50 to deflect by corresponding angles to emit light of corresponding brightness, thereby performing image display.

[0043] In a specific embodiment of the present application, the array substrate 10 includes a plurality of first fabricated color resists 1, a plurality of second fabricated color resists 2, a metal layer 13, an insulating layer 14, a plurality of conductive layers 16, and a plurality of spacers 15. Among them, the first fabricated color resist 1 and the second fabricated color resist 2 are partially overlapped and arranged at positions corresponding to the metal layer 13 to form a spacer area, and the spacers 15 are arranged at the overlapping positions (i.e., the spacer area) of the first fabricated color resist 1 and the second fabricated color resist 2. The spacers 15 are used to fill the overlapping positions of the first fabricated color resist 1 and the second fabricated color resist 2, so that the overall thickness of the color resist on the data line or the scan line is consistent.

[0044] The metal layer 13 is disposed on the surface of the first color resist 1 and the second color resist 2 facing away from the liquid crystal layer 50, and corresponds to the spacer 15, that is, the metal layer 13 is located on the side of the first color resist 1 and the second color resist 2 facing away from the liquid crystal layer 50, and corresponds to the overlapping position (i.e., the spacer area) of the first color resist 1 and the second color resist 2. The metal layer 13 is used to lay out data lines or scan lines to transmit control signals.

[0045] The insulating layer 14 is disposed to cover the surface of the first color resist 1 and the second color resist 2 facing away from the metal layer 13. The conductive layer 16 is disposed to cover a partial surface of the insulating layer 14 facing away from the first color resist 1 and the second color resist 2. Since the spacer 15 fills the gap at the overlapping position of the first color resist 1 and the second color resist 2, the overall thickness of the color resist on the data line or the scan line is made consistent, thereby increasing the distance between the conductive layer 16 and the data line or the scan line, reducing the capacitance therebetween, and further achieving the purpose of reducing the load of the data line or the scan line.

[0046] It should be noted that in the embodiment of the present application, the array substrate 10 includes a first color resist 11, a second color resist 12, and a third color resist 19. The first color resist 11, the second color resist 12, and the third color resist 19 may be a red color resist, a green color resist, and a blue color resist, respectively. That is, the first color resist 11, the second color resist 12, and the third color resist 19 are color resists with different colors.

[0047] The specific setting position of the spacer 15 is related to the manufacturing process sequence of the first color resist 11, the second color resist 12, and the third color resist 19. Since the spacer 15 is correspondingly disposed at the overlapping position (i.e., the spacer area) of two color resists, the color resist with the earlier manufacturing process sequence among the two color resists is defined as the first color resist 1 to be manufactured, and the color resist with the later manufacturing process sequence is defined as the second color resist 2 to be manufactured. Among them, the first color resist 1 to be manufactured and the second color resist 2 to be manufactured may be any two of the first color resist 11, the second color resist 12, and the third color resist 19.

[0048] In the embodiment of the present application, the conductive layer 16 may be a DBS (Data line BM Less) indium tin oxide (ITO) layer.

[0049] In the embodiment of the present application, the insulating layer 14 may be a PV2 insulating layer, that is, the array substrate 10 may be a double-insulating-layer substrate. The insulating layer 14 is the insulating layer closer to the liquid crystal layer 50 among the two insulating layers, and the other insulating layer is not shown in the embodiment of the present application. That is to say, the array substrate 10 includes a first insulating layer and a second insulating layer, the first insulating layer and the second insulating layer are respectively disposed on both sides of the metal layer 13, the insulating layer 14 is the insulating layer on the side of the metal layer 13 closer to the liquid crystal layer 50, and the insulating layer 14 is made of silicon nitride.

[0050] In a specific embodiment of the present application, the array substrate 10 further includes pixel units 17 and a common electrode 18. The pixel units 17 and the common electrode 18 are distributively arranged on the side of each of the first color resist 11 and the second color resist 12 facing away from the liquid crystal layer 50, and the pixel units 17 are closer to the conductive layer 16 than the common electrode 18. That is, the pixel units 17 and the common electrode 18 are disposed on the side of the first color resist 11 and the second color resist 12 facing away from the liquid crystal layer 50, that is, the pixel units 17 are disposed closer to the conductive layer 16 than the common electrode 18.

[0051] In the embodiment of the present application, the spacer 15 may be the first color resist 11, the second color resist 12, the third color resist 19, the white color resist, or a post spacer (PS). The specific usage scenarios will be elaborated in detail later.

[0052] In the embodiment of the present application, the thickness of the insulating layer 14 may be 0.1 micrometer (μm) - 0.2 μm, and the thickness of the first color resist 11, the second color resist 12, and the third color resist 19 when not serving as a spacer may be 1 μm. That is to say, when the first color resist 11 is the first fabricated color resist 1, the second color resist 12 partially overlaps with the first fabricated color resist 2 at the position corresponding to the metal layer 13, and the third color resist 19 serves as the spacer 15, the thicknesses of the first color resist 11 and the second color resist 12 are 1 μm. When the second color resist 12 is the first fabricated color resist 1, the third color resist 19 partially overlaps with the first fabricated color resist 2 at the position corresponding to the metal layer 13, and the first color resist 11 serves as the spacer 15, the thicknesses of the second color resist 12 and the third color resist 19 are 1 μm.

[0053] The thickness of the pixel unit 17 may be 0.65 μm, and the thickness of the conductive layer 16 may be 0.05 μm-0.07 μm, and this application does not impose any specific restrictions on this. It should be noted that, according to the example of the specific thickness parameters of the above structure, it can also be seen that the thickness difference between the insulating layer 14 and the color resist is large, resulting in that the insulating layer 14 cannot make up for the problem that the thickness of the overlapping position of the two color resists is thinner than that of other positions of the color resists when the two color resists overlap.

[0054] In the embodiment of the present application, the insulating layer 14 may be made of silicon nitride (SiNx), and the present application does not impose any specific limitation on this.

[0055] In a specific embodiment of the present application, the display panel may be a thin film transistor liquid crystal display (TFT-LCD). In this case, the array substrate 10 may be a thin film field effect transistor (TFT) substrate.

[0056] In a specific embodiment of the present application, the display panel 200 adopts the COA technology, or adopts the design of the COA technology and the POA technology at the same time, and the present application does not make any specific limitation on this.

[0057] In the embodiment of the present application, according to the process sequence of the first color resist 11, the second color resist 12 and the third color resist 19, the pad 15 is arranged at the overlapping position of the two overlapping color resists (i.e., the padding area) to increase the thickness of the two overlapping color resists at the overlapping position, so that the overall thickness of the color resist on the metal layer 13 is consistent, thereby increasing the distance between the conductive layer 16 and the metal layer 13 to reduce the capacitance between the two, thereby effectively reducing the load of the data line or the scan line.

[0058] Please continue reading Figure 2 In the first embodiment of the present application, the first color resist 1 is a first color resist 11, and the second color resist 2 is a second color resist 12. The first color resist 11 and the second color resist 12 each have a first thickness region, second thickness regions located on both sides of the first thickness region, and a transition region between the first thickness region and the second thickness region, wherein the thickness of the first thickness region is greater than the thickness of the second thickness region.

[0059] The first color resistor 11 and the second color resistor 12 are arranged in a partially overlapping manner at the position of the metal layer 13. Specifically, two second thickness regions of the first color resistor 11 and the second color resistor 12 overlap. An overlapping portion of the first color resistor 11 and the second color resistor 12, a transition region of the first color resistor 11 adjacent to the overlapping portion, and a transition region of the second color resistor 12 adjacent to the overlapping portion together form a raised area, and the spacer 15 is disposed in the raised area and faces away from the metal layer 13. Among them, the spacer 15 can be a white color resistor (W color resistor), a third color resistor 19, or a photo spacer (PS). By disposing the spacer 15 in the raised area, the overall thickness of the color resistors between the metal layer 13 and the conductive layer 16 can be made consistent, and the distance between the conductive layer 16 and the data line or the scan line is increased.

[0060] In a specific embodiment of the present application, the number of the spacers 15 disposed can be determined according to actual production needs, that is, it is only necessary to make the overall thickness of the color resistors on the metal layer 13 tend to be consistent, and the present application does not make specific restrictions on this.

[0061] In a specific embodiment of the present application, the first color resistor 11 can be a red color resistor, the second color resistor 12 can be a green color resistor, and the third color resistor 19 can be a blue color resistor.

[0062] In another specific embodiment of the present application, the first color resistor 11 can be a red color resistor, the second color resistor 12 can be a green color resistor, and the third color resistor 19 can be a photo spacer (PS).

[0063] It can be understood that the manufacturing process sequence of the color resistors is as follows: the first color resistor 11, the second color resistor 12, and the third color resistor 19. Therefore, in the embodiment of the present application, using the original manufacturing process sequence, the third color resistor 19 is disposed as the spacer 15 at the overlapping position of the first color resistor 11 and the second color resistor 12, that is, at the position of the raised area. Therefore, the thickness of the first color resistor 11 and the second color resistor 12 at the overlapping position can be effectively increased, thereby increasing the distance between the conductive layer 16 and the data line or the scan line, so as to avoid generating a large capacitance between the conductive layer 123 and the data line or the scan line, and further effectively reducing the load of the data line or the scan line.

[0064] Please refer to Figure 3 , Figure 3 for Figure 2 another partial structural schematic diagram of the display panel 200 shown. As Figure 3As shown, in the second embodiment of the present application, the first color resistor 1 is the second color resistor 12, and the second color resistor 2 is the third color resistor 19. The second color resistor 12 and the third color resistor 19 are arranged side by side, and the raised area corresponding to the metal layer 13 is located between the second color resistor 12 and the third color resistor 19.

[0065] That is, the raised object 15 is disposed in the raised area and on the metal layer 13. The second color resistor 12 and the third color resistor 19 are respectively disposed on both sides of the raised object 15 and in contact with the raised object 15. Among them, the raised object 15 is the first color resistor 11. By providing the raised object 15 in the raised area, the overall thickness of the color resistor between the metal layer 13 and the conductive layer 16 can be made consistent, and the distance between the conductive layer 16 and the data line or the scan line is increased.

[0066] Specifically, the raised object 15 has a first thickness area, two second thickness areas located on both sides of the first thickness area, and a transition area located between the first thickness area and the second thickness area. The thickness of the first thickness area is greater than the thickness of the second thickness area. The second color resistor 12 and the third color resistor 19 have opposite sides. One side of the second color resistor 12 is in contact with the second thickness area on one side of the raised object 15, and one side of the third color resistor 19 is in contact with the second thickness area on the other side of the raised object 15.

[0067] In a specific embodiment of the present application, the first color resistor 11 may be a red color resistor, the second color resistor 12 is a green color resistor, and the third color resistor 19 is a blue color resistor.

[0068] It can be understood that the manufacturing process sequence of the color resistors is: the first color resistor 11, the second color resistor 12, and the third color resistor 19. Therefore, in the embodiment of the present application, using the original manufacturing process sequence, the first color resistor 11 is first disposed as the raised object 15 on the surface of the metal layer 13 close to the liquid crystal layer 50, and then the second color resistor 12 and the third color resistor 19 are respectively disposed on opposite sides of the first color resistor 11 and in contact with the first color resistor 11 according to the original manufacturing process sequence. Thus, the thickness of the second color resistor 12 and the third color resistor 19 in the raised area is effectively increased, thereby increasing the distance between the conductive layer 16 and the metal layer 13 to reduce the capacitance between them, and further effectively reducing the load of the data line or the scan line.

[0069] Please refer to Figure 4 , Figure 4 For Figure 2 a further partial structural schematic diagram of the display panel 200 shown. As Figure 4As shown, in the third embodiment of the present application, the first color resistor 1 is the first color resistor 11, and the second color resistor 2 is the third color resistor 19. The first color resistor 11 and the third color resistor 19 are arranged side by side with a gap therebetween, and the gap corresponds to the metal layer 13. That is, the first color resistor 11 and the third color resistor 19 are arranged side by side, and a gap is formed between the first color resistor 11 and the third color resistor 19, and the position of the gap corresponds to the metal layer 13. The raised area includes a partial area of the surface of the first color resistor 11 away from the metal layer 13 and the gap. The spacer 15 is disposed on the partial area of the surface of the first color resistor 11 away from the metal layer 13 and the gap, and one end of the spacer 15 is located on the metal layer 13. That is to say, the first color resistor 11 and the third color resistor 19 are located on both sides of the spacer 15 and in contact with the spacer 15. Wherein, the spacer is the second color resistor 12. By arranging the spacer 15 in the raised area, the overall thickness of the color resistor between the metal layer 13 and the conductive layer 16 can be made consistent, and the distance between the conductive layer 16 and the data line or the scan line is increased.

[0070] In a specific embodiment of the present application, the first color resistor 11 may be a red color resistor, the second color resistor 12 is a green color resistor, and the third color resistor 19 is a blue color resistor.

[0071] It can be understood that the manufacturing process sequence of the color resistors is as follows: the first color resistor 11, the second color resistor 12, and the third color resistor 19. Therefore, in the embodiment of the present application, using the original manufacturing process sequence, the first color resistor 11 is first set, and one side of the first color resistor 11 corresponds to the metal layer 13, and then the second color resistor 12 is used as the spacer 15 and set on the first color resistor 11 and the metal layer 13, and then the third color resistor 19 is set on the metal layer 13, and one side of the third color resistor 19 is in contact with the second color resistor 12. Thus, the height of the side of the third color resistor 19 close to the second color resistor 12 (i.e., the spacer 15) can be effectively raised when the third color resistor 19 is set, thereby increasing the distance between the conductive layer 16 and the metal layer 13 to reduce the capacitance therebetween, and effectively reducing the load of the data line or the scan line.

[0072] It should be noted that in the embodiments of the present application, the display panel 200 may also include color filters of four different colors. At this time, the spacer 15 may be a color filter of a third color other than the colors corresponding to the two overlapping color filters. Specifically, the display panel 200 may include a first color filter 11, a second color filter 12, a third color filter 19, and a fourth color filter. When the first color filter 11 and the second color filter 12 overlap, the third color filter 19 or the fourth color filter may be filled into the spacer area as the spacer 15 according to the process sequence to increase the thickness of the overlapping position of the two overlapping color filters, so that the overall thickness of the color filter between the metal layer 13 and the conductive layer 16 is consistent, thereby increasing the distance between the conductive layer 16 and the metal layer 13 to avoid generating a large capacitance between the conductive layer 123 and the data line or the scan line, and further effectively reducing the load of the data line or the scan line.

[0073] Based on the same inventive concept, the present application further provides a display device, which includes a power supply module and the above-mentioned display panel 200, and the power supply module provides electrical energy for the display panel 200 to display images.

[0074] Please refer to Figure 5 , Figure 5 which is a schematic flowchart of the manufacturing method of the display panel 200 disclosed in the embodiments of the present application.

[0075] As Figure 5 shown, based on the same inventive concept, the present application further provides a manufacturing method of the above-mentioned display panel 200. It should be noted that the manufacturing method of the embodiments of the present application is not limited to Figure 5 the steps and sequences in the flowchart shown. According to different requirements, the steps in the shown flowchart may be added, removed, or the order may be changed. In the embodiments of the present application, the manufacturing method may include the following steps.

[0076] Step S1: Fabricate the metal layer 13 and arrange data lines or scan lines on the metal layer 13.

[0077] Step S2: Arrange a plurality of first fabricated color filters 1, a plurality of second fabricated color filters 2, and a plurality of spacers 15 on the array substrate 10, wherein the first fabricated color filters 1 and the second fabricated color filters 2 form a spacer area at positions corresponding to the metal layer 13, and the spacers 15 are disposed in the spacer area.

[0078] In an embodiment of the present application, the display panel 200 includes a first color filter 11, a second color filter 12, and a third color filter 19. Among them, the colors corresponding to the first color filter 11, the second color filter 12, and the third color filter 19 are different. The first fabricated color filter 1 and the second fabricated color filter 2 can be any two of the first color filter 11, the second color filter 12, and the third color filter 19. The first fabricated color filter 1 and the second fabricated color filter 2 are partially overlapped or arranged side by side at a position corresponding to the metal layer 13 to form a raised area, and a spacer 15 is disposed at an overlapping position (i.e., the raised area) corresponding to the first fabricated color filter 1 and the second fabricated color filter 2. The spacer 15 is used to fill the overlapping position of the first fabricated color filter 1 and the second fabricated color filter 2, so that the overall thickness of the color filters on the data line or the scan line is consistent.

[0079] Step S3: Dispose the insulating layer 14 on a side of the first fabricated color filter 1, the second fabricated color filter 2, and the spacer 15 facing away from the metal layer 13.

[0080] In an embodiment of the present application, the insulating layer 14 can be a PV2 insulating layer, that is, the array substrate 10 can be a double-insulating layer substrate. The insulating layer 14 is an insulating layer close to the liquid crystal layer 50, and another insulating layer is not shown in the embodiment of the present application. The thickness of the insulating layer 14 can be 0.1 μm - 0.2 μm.

[0081] Step S4: Dispose the conductive layer 16 on a partial surface of the insulating layer 14 on a side facing away from the first fabricated color filter 1 and the second fabricated color filter 2.

[0082] In an embodiment of the present application, the first fabricated color filter 1 and the second fabricated color filter 2 are disposed adjacent to each other, and the spacer 15 is disposed therebetween. The insulating layer 14 is disposed to cover the surfaces of the first fabricated color filter 1 and the second fabricated color filter 2 on a side facing away from the metal layer 13. The conductive layer 16 is disposed to cover a partial surface of the insulating layer 14 on a side facing away from the first fabricated color filter 1 and the second fabricated color filter 2. Since the spacer 15 fills the gap at the overlapping position of the first fabricated color filter 1 and the second fabricated color filter 2, the overall thickness of the color filters on the data line or the scan line is consistent. Therefore, the distance between the conductive layer 16 and the data line or the scan line is increased, thereby reducing the capacitance therebetween, and further achieving the purpose of reducing the load of the data line or the scan line.

[0083] In an embodiment of the present application, the conductive layer 16 can be a DBS ITO layer.

[0084] Step S5: Pixel units 17 and a common electrode 18 are provided on the side of each of the first fabricated color resistors 11 and each of the second fabricated color resistors 12 facing away from the liquid crystal layer 50. Among them, the pixel unit 17 is disposed closer to the conductive layer 16 than the common electrode 18.

[0085] In the embodiment of the present application, the pixel units 17 and the common electrode 18 are distributively provided on the side of each of the first fabricated color resistors 11 and the second fabricated color resistors 12 facing away from the liquid crystal layer 50, and the pixel unit 17 is closer to the conductive layer 16 than the common electrode 18. That is, the pixel unit 17 and the common electrode 18 are provided on the side of the first fabricated color resistors 11 and the second fabricated color resistors 12 facing away from the liquid crystal layer 50, that is, the pixel unit 17 is disposed closer to the conductive layer 16 than the common electrode 18.

[0086] Please refer to Figure 6 , Figure 6 is Figure 5 a schematic flow chart of the first embodiment of step S2 in the manufacturing method shown. As Figure 6 shown, in the embodiment of the present application, the step S2 "disposing a plurality of first fabricated color resistors 1, a plurality of second fabricated color resistors 2, and a plurality of spacers 15 on the array substrate 10, wherein the first fabricated color resistors 1 and the second fabricated color resistors 2 form a raised area at the position corresponding to the metal layer 13, and the spacers 15 are disposed in the raised area" may include the following steps.

[0087] Step S11: Using the first color resistor 11 and the second color resistor 12 of the display panel 200 as the first fabricated color resistor and the second fabricated color resistor respectively, and partially overlapping them at the position corresponding to the metal layer 13 to form the raised area.

[0088] In the embodiment of the present application, please refer to Figure 2 , the first fabricated color resistor 1 is the first color resistor 11, and the second fabricated color resistor 2 is the second color resistor 12. Both the first color resistor 11 and the second color resistor 12 respectively have a first thickness region, second thickness regions on both sides of the first thickness region, and a transition region between the first thickness region and the second thickness region. The thickness of the first thickness region is greater than that of the second thickness region.

[0089] The two first thickness regions of the first color resistor 11 and the second color resistor 12 overlap. The overlapping portion of the first color resistor 11 and the second color resistor 12, the transition region of the first color resistor 11 adjacent to the overlapping portion, and the transition region of the second color resistor 12 adjacent to the overlapping portion together form a raised area.

[0090] Step S12: Filling the spacer 15 into the raised area.

[0091] In an embodiment of the present application, the spacer 15 is disposed in the raised area. Wherein, the spacer 15 may be a W color resistor, a third color resistor 19 or a spacer.

[0092] Please refer to Figure 7 , Figure 7 for Figure 5 the schematic flow chart of the second embodiment of step S2 in the manufacturing method shown. As Figure 7 shown, in an embodiment of the present application, the step S2 of "disposing a plurality of first manufacturing color resistors 1, a plurality of second manufacturing color resistors 2 and a plurality of spacers 15 on the array substrate 10, wherein the first manufacturing color resistor 1 and the second manufacturing color resistor 2 form a raised area at positions corresponding to the metal layer 13, and the spacer 15 is disposed in the raised area" may include the following steps.

[0093] Step S21: Dispose the spacer 15 in the raised area, wherein the spacer 15 is the first color resistor 11.

[0094] In an embodiment of the present application, the spacer 15 may be the first color resistor 11.

[0095] Step S22: Respectively use the second color resistor 12 and the third color resistor 19 as the first manufacturing color resistor 1 and the second manufacturing color resistor 2, and dispose them on opposite sides of the spacer 15 and in contact with the spacer 15.

[0096] In an embodiment of the present application, please refer to Figure 3 , the first manufacturing color resistor 1 is the second color resistor 12, and the second manufacturing color resistor 2 is the third color resistor 19. The spacer 15 has a first thickness region, two second thickness regions on both sides thereof, and a transition region between the first thickness region and the second thickness region. The thickness of the first thickness region is greater than the thickness of the second thickness region. The second color resistor 12 and the third color resistor 19 have opposite sides. One side of the second color resistor 12 is in contact with the second thickness region on one side of the spacer 15, and one side of the third color resistor 19 is in contact with the second thickness region on the other side of the spacer 15.

[0097] Please refer to Figure 8 , Figure 8 for Figure 5 the schematic flow chart of the third embodiment of step S2 in the manufacturing method shown. As Figure 8As shown, in the embodiment of the present application, the step S2 "disposing a plurality of first color resist layers 1, a plurality of second color resist layers 2, and a plurality of spacers 15 on the array substrate 10, wherein the first color resist layer 1 and the second color resist layer 2 form a raised area at the position corresponding to the metal layer 13, and the spacers 15 are disposed in the raised area" may include the following steps.

[0098] Step S31: Dispose the first color resist layer 11 as the first color resist layer 1 on the metal layer 13, and dispose the spacers 15 in the raised area, wherein the raised area includes a partial area on the surface of the first color resist layer away from the metal layer and the gap.

[0099] Step S32: Dispose the third color resist layer 19 as the second color resist layer 2 on the side of the spacers 15 away from the first color resist layer 11 and in contact with the spacers 15.

[0100] In the embodiment of the present application, please refer to Figure 4 , the first color resist layer 11 is the first color resist layer 1, and the third color resist layer 19 is the second color resist layer 2. The first color resist layer 11 and the third color resist layer 19 are arranged side by side with a gap therebetween, and the gap corresponds to the metal layer 13. The spacers are disposed in a partial area on the surface of the first color resist layer 11 away from the metal layer 13 and in the gap. Wherein, the spacers are the second color resist layer 12.

[0101] In summary, in the display panel 200, the display device, and the above manufacturing method of the present application, according to the manufacturing sequence of the first color resist layer 11, the second color resist layer 12, and the third color resist layer 19, corresponding spacers 15, i.e., spacers (PS) or color resist layers of a third color other than the corresponding colors of the two overlapping color resist layers, are disposed between the two overlapping color resist layers to increase the thickness at the overlapping position of the two overlapping color resist layers, so that the overall thickness of the color resist layer between the metal layer 13 and the conductive layer 16 is consistent, thereby increasing the distance between the conductive layer 16 and the metal layer 13 to avoid generating a large capacitance between the conductive layer 123 and the data line or the scan line, and further effectively reducing the load of the data line or the scan line, thereby improving the display quality and performance of the display panel 200 and the display device.

[0102] All possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0103] In the description of this specification, the descriptions with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples" or "some examples" etc. mean that the specific features, structures, materials or characteristics described in connection with the said embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

[0104] It should be understood that the above-mentioned embodiments only represent several embodiments of the present application, and their descriptions are relatively specific and detailed, but should not be construed as a limitation to the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several variations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A display panel, comprising an array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate, wherein, The array substrate includes a plurality of first fabricated color filters, a plurality of second fabricated color filters, a metal layer, an insulating layer, a plurality of conductive layers, and a plurality of spacers. Among them, the first fabricated color filters and the second fabricated color filters are partially overlapped at positions corresponding to the metal layer to form a raised area. The overall thickness of the adjacent first fabricated color filters and second fabricated color filters in the overlapping area is smaller. The raised area is used to arrange the spacers. The metal layer is disposed on one side of the first fabricated color filters and the second fabricated color filters facing away from the liquid crystal layer and at positions corresponding to the spacers. The metal layer is used to arrange data lines or scan lines. The insulating layer is disposed on the surface of the first fabricated color filters, the spacers, and the second fabricated color filters facing the liquid crystal layer. The conductive layer is disposed on a partial surface of the insulating layer on the side facing away from the first fabricated color filters and the second fabricated color filters.

2. The display panel according to claim 1, wherein The array substrate further includes a first color filter, a second color filter, and a third color filter. Among them, the first fabricated color filter and the second fabricated color filter are the first color filter and the second color filter respectively; or, The first fabricated color filter and the second fabricated color filter are the second color filter and the third color filter respectively; or, The first fabricated color filter and the second fabricated color filter are the first color filter and the third color filter respectively.

3. The display panel according to claim 2, wherein When the first fabricated color filter is the first color filter and the second fabricated color filter is the second color filter, the first color filter and the second color filter are partially overlapped at the position of the metal layer, and the first color filter and the second color filter form the raised area at the overlapping position. The spacers are arranged in the raised area. Among them, the spacers are white color filters, third color filters, or spacers.

4. The display panel according to claim 2, wherein When the first fabricated color filter is the second color filter and the second fabricated color filter is the third color filter, the second color filter and the third color filter are arranged side by side, and the raised area is between the second color filter and the third color filter. The spacers are arranged in the raised area. Among them, the spacers are the first color filter.

5. The display panel according to claim 2, wherein When the first fabricated color filter is the first color filter and the second fabricated color filter is the third color filter, the first color filter and the second color filter are arranged side by side, and a gap is formed between the first color filter and the third color filter. The gap corresponds to the position of the metal layer. The raised area includes a partial area of the surface of the first color filter away from the metal layer and the gap. The spacers are arranged in the raised area. Among them, the spacers are the second color filter.

6. A method for manufacturing a display panel, which is used to manufacture the display panel according to any one of claims 1-5, characterized in that, The manufacturing method includes: Manufacturing the metal layer and arranging data lines or scan lines on the metal layer; Arranging a plurality of first fabricated color filters, a plurality of second fabricated color filters, and a plurality of spacers on the array substrate. Among them, the first fabricated color filters and the second fabricated color filters form a raised area at positions corresponding to the metal layer, and the spacers are arranged in the raised area. Arranging the insulating layer on one side of the first fabricated color filters, the second fabricated color filters, and the spacers facing away from the metal layer. The conductive layer is disposed on a partial surface of the insulating layer facing away from the first color resist and the second color resist; A pixel unit and a common electrode are disposed on one side of each of the first color resists and each of the second color resists facing away from the liquid crystal layer. Among them, the pixel unit is disposed closer to the conductive layer than the common electrode.

7. The manufacturing method according to claim 6, characterized in that The method of disposing a plurality of first color resists, a plurality of second color resists, and a plurality of spacers on the array substrate, wherein the first color resist and the second color resist form a raised area at a position corresponding to the metal layer, and the spacers are disposed in the raised area, includes: Using the first color resist and the second color resist of the display panel as the first color resist and the second color resist respectively, and partially overlapping them at a position corresponding to the metal layer to form the raised area; Filling the raised area with the spacers.

8. The manufacturing method according to claim 6, characterized in that, The method of disposing a plurality of first color resists, a plurality of second color resists, and a plurality of spacers on the array substrate, wherein the first color resist and the second color resist form a raised area at a position corresponding to the metal layer, and the spacers are disposed in the raised area, includes: Disposing the spacers in the raised area, wherein the spacers are the first color resist; Using the second color resist and the third color resist as the first color resist and the second color resist respectively, and disposing them on opposite sides of the spacers and in contact with the spacers.

9. The manufacturing method according to claim 6, characterized in that, The method of disposing a plurality of first color resists, a plurality of second color resists, and a plurality of spacers on the array substrate, wherein the first color resist and the second color resist form a raised area at a position corresponding to the metal layer, and the spacers are disposed in the raised area, includes: Using the first color resist as the first color resist and disposing it on the metal layer, and disposing the spacers in the raised area, wherein the raised area includes a partial area on a surface of the first color resist away from the metal layer and a gap; Using the third color resist as the second color resist and disposing it on a side of the spacers away from the first color resist and in contact with the spacers, wherein the first color resist and the third color resist are arranged side by side, and a gap is formed between the first color resist and the third color resist, and the gap corresponds to the position of the metal layer.

10. A display device, characterized in that, The display device includes a power supply module and a display panel according to any one of claims 1-5, and the power supply module provides electric energy for the display panel to display images.

Images