Time-to-Digital Converter Based on Self-Referenced Delay Cells

Abstract

The present disclosure relates to a time-to-digital converter based on a self-referenced delay cell. A time-to-digital converter (TDC) circuit includes control logic and a first self-referenced delay cell circuit coupled to the control logic. The first self-referenced delay cell circuit includes: a first group of capacitors coupled to a first node between a first positive input and a first positive output, wherein the first group of capacitors is selectively controlled by a first control signal from the control logic, the first control signal including a first up value corresponding to a first positive threshold; and a second group of capacitors coupled to a second node between a first negative input and a first negative output, wherein the second group of capacitors is selectively controlled by a second control signal from the control logic, the second control signal including a first down value corresponding to a first negative threshold.

Description

Technical Field

[0001] At least one embodiment generally relates to a phase-locked loop (PLL), and more particularly, to a time-to-digital converter (TDC) based on a self-reference delay cell in a PLL. Background Art

[0002] A phase-locked loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. There are several different types, but the simplest is an electronic circuit that includes a variable-frequency oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares the phase of this signal with the phase of the input periodic signal and adjusts the oscillator to maintain phase matching. Thus, a PLL operates on two inputs, which can be understood as a reference clock and a feedback clock. Part of the function of a PLL is to approximate the delay between these two inputs for matching adjustment.

[0003] In some PLLs, a time-to-digital converter (TDC) is typically used to accurately define the gain and allow digital tracking of the spread spectrum of the reference clock. There are different limitations in these TDCs, which may include system offsets, especially when the PLL is a hybrid PLL, for example, a hybrid PLL that employs an analog proportional path circuit and a digital integration path circuit, where the TDC digitizes the delay value of the latter. These limitations increase when trying to achieve a very small step size between the reference clock and the feedback clock, for example, on the order of picoseconds or a few picoseconds. Brief Description of the Drawings

[0004] Various embodiments in accordance with the present disclosure will be described with reference to the accompanying drawings, in which:

[0005] Figure 1 is a schematic block diagram of a phase-locked loop (PLL) employing a time-to-digital converter (TDC) circuit according to at least some embodiments;

[0006] Figure 2A is a schematic block diagram of a TDC circuit based on a self-reference delay cell according to at least some embodiments;

[0007] Figure 2B is a schematic block diagram of a self-reference delay cell circuit in a TDC circuit according to at least some embodiments; and

[0008] Figure 3 is a flowchart of a method for controlling a plurality of self-reference delay cell circuits according to at least some embodiments. Detailed Description

[0009] Aspects and embodiments of the present invention address the above complexities and challenges of using a TDC circuit in a PLL by employing a self-referenced delay cell circuit in the TDC circuit, e.g., which is distinguished from using multiple single-ended delay cell circuits with a common timing reference. In some PLLs, a linear TDC circuit is used to precisely define gain and allow tracking of a spread spectrum reference clock. For low jitter applications, the PLL uses a high-resolution TDC circuit with a medium range. Additionally, TDC step changes are tightly controlled to meet the bandwidth specifications mandated by standards such as PCI and so on.

[0010] In some PLLs, a flash TDC circuit meets these limitations, which uses the difference between two delay values to obtain high resolution. A flash TDC circuit can be understood as being similar to a flash analog-to-digital converter that uses multiple delay cell circuits, where the TDC time step is implemented as the difference between two delay cell circuits with different settings. The delay in the delay cell circuit can be programmed by variably changing the capacitance of each corresponding delay cell circuit using control logic. By using logic that implements dynamic element matching (DEM) based on a pseudo-random binary sequence (PRBS), such as the PRBS31 pattern, TDC step changes can be countered. The control logic can use this PRBS pattern to transform the threshold of the delay cell circuit in each cycle to attempt to reduce the impact of mismatches and linearize the flash TDC circuit.

[0011] However, in these TDC circuits, there are limitations due to the design using single-ended delay cells with a common reference. For example, the outputs of multiple delay cell circuits that process the up (UP) signal of the reference clock can be provided by flip-flops or latches that are clocked based on the output of a single delay cell circuit that processes the down (DN) signal of the feedback clock. This DN single delay cell circuit generates a common reference (which can be delayed by a fixed amount), and the common reference drives the latches of all UP delay cell circuits, which are delayed by different amounts according to the PRBS pattern. These single-ended delay cell circuits can cause input path mismatches, resulting in a systematic offset at the input of the TDC circuit, which is difficult to compensate for in the TDC circuit / PLL implementation design.

[0012] For example, although attempts are made to load the DN signal with a virtual load to create symmetry, it is difficult to be accurate because, by design, the fan-out signals between the UP / DN delay cell circuits are asymmetric. More specifically, a common reference from a single DN delay cell circuit uses a large number of fan-out signals to drive all the UP latches, and for the UP delay cell circuits, when each UP delay cell circuit drives a single latch of the UP latches, a small number of fan-out signals are used. The output combination of these latches is a thermometer code, which can be understood as an entropy encoding representing natural numbers. By summing these thermometer outputs, a final binary code is generated. As mentioned above, when using the PLL with the analog proportional path circuit and the digital integration path circuit in the hybrid mode, the system offset is a more intractable problem, resulting in reference spurs in the output of the TDC circuit.

[0013] In addition, the single-ended TDC circuit design must cope with the challenge of asymmetric positive and negative thresholds that occur in multiple delay cell circuits. A positive threshold is created by increasing the capacitance, and a negative threshold is created by removing capacitance from a given delay cell circuit. The resistance / capacitance (RC) value of each node in the delay cell circuit changes with the change in capacitance. Changing the capacitance is a non-linear process, which generally works well in a small delay range, such as in the range of 10-20% of the capacitance value, but does not work in a large delay range. In fact, the behaviors of increasing capacitance and removing capacitance are almost the same but not identical. Therefore, although very small, this asymmetry is a problem when attempting to achieve very small step sizes on the order of, for example, 1-3 picoseconds (ps).

[0014] Aspects of the present invention address the above and other deficiencies by using a self-reference delay cell circuit in the TDC circuit of the PLL, thereby eliminating the single-ended common reference of the previous designs. For example, each self-reference delay cell circuit may include a first inverter serially coupled to a second inverter, the first inverter receiving a positive time signal representing an incoming up signal (UP), and a third inverter serially coupled to a fourth inverter, the third inverter receiving a negative time signal representing an incoming down signal (DN). Each self-reference delay cell circuit may further include a first set of capacitors coupled to a first node between the first inverter and the second inverter, and the control logic selectively controls the first set of capacitors through a first control signal corresponding to a positive threshold. Each self-reference delay cell circuit may further include a second set of capacitors coupled to a second node between the third inverter and the fourth inverter, wherein the control logic selectively controls the second set of capacitors through a second control signal corresponding to a negative threshold. In this way, the second set of capacitors in each delay cell circuit can be controlled independently of the first set of capacitors, and any asymmetry between the positive threshold and the negative threshold can also be eliminated.

[0015] In these embodiments, the disclosed TDC circuit may further include a phase detector coupled to respective outputs of the self-reference delay cell circuit and an adder coupled to the output of the phase detector. The adder may be configured to generate a multi-bit output representing the time difference between an incoming upstream signal and an incoming downstream signal. Due to a mismatch between the logic and the number of effective delay cell circuits employed, mapping logic may be used to map the multi-bit output to a digital code that is at least one bit smaller than the multi-bit output and quantifies the time difference.

[0016] Thus, advantages of the systems and methods implemented in accordance with some embodiments of the present disclosure include, but are not limited to, the ability to match the input paths of the multi-delay cell circuits of the TDC circuit, eliminate system offsets, and the ability to match (e.g., be symmetric with respect to) a positive threshold to a negative threshold. The disclosed TDC circuit is compatible with DEM logic, reducing the impact of mismatches in the delay cell circuits and reducing the non-linearity of the TDC circuit. Other advantages of the TDC circuit-based PLL discussed below will be apparent to those skilled in the art.

[0017] Figure 1 FIG. 7 is a schematic block diagram of a phase-locked loop (PLL) 100 employing a TDC circuit 120 in accordance with at least some embodiments. In at least some embodiments, PLL 100 includes a phase frequency detector (PFD) 110, a proportional path circuit 130, a TDC circuit 120, a digital integration path circuit 140, a digitally controlled oscillator (DCO) 150, a high-speed divider (HSDIV) 160, a delta-sigma modulator divider (DSMDIV) 170, and an integer divider (NDIV) 180. Thus, TDC circuit 120 is coupled between phase frequency detector 110 and DCO 150, digital integration path circuit 140 is coupled between TDC circuit 120 and DCO 150, and proportional path circuit 130 is coupled between phase frequency detector 110 and DCO 150.

[0018] In at least some embodiments of PLL 100, PFD 110 receives a reference clock (REFCLK) and a feedback clock (FBCLK) from PLL 100 feedback loop 174. PFD 110 detects the frequency / phase of the reference clock and the feedback clock and generates two corresponding signals, e.g., an UP signal for the frequency / phase of the reference clock and a DN signal for the frequency / phase of the feedback clock. The UP signal and the DN signal are both provided to proportional path circuit 130 and TDC circuit 120. As previously described, in the hybrid mode of PLL 100, proportional path circuit 130 is an analog circuit, e.g., including a charge pump, a low-pass filter, and other filtering circuits. Proportional path circuit 130 is used to perform proportional processing on the UP / DN signals.

[0019] In these embodiments, the TDC circuit 120 converts the UP / DN signals into digital values that can be combined and processed into a final digital code that quantifies the time difference between UP / DN. In some embodiments, the final digital code can be a 4-bit digital code, but it can also be other digital codes. The digital code is fed into the digital integration path circuit 140, which then performs an integration process on the UP / DN signals based on the digital code generated by the TDC circuit 120.

[0020] In these embodiments, the outputs of both paths, including the scaled path circuit 130 and the digital integration path circuit 140, are input into the DCO 150. In this way, the two scaled and integration paths are connected together, causing a change in the frequency of the DCO 150 in a continuous feedback loop. In turn, the feedback loop 174 can include components such as HSDIV 160, DSMDIV 170, and NDIV 180, which divide down the signal generated by the DCO to generate a feedback clock (FBCLK).

[0021] In various embodiments, any offset exhibited by the TDC circuit 120 (e.g., system offset) causes the scaled path circuit 130 and the digital integration path circuit 140 to compete (e.g., via the DCO 130) to resolve phase-based timing issues. Due to its higher gain, the digital integration path circuit 140 wins this competition. This can cause an offset in the input to the PLL 100, resulting in spurs in the output of the PLL 100 at the reference clock frequency. This and other deficiencies in the single-ended TDC circuit can be addressed by the self-reference delay cell-based TDC circuit described below.

[0022] Figure 2A is a schematic block diagram of a self-reference delay cell-based TDC circuit 200 according to at least some embodiments. In some embodiments, the TDC circuit 200 is used as a reference Figure 1 for the TDC circuit 120 of the PLL 100 discussed. In these embodiments, the TDC circuit 200 includes a chopper 202 that samples or otherwise slices the UP signal of the reference clock and the DN signal of the feedback clock. The TDC circuit 200 also includes DEM logic 206 (also referred to herein as control logic), a plurality of self-reference delay cell circuits 210 (illustrated as DLY), a plurality of phase detectors 220A (illustrated as PD) coupled to each of the plurality of self-reference delay cell circuits 210, an adder 230 coupled to the outputs of the plurality of phase detectors 220A, and a mapping logic 240 coupled to the output of the adder 230. Figure 2BSchematic diagram of the first self - reference time - delay unit circuit 210A among a plurality of self - reference delay unit circuits 210 in the TDC circuit 200 according to at least some embodiments, illustrating the structure of each of the plurality of self - reference delay unit circuits 210 by way of example.

[0023] In at least some embodiments, the plurality of self - reference delay unit circuits 210 includes a first self - reference delay unit circuit 210A, a second self - reference delay unit circuit 210B, a third self - reference delay unit circuit 210C, a fourth self - reference delay unit circuit 210N, a fifth self - reference delay unit circuit 210O, and a sixth self - reference delay unit circuit 210P. Correspondingly, the plurality of phase detectors (each of which can be a flip - flop, a latch, etc.) includes a first phase detector 220A, a second phase detector 220B, a third phase detector 220C, a fourth phase detector 220N, a fifth phase detector 220O, and a sixth phase detector 220P, which are coupled to the output terminals of the self - reference delay unit circuits with their respective numbers. Although Figure 2A Six of the plurality of self - reference delay unit circuits 210 and the plurality of phase detectors 220 are shown, but the dots in the middle indicate that there may be more in each circuit. For example, there are 16 pairs working in each circuit.

[0024] In these embodiments, a sampling portion (UP_CHOP) of the UP signal and a sampling portion (DN_CHOP) of the DN signal are provided to each of the plurality of self - reference delay unit circuits 210. The DEM logic 206 also sends two control signals (k1, k2) to each of the plurality of self - reference delay unit circuits 210, as Figure 2B shown and indicated by the dashed lines in Figure 2A In this way, each self - reference delay unit circuit obtains the DN portion of the input DN signal as its own reference, thus eliminating the systematic offset between the groups of delay unit circuits.

[0025] In various embodiments, each self - reference delay unit circuit 210 includes a first inverter 212A serially coupled to a second inverter 212B, where the first inverter 212A receives a positive time signal (INP) representing an incoming up - signal, and a third inverter 212C serially coupled to a fourth inverter 212D, where the third inverter 212C receives a negative time signal (INN) representing an incoming down - signal. Then, the capacitor bank in each delay unit circuit can be split into a first group of capacitors 214A and a second group of capacitors 214B within each of the plurality of self - reference delay unit circuits 210. Although these inverters can be used in the delay unit circuits, other buffers or similar components can also be used.

[0026] In these embodiments, a first set of capacitors 214A is coupled to a first node 215A between a first inverter 212A and a second inverter 212B. The first set of capacitors 214A is selectively controlled by a first control signal corresponding to a positive threshold from the DEM logic 206. For example, the DEM logic 206 can selectively control a first switch 216A coupled to the first set of capacitors 214A. Additionally, in these embodiments, a second set of capacitors 214B is coupled to a second node 215B between a third inverter 212C and a fourth inverter 212D. The second set of capacitors 214B is selectively controlled by a second control signal corresponding to a negative threshold from the DEM logic 206. For example, the DEM logic 206 can selectively control a second switch 216B coupled to the second set of capacitors 214B. Since adding a positive threshold or removing a negative threshold is performed discretely in each corresponding self-reference delay cell circuit having the same mirror capacitor bank, a positive threshold symmetric to the negative threshold can be created, thereby reducing non-linearity. Thus, in some embodiments, the capacitors in the first set of capacitors 214A are equal in size and number to the capacitors in the second set of capacitors to provide such the same mirror capacitor bank.

[0027] In these embodiments, the TDC circuit 200 further includes a plurality of phase detectors 220 coupled to respective output terminals of the plurality of self-reference delay cell circuits 210, and an adder 230 coupled to the output terminals of the plurality of phase detectors 200. In some embodiments, the adder 230 generates a multi-bit output (iOUT<4:0>) that represents the time difference between an incoming up-signal and an incoming down-signal, for example as a thermometer code. Thus, in some embodiments, the adder 230 can be an adder-based therm2 bin.

[0028] In various embodiments, the mapping logic 240 is further coupled to the adder 230 and is configured to map the multi-bit output to a digital code (e.g., OUT<3:0>) that is at least one bit smaller than the multi-bit output and quantifies the time difference. Since the digital code is encoded into less than all the outputs from the plurality of phase detectors 220, the mapping logic 240 can be used. However, in these embodiments, a larger (and 2 N ) number of delay cell circuit / phase detector pairs is included such that it is easier to transform the control signal values between the plurality of self-reference delay cell circuits 210, as will be described in more detail. Thus, in some embodiments, the mapping logic 240 can include saturation logic, chopper demodulation logic, and TDC_NBIT logic to convert the 5-bit output of the adder 230 to a 4-bit output of the mapping logic 240. Although specific numbers of bits are shown in these outputs, different embodiments may vary the number of bits in these outputs.

[0029]

[0030] Table 1

[0031] In the disclosed embodiments, further referring to Figure 2A - 2B and Table 1, control logic (e.g., DEM logic 206) is configured to generate a first control signal to selectively control a first set of capacitors 214A of a plurality of self - reference delay unit circuits 210, wherein a corresponding first control signal in the first control signal includes an up - value (k1). In the disclosed embodiments, the control logic is further configured to generate a second control signal to selectively control a second set of capacitors 214B of the plurality of self - reference delay unit circuits 210, wherein a corresponding second control signal in the second control signal includes a down - value (k2).

[0032] In these embodiments, the control logic is configured to change the up - value relative to the down - value in the first and second control signals. There are multiple ways to do this, but one way is as shown in Table 1, where the k1 value and the k2 value are programmed in a ping - pong manner, increasing or decreasing one k value in one round - trip, e.g., increasing k1 and then decreasing k2, and so on, repeating the increase of k1 and the decrease of k2. It can be seen that the positive threshold and the negative threshold are symmetric by exchanging the k1 / k2 settings between the plurality of self - reference delay unit circuits 210. Thus, in some embodiments, the control logic is configured to alternately increment the up - value within a corresponding first control signal in the first control signal and decrement the down - value within a corresponding second control signal in the second control signal, as shown in Table 1. However, the control logic can also be configured to alternately increment the up - value within a corresponding first control signal in the first control signal and decrement the down - value within a corresponding second control signal in the second control signal.

[0033] In at least some embodiments, the control logic is configured to generate the first control signal and the second control signal in control signal pairs, with one control signal pair being provided to each respective self - reference delay unit circuit. In these embodiments, the control logic is further configured to rotate the control signal pairs over time to different self - reference delay unit circuits of the plurality of self - reference delay unit circuits 210 according to one of an ordered pattern or a pseudo - random pattern. This rotation of values further reduces the likelihood of forming any type of systematic and random offset between the self - reference delay unit circuits 210 in the plurality of self - reference delay unit circuits 210.

[0034] Referring to Figure 2A - 2Band Table 1, according to an exemplary embodiment, the first self - reference delay unit circuit 210A is coupled to the control logic and includes a first set of capacitors 214A coupled to a first node 215B between the first positive input (INP) and the first positive output. The first set of capacitors 214A is selectively controlled by a first control signal from the control logic, and the first control signal includes a first upward value corresponding to a first positive threshold (e.g., k1 = 0). A second set of capacitors 214B is coupled to a second node 215B between the first negative input (INN) and the first negative output. The second set of capacitors 214B is selectively controlled by a second control signal from the control logic, and the second control signal includes a first downward value corresponding to a first negative threshold (e.g., k2 = 7).

[0035] In an exemplary embodiment, the second self - reference delay unit circuit 210B is coupled to the control logic and includes a third set of capacitors coupled to a third node between the second positive input and the second positive output. The third set of capacitors is selectively controlled by a third control signal from the control logic, and the third control signal includes a second upward value equal to the first upward value (e.g., k1 = 0). The second self - reference delay unit circuit 210B further includes a fourth set of capacitors coupled to a fourth node between the second negative input and the second negative output. The fourth set of capacitors is selectively controlled by a fourth control signal from the control logic, and the fourth control signal includes a second downward value equal to the first downward value minus one (e.g., k2 = 6).

[0036] In an exemplary embodiment, the third self - reference delay unit circuit 210C is coupled to the control logic and includes a fifth set of capacitors coupled to a fifth node between the third positive input and the third positive output. The fifth set of capacitors is selectively controlled by a fifth control signal from the control logic, and the fifth control signal includes a second upward value equal to the first upward value plus one (e.g., k1 = 1). The third self - reference delay unit circuit 210C further includes a sixth set of capacitors coupled to a sixth node between the third negative input and the third negative output. The sixth set of capacitors is selectively controlled by the fourth control signal from the control logic, and the fourth control signal includes a second downward value equal to the first downward value minus one (e.g., k2 = 6).

[0037] In an exemplary embodiment, a fourth self-reference delay cell circuit 210N is coupled to control logic and includes a seventh set of capacitors coupled to a seventh node between a fourth positive input and a fourth positive output. The seventh set of capacitors is selectively controlled by a seventh control signal from the control logic, the seventh control signal including a second rising value equal to a first falling value minus one (e.g., k1 = 6). The fourth self-reference delay cell circuit 210N further includes an eighth set of capacitors coupled to an eighth node between a fourth negative input and a fourth negative output. The eighth set of capacitors is selectively controlled by an eighth control signal from the control logic, the eighth control signal including a second falling value equal to a first rising value plus one (k2 = 1).

[0038] In an exemplary embodiment, a fifth self-reference delay cell circuit 210O is coupled to control logic and includes a ninth set of capacitors coupled to a ninth node between a fifth positive input and a fifth positive output. The ninth set of capacitors is selectively controlled by a ninth control signal from the control logic, the ninth control signal including a second rising value equal to a first falling value minus one (e.g., k1 = 6). The fifth self-reference delay cell circuit 210O further includes a tenth set of capacitors coupled to a tenth node between a fifth negative input and a fifth negative output. The tenth set of capacitors is selectively controlled by a tenth control signal from the control logic, the tenth control signal including a second falling value equal to a first rising value (e.g., k2 = 0).

[0039] In an exemplary embodiment, a sixth self-reference delay cell circuit 210P is coupled to control logic and includes an eleventh set of capacitors coupled to an eleventh node between a sixth positive input and a sixth positive output. The eleventh set of capacitors is selectively controlled by an eleventh control signal from the control logic, the eleventh control signal including a second rising value equal to a first falling value (e.g., k1 = 7). The sixth self-reference delay cell circuit 210P further includes a twelfth set of capacitors coupled to a twelfth node between a sixth negative input and a sixth negative output. The twelfth set of capacitors is selectively controlled by a twelfth control signal from the control logic, the twelfth control signal including a second falling value equal to a first rising value (k2 = 0).

[0040] In an exemplary embodiment, at least a seventh self-reference delay cell circuit (somewhere in the middle of a plurality of self-reference delay element circuits 210) is coupled to control logic and includes a thirteenth group of capacitors coupled to a thirteenth node between a seventh positive input and a seventh positive output. The thirteenth group of capacitors is selectively controlled by a thirteenth control signal from the control logic, and the thirteenth control signal includes a second upward value (e.g., k1 = 3). The seventh self-reference delay cell circuit further includes a fourteenth group of capacitors coupled to a fourteenth node between a seventh negative input and a seventh negative output. The fourteenth group of capacitors is selectively controlled by a fourteenth control signal from the control logic, and the fourteenth control signal includes a second downward value equal to the second upward value (e.g., k2 = 3).

[0041] In a further embodiment, the control logic may change the generation of the values of the first control signal (k1) and the second control signal (k2) in a manner that does not follow Table 1. For example, Table 2 may streamline the method that can minimize power consumption.

[0042]

[0043]

[0044] Table 2

[0045] In a further embodiment, if desired and / or acceptable in a particular TDC circuit, the range of the TDC circuit 200 may be reduced, which increases the frequency of the spurious tones generated by the DEM logic 206. For example, Table 3 shows the values of the first control signal (k1) and the second control signal (k2) for implementing a 4-bit TDC circuit, which rotate through 15 states and generate spurious tones at fref / 15 and its harmonics, where "fref" is the DEM logic clock frequency.

[0046] Status number k1 k2 k1 - k2 1 0 7 -7 2 0 6 -6 3 1 6 -5 4 1 5 -4 5 2 5 -3 6 2 4 -2 7 3 4 -1 8 3 3 0 9 4 3 1 10 4 2 2 11 5 2 3 12 5 1 4 13 6 1 5 14 6 0 6 15 7 0 7

[0047] Table 3

[0048] As another example, Table 4 illustrates the values of the first control signal (k1) and the second control signal (k2) for implementing a 2-bit TDC circuit, which rotate through 3 states and generate spurious tones at fref / 3 and its harmonics.

[0049]

[0050]

[0051] Table 4

[0052] As another example, Table 5 illustrates the values of the first control signal (k1) and the second control signal (k2) for implementing a 2.5-bit TDC circuit, which rotate in 5 states and generate spurious tones and their harmonics at fref / 5.

[0053] Status number k1 k2 k1 - k2 1 0 2 -2 1 0 2 -2 1 0 2 -2 2 0 1 -1 2 0 1 -1 2 0 1 -1 3 0 0 0 3 0 0 0 3 0 0 0 4 1 0 1 4 1 0 1 4 1 0 1 5 2 0 2 5 2 0 2 5 2 0 2

[0054] Table 5

[0055] Figure 3 is a flowchart of a method 300 for controlling a plurality of self-referenced delay cell circuits according to at least some embodiments. Method 300 may be executed by processing logic including hardware, software, firmware, or any combination thereof. For example, method 300 may be executed by the TDC circuit 200, specifically, by the DEM logic 206 of the TDC circuit 200. Although shown in a particular order or sequence, the order of the flow may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood only as examples, and the illustrated processes may be executed in a different order, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0056] In operation 310, the processing logic generates a plurality of first control signals (e.g., k1) to selectively control a first set of capacitors of a plurality of self-referenced delay cell circuits, wherein a corresponding first control signal among the plurality of first controller signals includes an up value.

[0057] In operation 320, the processing logic generates a plurality of second control signals (e.g., k2) to selectively control a second set of capacitors of a plurality of self-referenced delay cell circuits, wherein a corresponding third control signal among the plurality of third control signals includes a down value, and the up value varies with respect to the down value among the plurality of first control signals and the second control signals.

[0058] In operation 325, the processing logic optionally alternately increments the up value within a corresponding first control signal among the plurality of first control signals and decrements the down value within a corresponding second control signal among the plurality of second control signals.

[0059] In operation 335, the processing logic optionally alternately decrements the up value of a corresponding first control signal among the plurality of first control signals and increments the down value of a corresponding second control signal among the plurality of second control signals.

[0060] In operation 340, the processing logic optionally generates the first control signal and the second control signal in pairs of control signals, and a pair of control signals is provided to each corresponding self-referenced delay cell circuit.

[0061] In operation 350, the processing logic selectively rotates the control signal pair to different self-reference delay unit circuits of the self-reference delay unit circuit according to one of a sequential pattern or a pseudo-random pattern.

[0062] Other variations are within the scope of the present disclosure. Thus, while the disclosed techniques are susceptible to various modifications and alternative configurations, certain illustrated embodiments thereof are shown in the drawings and described in detail above. However, it is to be understood that the intention is not to limit the disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, alternative configurations, and equivalents falling within the spirit and scope of the appended claims.

[0063] In the context of describing the disclosed embodiments (particularly in the context of the following claims), the use of the terms "a," "an," and "the," and similar referents should be construed to include both the singular and the plural unless otherwise indicated herein or the context clearly dictates otherwise, rather than as a definition of the term. Unless otherwise indicated, the terms "comprising," "having," "including," and "containing" should be construed as open-ended terms (i.e., "including but not limited to"). "Connected," when unmodified and referring to physical connection, should be construed to mean partially or wholly contained in, attached to, or joined together, even if there is intervening. Unless otherwise indicated herein, the reference to a numerical range herein is only a shorthand method for separately referring to each individual numerical value within the range, and each individual numerical value is incorporated into the specification as if it were separately recited herein. In at least one embodiment, unless the context otherwise indicates or is inconsistent, the use of the term "set" (e.g., "a set of items") or "subset" should be construed to mean a non-empty set containing one or more members. Further, unless the context otherwise indicates or is inconsistent, the term "subset" of a corresponding set does not necessarily denote a proper subset of the corresponding set, but the subset and the corresponding set may be equal.

[0064] Unless otherwise expressly stated or clearly contradicted by the context, conjunctive language, such as phrases in the form of "at least one of A, B, and C" or "at least one among A, B, and C", is generally understood in context to mean that the items, terms, etc. can be A, B, or C, or any non - empty subset of the set of A, B, and C. For example, in an example of a set with three members, the conjunctive phrases "at least one of a, B, and C" and "at least one among A, B, and C" refer to any one of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language generally does not mean that certain embodiments require the presence of at least one of A, at least 1 of B, and at least 2 of C. Further, unless the context otherwise indicates or contradicts, the term "plural" indicates a plural state (e.g., "plural items" means multiple items). In at least one embodiment, the number of items among the multiple items is at least two, but can be more if expressly or indicated by context. Additionally, unless otherwise stated or clearly provided by the context, the phrase "based on" means "at least partially based on" rather than "based solely on"

[0065] Unless otherwise specified herein or unless the context clearly dictates otherwise, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, a process such as those described herein (or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with executable instructions and implemented by hardware or a combination thereof as code collectively executed on one or more processors (e.g., executable instructions, one or more computer programs, or one or more applications). In at least one embodiment, the code is stored in a computer-readable storage medium in the form of a computer program that includes a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that does not include transient signals (e.g., propagating transient electrical or electromagnetic transmissions), but includes non-transitory data storage circuits (e.g., buffers, caches, and queues) within a transient signal transceiver. In at least one embodiment, the code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media that store executable instructions (or other memory storing the executable instructions), which, when executed (i.e., as a result of execution) by one or more processors of a computer system, cause the computer system to perform the operations described herein. In at least one embodiment, a set of non-temporary computer-readable storage media includes a plurality of non-temporary computer-readable storage media and one or more individual non-temporary storage media of the plurality of non-temporary computer-readable storage media lack all of the code, while the plurality of non-temporary computer-readable storage media together store all of the code. In at least one embodiment, the execution of the executable instructions causes different instructions to be executed by different processors.

[0066] Thus, in at least one embodiment, a computer system is configured to implement one or more services that, individually or collectively, perform the operations of the processes described herein, and such computer system is configured with suitable hardware and / or software capable of performing the operations. Additionally, a computer system implementing at least one embodiment of the present invention is a single device, and in another embodiment, is a distributed computer system of devices including multiple different operations such that the distributed computer system performs the operations described herein and such that a single device does not perform all of the operations.

[0067] Any and all examples or exemplary language provided herein (e.g., “such as”) are merely used to better illustrate embodiments of the present invention and do not limit the scope of the present invention unless otherwise stated. No language in the specification should be construed as indicating that any non-claimed element is essential to the practice of the present invention.

[0068] All references cited herein, including publications, patent applications, and patents, are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and set forth in full herein.

[0069] In the specification and claims, the terms "coupled" and "connected" and their derivatives may be used. It should be understood that these terms are not necessarily synonyms of each other. Instead, in a particular example, "connected" or "coupled" may be used to indicate that there is a direct or indirect physical or electrical contact between two or more elements. "Coupled" may also mean that two or more elements are not in direct contact, but still cooperate or interact with each other.

[0070] Unless otherwise specifically stated, it can be understood that throughout the specification, terms such as "processing", "computing", "operation", "determination", etc. refer to the operations and / or processes of a computer or computing system or similar electronic computing device, and these operations and / or conversions represent physical data, such as the conversion of quantities in the registers and / or memories of an electronic data, computing system into other data, and similarly represented as physical quantities in the memories, registers or other such information storage, transmission or display devices of the computing system.

[0071] In a similar manner, the term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memories and converts that electronic data into other electronic data that can be stored in registers and / or memories. As a non-limiting example, a "processor" can be a network device or a MACsec device. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Additionally, each process may refer to multiple processes for executing instructions sequentially or in parallel, continuously or intermittently. In at least one embodiment, the terms "system" and "method" may be used interchangeably herein, provided that a system can include one or more methods and a method can be regarded as a system.

[0072] In this document, obtaining, acquiring, receiving analog or digital data, or inputting it into a subsystem, computer system, or computer-implemented machine may be mentioned. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways, such as by receiving the data as a parameter of a function call or an application programming interface call. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting the data through a serial or parallel interface. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting the data from a providing entity to an obtaining entity over a computer network. In at least one embodiment, providing, outputting, transmitting, sending, or presenting analog or digital data may also be mentioned. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by using the data as an input or output parameter of a function call, a parameter of an application programming interface, or an interprocess communication mechanism.

[0073] Although the description herein sets forth example embodiments of the technology, other architectures may be used to implement the functionality and are intended to be within the scope of the present invention. Additionally, although specific assignments of responsibilities may have been defined above for purposes of description, the different functions and responsibilities may be assigned and divided in different ways depending on the circumstances.

[0074] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claims.

Claims

1. A time-to-digital converter (TDC) circuit, comprising: Control logic; And A plurality of self-reference delay unit circuits coupled to the control logic, wherein the plurality of self-reference delay unit circuits includes a first self-reference delay unit circuit, and the first self-reference delay unit circuit includes: A first set of capacitors coupled to a first node between a first positive input and a first positive output, wherein the first set of capacitors is selectively controlled by a first control signal from the control logic, and the first control signal includes a first up value corresponding to a first positive threshold; A second set of capacitors coupled to a second node between a first negative input and a first negative output, wherein the second set of capacitors is selectively controlled by a second control signal from the control logic, and the second control signal includes a first down value corresponding to a first negative threshold; A plurality of phase detectors coupled to respective outputs of the plurality of self-reference delay unit circuits; and An adder coupled to the outputs of the plurality of phase detectors, the adder being configured to generate a multi-bit output that represents a time difference between an incoming up signal and an incoming down signal.

2. The TDC circuit according to claim 1, wherein the plurality of self-reference delay unit circuits further includes: A second self-reference delay unit circuit coupled to the control logic, wherein the second self-reference delay unit circuit includes: A third set of capacitors coupled to a third node between a second positive input and a second positive output, wherein the third set of capacitors is selectively controlled by a third control signal from the control logic, and the third control signal includes a second up value equal to the first up value; and A fourth set of capacitors coupled to a fourth node between a second negative input and a second negative output, wherein the fourth set of capacitors is selectively controlled by a fourth control signal from the control logic, and the fourth control signal includes a second down value equal to the first down value minus one.

3. The TDC circuit according to claim 1, wherein the plurality of self-reference delay unit circuits further includes: A second self-reference delay unit circuit coupled to the control logic, wherein the second self-reference delay unit circuit includes: A third set of capacitors coupled to a third node between a second positive input and a second positive output, wherein the third set of capacitors is selectively controlled by a third control signal from the control logic, and the third control signal includes a second up value equal to the first up value plus one; and A fourth set of capacitors coupled to a fourth node between a second negative input and a second negative output, wherein the fourth set of capacitors is selectively controlled by a fourth control signal from the control logic, and the fourth control signal includes a second down value equal to the first down value minus one.

4. The TDC circuit according to claim 1, wherein the plurality of self-reference delay unit circuits further includes: A second self-reference delay unit circuit coupled to the control logic, wherein the second self-reference delay unit circuit includes: A third set of capacitors, coupled to a third node between a second positive input and a second positive output, wherein the third set of capacitors is selectively controlled by a third control signal from the control logic, the third control signal including a second up value; and A fourth set of capacitors, coupled to a fourth node between a second negative input and a second negative output, wherein the fourth set of capacitors is selectively controlled by a fourth control signal from the control logic, the fourth control signal including a second down value equal to the second up value.

5. The TDC circuit according to claim 1, wherein the plurality of self-reference delay unit circuits further comprises: A second self-reference delay unit circuit, coupled to the control logic, wherein the second self-reference delay unit circuit comprises: A third set of capacitors, coupled to a third node between a second positive input and a second positive output, wherein the third set of capacitors is selectively controlled by a third control signal from the control logic, the third control signal including a second up value equal to the first down value; and A fourth set of capacitors, coupled to a fourth node between a second negative input and a second negative output, wherein the fourth set of capacitors is selectively controlled by a fourth control signal from the control logic, the fourth control signal including a second down value equal to the first up value.

6. The TDC circuit according to claim 1, wherein the plurality of self-reference delay unit circuits further comprises: A second self-reference delay unit circuit, coupled to the control logic, wherein the second self-reference delay unit circuit comprises: A third set of capacitors, coupled to a third node between a second positive input and a second positive output, wherein the third set of capacitors is selectively controlled by a third control signal from the control logic, the third control signal including a second up value equal to the first down value minus one; and A fourth set of capacitors, coupled to a fourth node between a second negative input and a second negative output, wherein the fourth set of capacitors is selectively controlled by a fourth control signal from the control logic, the fourth control signal including a second down value equal to the first up value.

7. The TDC circuit according to claim 1, wherein the plurality of self-reference delay unit circuits further comprises: A second self-reference delay unit circuit, coupled to the control logic, wherein the second self-reference delay unit circuit comprises: A third set of capacitors, coupled to a third node between a second positive input and a second positive output, wherein the third set of capacitors is selectively controlled by a third control signal from the control logic, the third control signal including a second up value equal to the first down value minus one; and A fourth set of capacitors, coupled to a fourth node between a second negative input and a second negative output, wherein the fourth set of capacitors is selectively controlled by a fourth control signal from the control logic, the fourth control signal including a second down value equal to the first up value plus one.

8. A time-to-digital converter (TDC) circuit, comprising: Control logic; A plurality of self-reference delay cell circuits, coupled to the control logic, wherein each self-reference delay cell circuit of the plurality of self-reference delay cell circuits includes: A first inverter, serially coupled to a second inverter, the first inverter receiving a positive time signal representative of an incoming upstream signal; A third inverter, serially coupled to a fourth inverter, the third inverter receiving a negative time signal representative of an incoming downstream signal; A first set of capacitors, coupled to a first node between the first inverter and the second inverter, wherein the first set of capacitors is selectively controlled by a first control signal from the control logic, the first control signal corresponding to a positive threshold; and A second set of capacitors, coupled to a second node between the third inverter and the fourth inverter, wherein the second set of capacitors is selectively controlled by a second control signal from the control logic, the second control signal corresponding to a negative threshold; A plurality of phase detectors, coupled to corresponding outputs of the plurality of self-reference delay cell circuits; and An adder, coupled to outputs of the plurality of phase detectors, the adder generating a multi-bit output, the multi-bit output representing a time difference between the incoming upstream signal and the incoming downstream signal.

9. The TDC circuit of claim 8, further comprising mapping logic coupled to the adder, the mapping logic mapping the multi-bit output to a digital code that is at least one bit smaller than the multi-bit output and quantizes the time difference.

10. The TDC circuit of claim 8, wherein the capacitors in the first set of capacitors are the same in size and number as the capacitors in the second set of capacitors.

11. The TDC circuit of claim 8, wherein the control logic is configured to: Generate a plurality of first control signals to selectively control the first set of capacitors of the plurality of self-reference delay cell circuits, wherein each of the plurality of first control signals includes an upstream value; and Generate a plurality of second control signals to selectively control the second set of capacitors of the plurality of self-reference delay cell circuits, wherein each of the plurality of second control signals includes a downstream value, and wherein the upstream value varies relative to the downstream value among the plurality of first control signals and the plurality of second control signals.

12. The TDC circuit of claim 11, wherein the plurality of first control signals and the plurality of second control signals are generated as control signal pairs, one control signal pair being provided to each corresponding self-reference delay cell circuit, and wherein the control logic further rotates the control signal pairs to different self-reference delay cell circuits among the plurality of self-reference delay cell circuits over time according to one of a sequential pattern or a pseudo-random pattern.

13. The TDC circuit of claim 11, wherein the control logic further alternately increments the upstream value within the corresponding first control signal of the plurality of first control signals and decrements the downstream value within the corresponding second control signal of the plurality of second control signals.

14. The TDC circuit according to claim 11, wherein the control logic further alternately decrements the up value in the corresponding first control signal among the plurality of first control signals and increments the down value in the corresponding second control signal among the plurality of second control signals.

15. A phase-locked loop PLL, comprising: A phase frequency detector; A digitally controlled oscillator DCO; And A time-to-digital converter TDC circuit coupled between the phase frequency detector and the DCO, the TDC circuit comprising: Control logic; and A first self-reference delay unit circuit coupled to the control logic, wherein the first self-reference delay unit circuit comprises: A first group of capacitors coupled to a first node between a first positive input and a first positive output, wherein the first group of capacitors is selectively controlled by a first control signal from the control logic, the first control signal comprising a first up value corresponding to a first positive threshold; and A second group of capacitors coupled to a second node between the first positive input and the first positive output, wherein the second group of capacitors is selectively controlled by a second control signal from the control logic, the second control signal comprising a first down value corresponding to a first negative threshold, A digital integration path circuit coupled between the TDC circuit and the DCO; and An analog proportional path circuit coupled between the phase frequency detector and the DCO.

16. The PLL according to claim 15, wherein the first node receives a positive time signal representing an incoming up signal, the second node receives a negative time signal representing an incoming down signal, and wherein the TDC circuit further comprises: A plurality of self-reference delay unit circuits identical to the first self-reference delay unit circuit; A plurality of phase detectors coupled to the respective outputs of the plurality of self-reference delay unit circuits; An adder coupled to the outputs of the plurality of phase detectors, the adder generating a multi-bit output representing the time difference between the incoming up signal and the incoming down signal; And Mapping logic coupled to the adder, the mapping logic mapping the multi-bit output to a digital code that is at least one bit smaller than the multi-bit output and quantifies the time difference.

17. The PLL according to claim 15, wherein the TDC circuit further comprises: A second self-reference delay unit circuit coupled to the control logic, wherein the second self-reference delay unit circuit comprises: A third group of capacitors coupled to a third node between a second positive input and a second positive output, Wherein the third group of capacitors is selectively controlled by a third control signal from the control logic, the third control signal comprising a second up value equal to the first up value; and A fourth group of capacitors coupled to a fourth node between a second negative input and a second negative output, Wherein the fourth group of capacitors is selectively controlled by a fourth control signal from the control logic, the fourth control signal comprising a second down value equal to the first down value minus one.

18. The PLL according to claim 15, wherein the TDC circuit further comprises: A second self-reference delay cell circuit, coupled to the control logic, wherein the second self-reference delay cell circuit includes: A third group of capacitors, coupled to a third node between a second positive input and a second positive output, wherein the third group of capacitors is selectively controlled by a third control signal from the control logic, the third control signal including a second up value equal to the first up value; and A fourth group of capacitors, coupled to a fourth node between a second negative input and a second negative output, wherein the fourth group of capacitors is selectively controlled by a fourth control signal from the control logic, the fourth control signal including a second down value equal to the first down value minus one.

19. The PLL of claim 15, wherein the TDC circuit further includes: A second self-reference delay cell circuit, coupled to the control logic, wherein the second self-reference delay cell circuit includes: A third group of capacitors, coupled to a third node between a second positive input and a second positive output, wherein the third group of capacitors is selectively controlled by a third control signal from the control logic, the third control signal including a second up value equal to the first up value plus one; and A fourth group of capacitors, coupled to a fourth node between a second negative input and a second negative output, wherein the fourth group of capacitors is selectively controlled by a fourth control signal from the control logic, the fourth control signal including a second down value equal to the first down value minus one.

20. The PLL of claim 15, wherein the TDC circuit further includes: A second self-reference delay cell circuit, coupled to the control logic, wherein the second self-reference delay cell circuit includes: A third group of capacitors, coupled to a third node between a second positive input and a second positive output, wherein the third group of capacitors is selectively controlled by a third control signal from the control logic, the third control signal including a second up value; and A fourth group of capacitors, coupled to a fourth node between a second negative input and a second negative output, wherein the fourth group of capacitors is selectively controlled by a fourth control signal from the control logic, the fourth control signal including a second down value equal to the second up value.

21. The PLL of claim 15, wherein the TDC circuit further includes: A second self-reference delay cell circuit, coupled to the control logic, wherein the second self-reference delay cell circuit includes: A third group of capacitors, coupled to a third node between a second positive input and a second positive output, wherein the third group of capacitors is selectively controlled by a third control signal from the control logic, the third control signal including a second up value equal to the first down value; and A fourth group of capacitors, coupled to a fourth node between a second negative input and a second negative output, wherein the fourth group of capacitors is selectively controlled by a fourth control signal from the control logic, the fourth control signal including a second down value equal to the first up value.

22. The PLL of claim 15, wherein the TDC circuit further includes: A second self-reference delay cell circuit, coupled to the control logic, wherein the second self-reference delay cell circuit includes: A third group of capacitors, coupled to a third node between a second positive input and a second positive output, wherein the third group of capacitors is selectively controlled by a third control signal from the control logic, the third control signal including a second up value equal to the first down value minus one; and A fourth group of capacitors, coupled to a fourth node between a second negative input and a second negative output, wherein the fourth group of capacitors is selectively controlled by a fourth control signal from the control logic, the fourth control signal including a second down value equal to the first up value.

23. The PLL of claim 15, wherein the TDC circuit further includes: A second self-reference delay cell circuit, coupled to the control logic, wherein the second self-reference delay cell circuit includes: A third group of capacitors, coupled to a third node between a second positive input and a second positive output, wherein the third group of capacitors is selectively controlled by a third control signal from the control logic, the third control signal including a second up value equal to the first down value minus one; and A fourth group of capacitors, coupled to a fourth node between a second negative input and a second negative output, wherein the fourth group of capacitors is selectively controlled by a fourth control signal from the control logic, the fourth control signal including a second down value equal to the first up value plus one.

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