A voltage pre-regulation circuit

Abstract

The present invention provides a voltage pre-regulation circuit, comprising a first resistor (R0), a Zener diode (D0) connected in series with the first resistor (R0), a first MOS tube (M0) whose G pole is connected to the negative pole of the Zener diode (D0), a transistor (Q0) whose base is connected to the negative pole of the Zener diode (D0), a first current mirror connected to the positive pole of the Zener diode (D0) and the emitter of the transistor (Q0), a second current mirror connected to the first resistor (R0) and the D pole of the first MOS tube (M0), a second MOS tube (M3) whose G pole and S pole are connected to the first current mirror and whose D pole is connected to the second current mirror, and a capacitor (C0) and a source follower connected to the second current mirror and arranged in parallel. The voltage pre-regulation circuit described in the present invention does not need to use a comparator and an additional bandgap reference circuit, greatly simplifies the circuit, and saves chip power consumption and area.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and in particular to a voltage pre-regulation circuit. Background Art

[0002] With the widespread use of embedded electronic products in industry, some industrial chips need to work in a high power supply voltage environment in actual applications. For example, in the application of automotive electronics with a standard voltage of 12V, the power supply voltage may soar to 40V as the working state changes. For a higher power supply voltage, it may cause the internal transistors of the chip to break down, causing irreversible damage to the chip. In order to meet the requirements of working under unstable high power supply voltage, the power supply voltage is usually pre-adjusted to generate a stable low voltage power supply to power the chip, thereby ensuring that the chip can work normally.

[0003] The scheme in "Design of adjustable multi-value reference voltage source with wide power supply input range" (Chen Zhi, University of Electronic Science and Technology of China, 2011) is as follows Figure 1 As shown, V IN is the power supply voltage before pre-adjustment (7V~40V), V OUT is the power supply voltage after pre-adjustment (about 10V), V OUT Used to supply subsequent chips. IN >10V, V OUT is fixed at 10V; when V IN <10V, V OUT Follow V IN Change, that is, V OUT =V IN The working principle of this voltage pre-regulation circuit is as follows:

[0004] In V IN For high voltage (V IN >10V), the voltage V at point X X for:

[0005]

[0006] V X >V REF (V REF is the reference voltage generated by the bandgap reference circuit), comparator COMP1 outputs a low level, turning off M1 and M4, the current in the branch where R4, R5, and M1 are located is 0, and the gate potential of M2 is V IN , so M2 is turned off. In addition, R6 is connected in series with N diode-connected MOS tubes, and the current in the branch where R6 is located can be expressed as:

[0007]

[0008] Because the gate potential of M3 tube is N·V GS , so the output voltage of the voltage pre-regulator circuit is V OUT for:

[0009] V OUT =N·V GS -V GS3 (3)

[0010] In order to save power consumption, the resistance of R6 should be large enough, because the voltage drop of R6 in this branch accounts for most of the power supply voltage. The current on R6 will change with the power supply voltage, but due to the IV square law of MOS tube, when I changes, M5~M 15 The gate-source voltage V GS The change is not large, so relative to V IN It is a relatively stable voltage.

[0011] In V IN For low voltage (V IN <10V), comparator COMP1 outputs a high level, M1 is turned on, and the gate-source voltage of M2 is:

[0012]

[0013] Therefore, M2 is turned on, and V IN With V OUT short-circuit, thereby achieving V OUT =V IN In addition, M4 is used to realize the function of hysteresis comparator. IN When it is low, M4 is turned on, V X is the voltage divided by R1 and R2; in contrast, when V IN When it is higher, M4 is turned off and V X It is the voltage divider of R1, R2 and R3.

[0014] Specifically, when V IN From low to high threshold voltage V H When the comparator COMP1 output level drops to a low level, M1 and M4 are turned off, and the gate-source voltage of M2 is 0, making V OUT As shown in formula (3). Here, the high threshold voltage V H It can be expressed as:

[0015]

[0016] When V IN From high to low threshold voltage V L When the output of comparator COMP1 rises to a high level, M1 and M4 change from off to on. At this time, M2 is turned on, achieving V OUT =VIN Here the low threshold voltage V L It can be expressed as:

[0017]

[0018] Since V L Not equal to V H , thus realizing the hysteresis function.

[0019] In summary, the voltage pre-regulation circuit in the above technical solution has an output that follows the input when the power supply voltage is low, and a stable output at a certain characteristic voltage when the power supply voltage is high, thereby ensuring that the subsequent chip can work at a stable and smaller power supply voltage, thus protecting the subsequent chip. The existing technical problems are: the circuit is highly complex, and in order to realize the voltage pre-regulation function, it needs to use an additional comparator and an additional bandgap reference circuit to generate V REF , this additional bandgap reference circuit will also waste additional static power consumption and chip area. Summary of the invention

[0020] The present invention aims to overcome the technical problems in the prior art that the circuit is highly complex and requires the use of additional comparators and bandgap reference circuits, resulting in waste of additional static power consumption and chip area. A novel voltage pre-adjustment circuit is provided, which does not require the use of comparators and additional bandgap reference circuits, greatly simplifies the circuit, and saves chip power consumption and area.

[0021] The present invention provides a voltage pre-regulation circuit, comprising a first resistor, a Zener diode connected in series with the first resistor, a first MOS tube connected with a G pole and a negative pole of the Zener diode, a triode connected with a base and a negative pole of the Zener diode, a first current mirror connected with a positive pole of the Zener diode and an emitter of the triode, a second current mirror connected with the first resistor and a D pole of the first MOS tube, a second MOS tube connected with a G pole and an S pole with the first current mirror and a D pole with the second current mirror, and a capacitor and a source follower connected with the second current mirror and arranged in parallel; the S pole of the first MOS tube is connected with a collector of the triode; the capacitor is connected with a positive pole of the Zener diode; and two ends of the source follower are respectively connected with the first resistor and the positive pole of the Zener diode.

[0022] A voltage pre-regulation circuit described in the present invention, as a preferred embodiment, the first current mirror includes a second resistor, a third MOS tube and a fourth MOS tube; one end of the second resistor is connected to the emitter of the triode and the G pole of the second MOS tube, and the other end of the second resistor is connected to the G pole and the D pole of the third MOS tube and the G pole of the fourth MOS tube; the S pole of the third MOS tube is connected to the S pole of the fourth MOS tube, the positive pole of the Zener diode, the second current mirror, the capacitor and the source follower; the S pole of the fourth MOS tube is connected to the S pole of the third MOS tube, the positive pole of the Zener diode, the second current mirror, the capacitor and the source follower, and the D pole of the fourth MOS tube is connected to the second current mirror.

[0023] In a voltage pre-regulation circuit described in the present invention, as a preferred embodiment, the second current mirror includes a third resistor, a fifth MOS tube and a sixth MOS tube; one end of the third resistor is connected to the positive electrode of the Zener diode, the first current mirror, a capacitor and a source follower, and the other end of the third resistor is connected to the D pole of the sixth MOS tube, the capacitor and the source follower; the D pole of the fifth MOS tube is connected to the D pole of the second MOS tube and the G pole of the sixth MOS tube, the G pole of the fifth MOS tube is connected to the G pole of the sixth MOS tube, the S pole of the fifth MOS tube is connected to the S pole of the sixth MOS tube, the D pole of the first MOS tube, the first resistor and the source follower; the S pole of the sixth MOS tube is connected to the S pole of the fifth MOS tube, the D pole of the first MOS tube, the first resistor and the source follower.

[0024] A voltage pre-regulation circuit described in the present invention, as a preferred embodiment, the source follower includes a seventh MOS tube and a current source, the G pole of the seventh MOS tube is connected to the second current mirror and the capacitor, the D pole of the seventh MOS tube is connected to the second current mirror, the D pole of the first MOS tube and the first resistor, the S pole of the seventh MOS tube is connected to the current source input end; the output end of the current source is connected to the positive pole of the Zener diode, the first current mirror, the second current mirror and the capacitor.

[0025] In the voltage pre-regulation circuit described in the present invention, as a preferred embodiment, the Zener diode can be replaced by a diode-connected MOS tube string or a BJT tube string.

[0026] In the voltage pre-regulation circuit described in the present invention, as a preferred embodiment, the first MOS tube is a depletion-type MOS tube.

[0027] In the voltage pre-regulation circuit described in the present invention, as a preferred embodiment, the seventh MOS tube is a depletion-type MOS tube.

[0028] The present invention has the following advantages: while realizing voltage pre-adjustment, the circuit structure is greatly simplified. Compared with the prior art, no additional comparator and bandgap reference circuit are required, which greatly reduces the circuit complexity, power consumption and area. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a voltage pre-adjustment circuit diagram in the prior art;

[0030] Figure 2 The present invention is a circuit diagram of a voltage pre-regulation.

[0031] Reference numerals:

[0032] R0, the first resistor; R1, the second resistor; R2, the third resistor; D0, the Zener diode; Q0, the transistor; M0, the first MOS transistor; M1, the third MOS transistor; M2, the fourth MOS transistor; M3, the second MOS transistor; M4, the fifth MOS transistor; M5, the sixth MOS transistor; M6, the seventh MOS transistor; C0, the capacitor; I0, the current source. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0034] Example 1

[0035] like Figure 2 As shown, a voltage pre-regulation circuit includes a first resistor R0, a Zener diode D0 connected in series with the first resistor R0, a first MOS tube M0 connected with the negative electrode of the Zener diode D0 at the G pole, a transistor Q0 connected with the negative electrode of the Zener diode D0 at the base, a first current mirror connected with the positive electrode of the Zener diode D0 and the emitter of the transistor Q0, a second current mirror connected with the first resistor R0 and the D pole of the first MOS tube M0, a second MOS tube M3 connected with the G pole and the S pole of the first current mirror and the D pole of the second current mirror, and a capacitor C0 and a source follower connected to the second current mirror arranged in parallel; the S pole of the first MOS tube M0 is connected with the collector of the transistor Q0; the capacitor C0 is connected with the positive electrode of the Zener diode D0; and the two ends of the source follower are respectively connected with the first resistor R0 and the positive electrode of the Zener diode D0. The Zener diode D0 can be replaced by a diode-connected MOS tube string or a BJT tube string. The first MOS tube M0 is a depletion-type MOS tube.

[0036] The first current mirror includes a second resistor R1, a third MOS tube M1 and a fourth MOS tube M2; one end of the second resistor R1 is connected to the emitter of the triode Q0 and the G pole of the second MOS tube M3, and the other end of the second resistor R1 is connected to the G pole and the D pole of the third MOS tube M1 and the G pole of the fourth MOS tube M2; the S pole of the third MOS tube M1 is connected to the S pole of the fourth MOS tube M2, the anode of the Zener diode D0, the second current mirror, the capacitor C0 and the source follower; the S pole of the fourth MOS tube M2 is connected to the S pole of the third MOS tube M1, the anode of the Zener diode D0, the second current mirror, the capacitor C0 and the source follower, and the D pole of the fourth MOS tube M2 is connected to the second current mirror.

[0037] The second current mirror includes a third resistor R2, a fifth MOS tube M4 and a sixth MOS tube M5; one end of the third resistor R2 is connected to the positive electrode of the Zener diode D0, the first current mirror, the capacitor C0 and the source follower, and the other end of the third resistor R2 is connected to the D electrode of the sixth MOS tube M5, the capacitor C0 and the source follower; the D electrode of the fifth MOS tube M4 is connected to the D electrode of the second MOS tube M3 and the G electrode of the sixth MOS tube M5, the G electrode of the fifth MOS tube M4 is connected to the G electrode of the sixth MOS tube M5, the S electrode of the fifth MOS tube M4 is connected to the S electrode of the sixth MOS tube M5, the D electrode of the first MOS tube M0, the first resistor R0 and the source follower; the S electrode of the sixth MOS tube M5 is connected to the S electrode of the fifth MOS tube M4, the D electrode of the first MOS tube M0, the first resistor R0 and the source follower.

[0038] The source follower includes a seventh MOS tube M6 and a current source I0, a G pole of the seventh MOS tube M6 is connected to the second current mirror and the capacitor C0, a D pole of the seventh MOS tube M6 is connected to the second current mirror, the D pole of the first MOS tube M0 and the first resistor R0, and an S pole of the seventh MOS tube M6 is connected to the input end of the current source I0; an output end of the current source I0 is connected to the positive pole of the Zener diode D0, the first current mirror, the second current mirror and the capacitor C0; the seventh MOS tube M6 is a depletion type MOS tube.

[0039] In the present embodiment, during use, the first resistor R0 and the Zener diode D0 are connected in series to generate a voltage V ZN .

[0040] At this time, the voltage drop across the second resistor R1 is:

[0041] V R1 =V ZN -V BE0 -V GS1 (7)

[0042] V R1 About 4V.

[0043] The current flowing through the second resistor R1 is:

[0044]

[0045] The third MOS tube M1 and the fourth MOS tube M2 in the first current mirror replicate the current in equal proportion. At the same time, the fifth MOS tube M4 and the sixth MOS tube M5 in the second current mirror replicate the current at a ratio of 1:2.5. The replicated current finally flows through the third resistor R2 (R2=R1), thereby amplifying the 4V voltage on the second resistor R1 by 2.5 times and placing it on the third resistor R2, so that the voltage drop of the third resistor R2 is about 10V.

[0046] When V IN >10V, the Y node voltage is stable at about 10V. The Y node voltage controls the gate of the seventh MOS tube M6 (depletion type MOS tube, the threshold voltage is negative). Since the seventh MOS tube M6 and the current source I0 form a source follower, the seventh MOS tube M6 is turned on to achieve V OUT =V Y -V TH6 (V TH6 represents the threshold voltage of M6).

[0047] When V IN <10V, the sixth MOS tube M5 enters the linear region and limits the voltage drop on the third resistor R2 to less than 10V. At this time, the voltage at point Y is approximately equal to V IN , rather than being fixed at 10V as before. Since the voltage at point Y controls the gate of the seventh MOS tube M6, and the threshold voltage of the seventh MOS tube M6 is negative (depletion type MOS tube), the seventh MOS tube M6 is turned on, and V OUT With V IN short-circuit, achieving V OUT =VI N function.

[0048] In order to avoid the breakdown of transistor Q0, the collector of transistor Q0 cannot be directly connected to the power supply voltage V IN , and the first MOS tube M0 (high-voltage MOS tube) is required for isolation. The first MOS tube M0 uses a depletion-type transistor (the source potential is greater than the gate potential), thereby ensuring that the collector potential of the transistor Q0 is greater than the base potential, ensuring the normal working state of the transistor Q0. In addition, in order to avoid the breakdown of the fourth MOS tube M2, the drain of the fourth MOS tube M2 cannot be directly connected to the gate / drain of the fifth MOS tube M4 (the gate / drain of M4 is closer to the power supply voltage V IN ), and a second MOS tube M3 (high-voltage MOS tube) is needed for isolation.

[0049] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A voltage pre-regulation circuit, characterized in that: The invention comprises a first resistor (R0), a Zener diode (D0) connected in series with the first resistor (R0), a first MOS tube (M0) whose G pole is connected to the negative pole of the Zener diode (D0), a transistor (Q0) whose base is connected to the negative pole of the Zener diode (D0), a first current mirror connected to the positive pole of the Zener diode (D0) and the emitter of the transistor (Q0), a second current mirror connected to the first resistor (R0) and the D pole of the first MOS tube (M0), a second MOS tube (M3) whose G pole and S pole are connected to the first current mirror and whose D pole is connected to the second current mirror, and a capacitor (C0) and a source follower connected to the second current mirror and arranged in parallel; The S pole of the first MOS tube (M0) is connected to the collector of the triode (Q0); the capacitor (C0) is connected to the positive pole of the Zener diode (D0); the two ends of the source follower are respectively connected to the first resistor (R0) and the positive pole of the Zener diode (D0); the first current mirror comprises a second resistor (R1), a third MOS tube (M1) and a fourth MOS tube (M2); one end of the second resistor (R1) is connected to the emitter of the triode (Q0) and the G pole of the second MOS tube (M3), and the other end of the second resistor (R1) is connected to the G pole and D pole of the third MOS tube (M1) and the G pole of the fourth MOS tube (M2); The S pole of the third MOS tube (M1) is connected to the S pole of the fourth MOS tube (M2), the positive pole of the Zener diode (D0), the second current mirror, the capacitor (C0) and the source follower; the S pole of the fourth MOS tube (M2) is connected to the S pole of the third MOS tube (M1), the positive pole of the Zener diode (D0), the second current mirror, the capacitor (C0) and the source follower, and the D pole of the fourth MOS tube (M2) is connected to the second current mirror; the second current mirror comprises a third resistor (R2), a fifth MOS tube (M4) and a sixth MOS tube (M5); one end of the third resistor (R2) is connected to the Zener diode (D0) ), the first current mirror, the capacitor (C0) and the source follower are connected; the other end of the third resistor (R2) is connected to the D pole of the sixth MOS tube (M5), the capacitor (C0) and the source follower; the D pole of the fifth MOS tube (M4) is connected to the D pole of the second MOS tube (M3) and the G pole of the sixth MOS tube (M5); the G pole of the fifth MOS tube (M4) is connected to the G pole of the sixth MOS tube (M5); the S pole of the fifth MOS tube (M4) is connected to the S pole of the sixth MOS tube (M5), the D pole of the first MOS tube (M0), the first resistor (R0) and the source follower;The S pole of the sixth MOS tube (M5) is connected to the S pole of the fifth MOS tube (M4), the D pole of the first MOS tube (M0), the first resistor (R0) and the source follower; the source follower comprises a seventh MOS tube (M6) and a current source (I0); the G pole of the seventh MOS tube (M6) is connected to the second current mirror and the capacitor (C0); the D pole of the seventh MOS tube (M6) is connected to the second current mirror, the D pole of the first MOS tube (M0) and the first resistor (R0); the S pole of the seventh MOS tube (M6) is connected to the input end of the current source (I0); the output end of the current source (I0) is connected to the positive pole of the Zener diode (D0), the first current mirror, the second current mirror and the capacitor (C0). ; 2. A voltage pre-regulation circuit according to claim 1, characterized in that: The Zener diode (D0) may be replaced by a diode-connected MOS tube string or a BJT tube string.

3. The voltage pre-regulation circuit according to claim 1, characterized in that: The first MOS transistor (M0) is a depletion type MOS transistor.

4. The voltage pre-regulation circuit according to claim 1, characterized in that: The seventh MOS transistor (M6) is a depletion type MOS transistor.

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