An LDO circuit based on PN complementary current-compensated power supply ripple feedforward

Abstract

This invention designs an LDO circuit based on PN complementary current-compensated power supply ripple feedforward, mainly consisting of a reference bias circuit, an error amplifier, a feedforward ripple circuit, an overshoot compensation circuit, and a power output stage composed of a power transistor and a voltage divider sampling circuit. The reference bias circuit connects to the error amplifier, feedforward ripple circuit, and overshoot compensation circuit, providing a bias voltage. The error amplifier compares the feedback voltage with the reference voltage and transmits the comparison result to the gate of the power transistor, adjusting its gate voltage change, thus adjusting the output voltage connected to the drain of the power transistor. The feedforward ripple circuit connects to the gate of the power transistor and the output voltage, adjusting the overshoot (undershoot) state of the output voltage, stabilizing the output, and enhancing transient response. The overshoot compensation circuit connects to the output voltage, regulating the overshoot state of the output voltage, stabilizing the output, and enhancing transient response. This invention has good power supply voltage rejection ratio and excellent stability.

Description

Technical Field

[0001] This invention designs a low-voltage linear regulator (LDO) and proposes a feedforward ripple circuit structure. This structure has three functions: improving the transient response of the low-voltage linear regulator, improving the power supply voltage rejection ratio to a certain extent, and improving the stability of the entire circuit module. It also serves as a power supply for other circuit modules, belonging to the technical field of integrated circuit power management modules. Background Technology

[0002] Low-dropout linear regulators (LDOs) are widely used in power management modules of very large-scale integrated circuits due to their small chip area, high power supply voltage rejection ratio, and fast time-domain response. This invention designs an LDO architecture with high power supply voltage rejection ratio and high-speed transient response.

[0003] For LDOs, suppressing power supply ripple, isolating power supply noise, and rapidly adjusting to different current loads are crucial. Common methods to improve the power supply rejection ratio (PSRR) of the circuit include: increasing loop gain, using a reference circuit with a high PSRR, cascading LDOs, and adding circuit structures that improve PSRR. For highly integrated LDOs without external capacitors, enhancing transient response can reduce transient response time by increasing loop bandwidth and increasing the switching current at the gate node of the power transistor.

[0004] This invention reduces the impact of power supply ripple variations on the output voltage through a feedforward ripple circuit. When the power supply ripple is transmitted to the source of the power transistor, the feedforward ripple circuit also amplifies the voltage ripple at the gate of the power transistor. The two cancel each other out, thereby improving the power supply voltage rejection ratio. When the output voltage experiences overshoot (undershoot), the feedforward ripple circuit can quickly perform a dynamic adjustment, allowing the circuit's output voltage to rapidly return to a stable state. Summary of the Invention

[0005] The purpose of this invention is to design a PN complementary current-compensated power supply ripple feedforward LDO circuit as a power management module inside a mobile system chip, which has a faster transient response and a higher power supply voltage rejection ratio.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] An LDO circuit based on PN complementary current-compensated power supply ripple feedforward includes a reference bias circuit, an error amplifier, and a power output stage. Its key feature is that it further includes a feedforward ripple circuit and an overshoot compensation circuit; wherein the reference bias circuit is connected to the error amplifier, the feedforward ripple circuit, and the overshoot compensation circuit; the positive input terminal of the error amplifier is connected to the feedback voltage V obtained by voltage division by resistors R1 and R2 in the voltage divider sampling circuit. FB The inverting input terminal is connected to the reference voltage V. REF The output terminal is connected to the feedforward ripple circuit and the gate of the power transistor; the feedforward ripple circuit, overshoot compensation circuit, voltage divider sampling circuit, and the drain of the power transistor are connected to the output voltage V. OUT The source of the power transistor and the feedforward ripple circuit are connected to the power supply signal VDD; the feedforward ripple circuit, overshoot compensation circuit, and voltage divider sampling circuit are connected to the power supply signal GND.

[0008] The reference bias circuit provides a reference current independent of the power supply voltage to the circuit and provides a bias voltage to the rest of the circuit.

[0009] The error amplifier is implemented by a rail-to-rail complementary operational amplifier, which converts the feedback voltage V... FB and reference voltage V REF The comparison results are passed to the power output stage.

[0010] The feedforward ripple circuit consists of a PN complementary structure and a low-pass filter (LPF). When the output voltage V... out During fluctuations, the PN complementary structure can quickly adjust the current, stabilize the output, and enhance transient response; at the same time, it amplifies the gate voltage ripple of the power transistor to offset the ripple generated by the power supply voltage at the source of the power transistor, thereby improving the power supply voltage rejection ratio.

[0011] The overshoot compensation circuit uses a low-pass filter (LPF) to regulate the overshoot state of the output voltage.

[0012] The power output stage consists of power transistors and a voltage divider sampling circuit. The voltage divider sampling circuit, composed of resistors R1 and R2, samples the output voltage V. out A sampling set voltage divider is performed. The gate of the power transistor is controlled by the output of the error amplifier in the feedback loop, which quickly adjusts the output current to stabilize the output voltage V. out .

[0013] The voltage regulation process of the low-dropout linear regulator of the present invention specifically includes the following steps:

[0014] Step 1: The LDO supplies power to other circuit modules, providing a stable 1.8V power supply voltage and the required load current.

[0015] Step 2: When the load changes, the feedback circuit starts working, and the changing voltage is fed back to the error amplifier, which is compared with the reference voltage V. REF The comparison generates an error voltage value, which is then transmitted to the gate of the power transistor for adjustment.

[0016] Step 3: When the load current decreases, the output voltage V... out When the voltage increases and the circuit is in an overshoot state, both the overshoot compensation circuit and the feedforward ripple circuit operate simultaneously. In the overshoot compensation circuit, the output voltage V... out Connected M 37 The source voltage increases, but because the gate of the transistor is connected to the LPF, its gate voltage remains unchanged, resulting in an increase in the current flowing through it; this increases the M voltage. 40 The gate voltage is adjusted to change the transistor from the cutoff state to the on state, generating a current to ground, allowing the power transistor to discharge quickly and reducing the effect of overshoot. This plays a role in stabilizing the voltage. Simultaneously, the feedforward ripple circuit is related to the output voltage V. out The connected capacitor C4 is turned on, making M in the PN complementary structure... 27 The source generates a voltage, while its gate voltage is locked to VB3 by LPF3, thereby generating drain-source current. This causes the gate voltage of the power transistor to rise, the current flowing through the power transistor to decrease, and the output voltage to drop, thus stabilizing the voltage.

[0017] Step 4: When the load current increases, it causes the output voltage V to... out When the voltage is reduced to an undervoltage state, only the feedforward ripple circuit is active. The feedforward ripple circuit is related to the output voltage V. out The connected capacitor C2 is turned on, making M in the PN complementary structure... 26 The source generates a voltage, while its gate voltage is locked to the bias voltage VB2 by LPF2, thereby generating drain-source current. This causes the gate voltage of the power transistor to decrease, the current flowing through the power transistor to increase, and the output voltage to rise, thus stabilizing the voltage.

[0018] Step 5: At high frequencies, when the power supply voltage ripple affects the output of the power transistor, the feedforward ripple circuit is affected by M. 25 and M 26 The common gate configuration has a certain gain, which amplifies the voltage ripple of the power transistor's gate and cancels out the ripple generated by the power supply voltage at its source, thereby improving the power supply voltage rejection ratio of the circuit at high frequencies.

[0019] Compared with existing LDO structures, the low-dropout linear regulator system designed in this invention has the following advantages:

[0020] 1. Employing a feedforward ripple circuit can improve circuit performance in several ways. First, this feedforward circuit enhances the power supply rejection ratio (PSRR) of the circuit structure. Under combined changes in process, power supply, and temperature (PVT), the minimum PSRR at low frequencies is -98.3dB, and at high frequencies it is -38.9dB, demonstrating relatively good power supply ripple suppression performance. Second, it enhances circuit stability. Under combined changes in process, power supply, and temperature (PVT), the minimum phase margin of the circuit is 74.35°; generally, the phase margin is above 90°, resulting in excellent overall circuit stability. Finally, this feedforward circuit enhances the transient response of the LDO circuit, reducing the time for the output voltage to return to a stable voltage to within 100ns.

[0021] 2. The reference bias circuit provides a suitable bias voltage for the error amplifier, feedforward ripple circuit, and overshoot compensation circuit in the LDO circuit, resulting in relatively low static power consumption; simultaneously, resistors R5 and R with different temperature coefficients are used in the reference bias circuit. 11 This ensures that the output current changes very little with temperature, thus minimizing the temperature drift of the entire circuit within a temperature range of -40℃ to 125℃. Attached Figure Description

[0022] Figure 1 This invention proposes an LDO system architecture.

[0023] Figure 2 The feedforward ripple circuit diagram proposed in this invention

[0024] Figure 3 Overshoot compensation circuit in this invention

[0025] Figure 4 This is the circuit diagram of the LDO system proposed in this invention.

[0026] Figure 5 The static current of the LDO proposed in this invention under load currents of 0A and 20mA is...

[0027] Figure 6 This is a transient simulation diagram of overshoot and undershoot under the standard LDO condition proposed in this invention.

[0028] Figure 7 Gain and amplitude-frequency curves of LDO with and without feedforward ripple circuit at load currents of 0A and 20mA.

[0029] Figure 8Power supply voltage rejection ratio curves of LDO with and without feedforward ripple circuit at load currents of 0A and 20mA. Detailed Implementation

[0030] The following describes in detail, with reference to embodiments and accompanying drawings, the various circuit modules and simulation test results of the LDO circuit design based on PN complementary current compensation power supply ripple feedforward according to the present invention.

[0031] Example 1

[0032] This invention is presented by combining the actual design and test results of an LDO circuit based on the TSMC 180nm process library. The overall structure of the LDO includes a reference bias circuit, an error amplifier, a feedforward ripple circuit, an overshoot compensation circuit, and a power output stage. Using the TSMC 180nm process, the input voltage is 3.2–5V, the output voltage is 1.8V, the load capacitance is 100pF, and it can output a load current of 0–20mA. The LDO area is approximately 0.087mm². 2 Its territory is relatively small.

[0033] The overall LDO system architecture and circuit diagram are as follows: Figure 1 and Figure 4 As shown.

[0034] I. Connection Method

[0035] exist Figure 1 In the LDO system architecture diagram shown, the input power signals of the LDO system are VDD and GND, and the output voltage is V. OUT The reference bias circuit is connected to the error amplifier, the feedforward ripple circuit, and the overshoot compensation circuit. The inverting input of the error amplifier is connected to the reference voltage V. REF The feedback voltage V of the circuit connected to the positive input terminal FB The feedforward ripple circuit connects the output of the error amplifier to the gate of the power transistor. The output voltage V... OUT It is connected to the feedforward ripple circuit, overshoot compensation circuit, drain of the power transistor, and voltage divider sampling circuit composed of R1 and R2. The connection point of resistors R1 and R2 is connected to the circuit feedback voltage V. FB The power transistor and the voltage divider sampling circuit form the power output stage. The power supply signal VDD is connected to the source of the power transistor and the feedforward ripple circuit; the power supply signal GND is connected to resistor R2, the feedforward ripple circuit, and the overshoot compensation circuit.

[0036] exist Figure 2 In the feedforward ripple circuit shown, the input power signals are VDD and GND, and the output voltage is V. OUT M 25 and M 26 For PMOS transistors, M 27and M 28 These are NMOS transistors, which together form a PN complementary structure; M 25 The drain and M 26 The source of M is connected to one end of capacitor C2. 27 The source and M 28 The drain of capacitor C2 is connected to one end of capacitor C4, and the other ends of capacitors C2 and C4 are connected to the output voltage V. OUT M 25 The gate connection is composed of resistor R7 and capacitor C5, which forms LPF1, M. 26 The gate connection is composed of resistor R8 and capacitor C6, forming LPF2, M. 27 The gate connection is composed of resistors R9 and C7, forming LPF3, M. 28 The gate connection is made of resistor R 10 LPF4 is composed of C8; LPF1, LPF2, LPF3, and LPF4 are respectively connected to the bias voltages VB1, VB2, VB3, and VB4 generated by the reference bias circuit; M 26 The drain and M 27 The drain of the power transistor is connected to the gate; M 25 The source is connected to the power supply signal VDD, M 28 The source of the capacitor and one end of capacitors C5, C6, C7 and C8 are connected to the power supply signal GND.

[0037] exist Figure 3 In the overshoot compensation circuit shown, the input power supply signal is GND, and the output voltage is V. OUT M 36 The source, M 37 The source and M 40 The drain connection output voltage V OUT M 36 The gate and drain are shorted and connected to the LPF and M formed by R6 and C9. 38 The drain connection, M 37 The gate is connected to LPF, M 37 The drain and M 39 The drain and M 40 Gate connection; M 38 The gate and M 39 The gate is connected to the bias voltage VB4 generated by the reference bias circuit; M 38 The source, M 39 The source, M 40 The source of C9 and one end of C9 are connected to the power supply signal GND.

[0038] exist Figure 4The LDO system circuit diagram shown consists of a reference bias circuit, an error amplifier, a feedforward ripple circuit, an overshoot compensation circuit, and a power output stage. The input power supply signals of the LDO system circuit are VDD and GND, and the input reference voltage is VDD. REF This indicates that the output signal is determined by V. OUT This is indicated. Table 1 summarizes... Figure 4 Table 2 summarizes the abbreviations for all transistors and their meanings, while Table 3 summarizes the abbreviations for all resistors and capacitors. Due to the large number of transistors, resistors, and capacitors involved, abbreviations will be used throughout this document.

[0039] exist Figure 4 In the middle, M1, M2, M3, M4, M7, M8, M9, M 13 M 14 M 15 M 16 M 21 M 24 M 25 M 26 M 29 M 34 M 35 M 36 M 37 M 41 M P These are PMOS transistors; M5, M6, M 10 M 11 M 12 M 17 M 18 M 19 M 20 M 22 M 23 M 27 M 28 M 30 M 31 M 32 M 33 M 38 M 39 M 40 M 42 These are NMOS transistors. M1, M2, M9, and M... 13 M 14 M 21 M 24 M 25 M 29 M 34 M P The source is connected to VDD; M5, M 12 M 19 M 20 M22 M 23 M 28 M 32 M 33 M 38 M 39 M 40 The source of each PMOS is connected to GND. The substrate of all PMOS is connected to VDD, and the substrate of all NMOS is connected to GND.

[0040] The drain and gate of M1 are shorted and connected to the gate of M2, the source of M3, and M... 29 The gates of M2 and M4 are connected. The drain of M2 is connected to the source of M4; the gate and drain of M4 are shorted and connected to the gate of M3 and the drain of M6; the gate and drain of M5 are shorted and connected to the drain of M3 and the gate of M6; one end of R5 is connected to the source of M6, and the other end is connected to R 11 One end, R 11 The other end is connected to GND. The gate of M9 is connected to VB1, and the drain of M9 is connected to the source of M7, the source of M8, and M... 41 The source and drain are connected; M 41 The gate of M7 is connected to the power supply VDD; the gate of M7 and M... 10 The gates of all are with V FB Connected; the gate of M8 and M 11 The gates of all are with V REF Connected; M 12 The gate is connected to VB4, M 12 The drains are respectively connected to M 10 The source, M 11 The source, M 42 The source and drain are connected; M 42 The gate is connected to GND. M 13 The gate and M 14 gate, M 15 Drain, M 17 The drain and M 24 The gate is connected; M 13 The drain and M 15 The source and M 10 The drains are connected; M 14 The drain and M 16 The source and M 11 The drains are connected; M 15 The gate and M 16 The gates of all M are connected to VB2; 16 The drain and M 18 The drain and M 21 The gate is connected; M 17 The gate and M 18 The gates of all M are connected to VB3; 17The source and M 19 The drain of M1 is connected to the drain of M7; M 18 The source and drain of M8 and M 20 The drains are connected; M 19 The gate and M 20 The gates of all are connected to VB4. M 22 The gate and drain are shorted and connected to M. 23 gate, M 21 The drains are connected; M 23 The drain and M 24 The drains are connected. M 30 gate, M 31 gate, M 29 The drain of R3 and one end of R3 are both connected to VB3; the other end of R3 is connected to M. 31 Drain, M 32 The gate and M 33 The gates of all M are connected to VB4; 31 The source and M 32 The drains are connected; M 30 The source and M 33 The drains are connected; M 34 The drain and M 35 Source connection; M 34 gate, M 35 The drain of R4 and one end of R4 are both connected to VB1; the other end of R4 and M 30 The drain and M 35 The gates of all are connected to VB2.

[0041] M 25 The gate is connected to one end of resistor R7 and one end of capacitor C5, the other end of R7 is connected to VB1, and the other end of C5 is connected to GND. 26 The gate is connected to one end of resistor R8 and one end of capacitor C6, the other end of R8 is connected to VB2, and the other end of C6 is connected to GND. 27 The gate is connected to one end of resistor R9 and one end of capacitor C7, the other end of R9 is connected to VB3, and the other end of C7 is connected to GND. 28 Gate and resistor R 10 One end is connected to one end of capacitor C8, R 10 The other end of C8 is connected to VB4, and the other end of C8 is connected to GND. 36 The gate and drain are shorted and connected to M. 38 The drain of the resistor is connected to one end of resistor R6; the other end of R6 is connected to M. 37 The gate of the capacitor is connected to one end of capacitor C9; the other end of capacitor C9 is connected to GND; M 37 The source and V OUT Connected; M 38The gate and M 39 The gates of all M are connected to VB4; 37 The drain and M 39 The drain and M 40 The gate is connected. M 40 Drain, M 36 The source, M P The drains are all connected to V OUT One end of C1 is connected to M 13 The gate of C1 is connected to V, and the other end of C1 is connected to V. OUT M 25 The drain and M 26 The source of the capacitor is connected to one end of capacitor C2, and the other end of C2 is connected to V. OUT M 26 The drain and M 27 Drain, M P gate, M 24 The drain of the capacitor is connected to one end of capacitor C3, and the other end of C3 is connected to V. OUT M 27 The source and M 28 The drain of capacitor C4 is connected to one end of capacitor C4, and the other end of capacitor C4 is connected to V. OUT One end of resistor R1 is connected to V. OUT The other end of R1 is connected to V FB Connect one end of R2; connect the other end of R2 to GND.

[0042] II. Engineering Design

[0043] Based on the TSMC 180nm process library, a device with an input voltage range of 3.2V to 5V, an output voltage of 1.8V, and a load current range of 0A to 20mA was designed. Tables 1, 2, and 3 summarize the design parameters of all devices.

[0044] III. Test Results

[0045] Depend on Figure 5 This demonstrates the quiescent current consumption of the LDO as a function of temperature at load currents of 0A and 20mA. Under standard conditions (tt, 4.2V, 40℃), the quiescent current consumption is 38.18uA at a load current of 0A. The maximum quiescent current is 67.9uA under different process angles (tt, ss, ff) and different temperatures (-40℃ to 125℃).

[0046] Depend on Figure 6As shown, under standard process angle conditions (i.e., tt process angle), the output voltage reaches 1.8V (±5%) when the load current increases, with a post-simulation time of 61ns; when the load current decreases, the output voltage reaches 1.8V (±5%), with a post-simulation time of 49ns. Overall, the time-domain performance is superior. The worst-case supply voltage regulation under standard conditions is 1.339uV / V in the post-simulation. The worst-case load regulation under standard conditions is -0.638%.

[0047] Figure 7 The diagram illustrates the amplitude-frequency angle of the LDO circuit proposed in this invention under two conditions: with and without a feedforward ripple circuit, and with load currents of 0A and 20mA, respectively, at a gain of 0dB. It can be seen that without the feedforward ripple circuit, when the load current is 0A, the amplitude-frequency angle is approximately 0°, indicating no phase margin and resulting in circuit instability; when the load current is 20mA, the amplitude-frequency angle is 153°, and the circuit output already oscillates. With the feedforward ripple circuit, when the load current is 0A and 20mA, the amplitude-frequency angles are 93° and 98° respectively, indicating a phase margin of over 90° and overall circuit stability.

[0048] exist Figure 8 The paper demonstrates the power supply voltage rejection ratio (PSRR) of the LDO circuit proposed in this invention at high and low frequencies, with and without a feedforward ripple circuit, and with load currents of 0A and 20mA, respectively. It shows that without the feedforward ripple circuit, the worst PSRR is 7.7dB at a load current of 0A; while with the feedforward ripple circuit, the worst PSRR is -5.5dB at a load current of 0A. At high frequencies, the PSRR is close to -41dB in both cases with and without the feedforward ripple circuit.

[0049] Table 4 provides a comprehensive summary of the technical specifications of the present invention before and after its development, covering the performance parameters of each specification under different temperatures, different power supply voltages, and different process angles. It also indicates the process angle under which the performance specifications are worst.

[0050] Table 1 Summary of Transistor Design Parameters

[0051]

[0052]

[0053] Table 2 Resistor Design Parameters

[0054] W(μm) L(μm) Fingers Multiplier Resistance value (KΩ) <![CDATA[R1]]> 0.42 10 1 1 100.232 <![CDATA[R2]]> 0.42 10 2 1 200.465 <![CDATA[R3]]> 2 20 15 1 150.463 <![CDATA[R4]]> 2 20 15 1 150.463 <![CDATA[R5]]> 0.43 20 23 1 8.212 <![CDATA[R6]]> 0.42 10 6 1 601.395 <![CDATA[R7]]> 0.42 10 20 1 2004.65 <![CDATA[R8]]> 0.42 10 20 1 2004.65 <![CDATA[R9]]> 0.42 10 20 1 2004.65 <![CDATA[R 10 ]]> 0.42 10 20 1 2004.65 <![CDATA[R 11 ]]> 2 2 3 1 3.475

[0055] Table 3 Capacitor Design Parameters

[0056]

[0057]

[0058] Table 4 Circuit Before and After Simulation Design Specifications

[0059]

Claims

1. An LDO circuit based on PN complementary current-compensated power supply ripple feedforward, comprising a reference bias circuit, an error amplifier, and a power output stage, wherein the reference bias circuit is connected to the error amplifier, the feedforward ripple circuit, and the overshoot compensation circuit; the positive input terminal of the error amplifier is connected to the feedback voltage V obtained by voltage division by resistors R1 and R2 in the voltage divider sampling circuit. FB The inverting input terminal is connected to the reference voltage V. REF The output terminal is connected to the feedforward ripple circuit and the gate of the power transistor; the feedforward ripple circuit, overshoot compensation circuit, voltage divider sampling circuit, and the drain of the power transistor are connected to the output voltage V. OUT The source of the power transistor and the feedforward ripple circuit are connected to the power supply signal VDD; the feedforward ripple circuit, overshoot compensation circuit, and voltage divider sampling circuit are connected to the power supply signal GND. Its features are: In a feedforward ripple circuit, the input power signals are VDD and GND, and the output voltage is V. OUT M 25 and M 26 For PMOS transistors, M 27 and M 28 These are NMOS transistors, which together form a PN complementary structure; M 25 The drain and M 26 The source of M is connected to one end of capacitor C2. 27 The source and M 28 The drain of capacitor C2 is connected to one end of capacitor C4, and the other ends of capacitors C2 and C4 are connected to the output voltage V. OUT M 25 The gate connection is composed of resistor R7 and capacitor C5, which forms LPF1, M. 26 The gate connection is composed of resistor R8 and capacitor C6, forming LPF2, M. 27 The gate connection is composed of resistors R9 and C7, forming LPF3, M. 28 The gate connection is made of resistor R 10 LPF4 is composed of C8; LPF1, LPF2, LPF3, and LPF4 are respectively connected to the bias voltages VB1, VB2, VB3, and VB4 generated by the reference bias circuit; M 26 The drain and M 27 The drain of the power transistor is connected to the gate; M 25 The source is connected to the power supply signal VDD, M 28 The source of the capacitor and one end of capacitors C5, C6, C7 and C8 are connected to the power supply signal GND.

2. The LDO circuit based on PN complementary current compensation power supply ripple feedforward according to claim 1, characterized in that: In the overshoot compensation circuit, the input power signal is GND, and the output voltage is V. OUT M 36 The source, M 37 The source and M 40 The drain connection output voltage V OUT M 36 The gate and drain are shorted and connected to the LPF and M formed by R6 and C9. 38 The drain connection, M 37 The gate is connected to LPF, M 37 The drain and M 39 The drain and M 40 Gate connection; M 38 and M 39 The gate is connected to the bias voltage VB4 generated by the reference bias circuit; M 38 The source, M 39 The source, M 40 The source of C9 and one end of C9 are connected to the power supply signal GND.

3. The LDO circuit based on PN complementary current compensation power supply ripple feedforward according to claim 1, characterized in that: M1, M2, M3, M4, M7, M8, M9, M 13 M 14 M 15 M 16 M 21 M 24 M 25 M 26 M 29 M 34 M 35 M 36 M 37 M 41 M P These are PMOS transistors; M5, M6, M 10 M 11 M 12 M 17 M 18 M 19 M 20 M 22 M 23 M 27 M 28 M 30 M 31 M 32 M 33 M 38 M 39 M 40 M 42 These are NMOS transistors; where M1, M2, M9, and M... 13 M 14 M 21 M 24 M 25 M 29 M 34 M P The source is connected to VDD; M5, M 12 M 19 M 20 M 22 M 23 M 28 M 32 M 33 M 38 M 39 M 40 The source of each PMOS is connected to GND; the substrate of all PMOS is connected to VDD, and the substrate of all NMOS is connected to GND. The drain and gate of M1 are shorted and connected to the gate of M2, the source of M3, and M... 29 The gates of M2 and M4 are connected; the drain of M2 is connected to the source of M4; the gate and drain of M4 are shorted and connected to the gate of M3 and the drain of M6; the gate and drain of M5 are shorted and connected to the drain of M3 and the gate of M6; one end of R5 is connected to the source of M6, and the other end is connected to R 11 One end, R 11 The other end is connected to GND; the gate of M9 is connected to VB1, and the drain of M9 is connected to the source of M7, the source of M8, and M... 41 The source and drain are connected; M 41 The gate of M7 is connected to the power supply VDD; the gate of M7 and M... 10 The gates of all are with V FB Connected; the gate of M8 and M 11 The gates of all are with V REF Connected; M 12 The gate is connected to VB4, M 12 The drains are respectively connected to M 10 The source, M 11 The source, M 42 The source and drain are connected; M 42 The gate is connected to GND; M 13 The gate and M 14 gate, M 15 Drain, M 17 The drain and M 24 The gate is connected; M 13 The drain and M 15 The source and M 10 The drains are connected; M 14 The drain and M 16 The source and M 11 The drains are connected; M 15 The gate and M 16 The gates of all M are connected to VB2; 16 The drain and M 18 The drain and M 21 The gate is connected; M 17 The gate and M 18 The gates of all M are connected to VB3; 17 The source and M 19 The drain of M1 is connected to the drain of M7; M 18 The source and drain of M8 and M 20 The drains are connected; M 19 The gate and M 20 The gates of all M are connected to VB4; 22 The gate and drain are shorted and connected to M. 23 gate, M 21 The drains are connected; M 23 The drain and M 24 The drains are connected; M 30 gate, M 31 gate, M 29 The drain of R3 and one end of R3 are both connected to VB3; the other end of R3 is connected to M. 31 Drain, M 32 The gate and M 33 The gates of all M are connected to VB4; 31 The source and M 32 The drains are connected; M 30 The source and M 33 The drains are connected; M 25 The gate is connected to one end of resistor R7 and one end of capacitor C5, the other end of R7 is connected to VB1, and the other end of C5 is connected to GND; M 26 The gate is connected to one end of resistor R8 and one end of capacitor C6, the other end of R8 is connected to VB2, and the other end of C6 is connected to GND; M 27 The gate is connected to one end of resistor R9 and one end of capacitor C7, the other end of R9 is connected to VB3, and the other end of C7 is connected to GND; M 28 Gate and resistor R 10 One end is connected to one end of capacitor C8, R 10 The other end is connected to VB4, and the other end of C8 is connected to GND; M 36 The gate and drain are shorted and connected to M. 38 The drain is connected to one end of resistor R6; The other end of R6 is connected to M 37 The gate of capacitor C9 is connected to one end of capacitor C9; the other end of capacitor C9 is connected to GND. M 37 The source and V OUT Connected; M 38 The gate and M 39 The gates of all M are connected to VB4; 37 The drain and M 39 The drain and M 40 The gate is connected; M 40 Drain, M 36 The source, M P The drains are all connected to V OUT One end of C1 is connected to M 13 The gate of C1 is connected to V, and the other end of C1 is connected to V. OUT M 25 The drain and M 26 The source of the capacitor is connected to one end of capacitor C2, and the other end of C2 is connected to V. OUT M 26 The drain and M 27 Drain, M P gate, M 24 The drain of the capacitor is connected to one end of capacitor C3, and the other end of C3 is connected to V. OUT M 27 The source and M 28 The drain of capacitor C4 is connected to one end of capacitor C4, and the other end of capacitor C4 is connected to V. OUT One end of resistor R1 is connected to V. OUT The other end of R1 is connected to V FB Connect one end of R2; connect the other end of R2 to GND.

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