Current mirror circuits, chips and electronic devices

Abstract

Embodiments of this disclosure provide a current mirror circuit, chip, and electronic device. The current mirror circuit includes: a reference current generating circuit, an input stage transistor circuit, and an output stage transistor circuit. The input stage transistor circuit and the output stage transistor circuit form a common-source, common-gate current mirror structure. The reference current generating circuit is configured to generate a reference current. The input stage transistor circuit is configured to adjust the equivalent transconductance of the input stage according to changes in the reference current, thereby adjusting the mirror ratio. The output stage transistor circuit is configured to output different output currents according to different mirror ratios. This solves the problems of inconvenient operation and large circuit area in existing current mirror circuits when the current mirror circuit is fixed and a variable output current is required.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to current mirror circuits, chips, and electronic devices. Background Technology

[0002] Current mirrors are widely used in the design of various analog circuits. Their characteristic is that the output current is a proportional "copy" of the input current, used to provide multiple constant currents. Typically, when the current mirror circuit is defined, the ratio of the output current to the input current is fixed; that is, the mirror current ratio is fixed. Therefore, if a variable output current is required, different circuits are needed. For example, for... Figure 1 In commonly used current mirror circuits, the mirror ratio corresponds to the width-to-length ratio of Mn1 and Mn2. If the width-to-length ratio of Mn1 and Mn2 is 1:1, then the ratio of the input current Iref to the output current Io is also 1:1, i.e., Io = Iref, meaning the mirror ratio is 1. If the width-to-length ratio of Mn1 and Mn2 is 1:10, then the ratio of the input current Iref to the output current Io is also 1:10, i.e., Io = 10 * Iref, meaning the mirror ratio is 10. Figure 1 As seen in the current mirror circuit, changing the ratio of the mirrored current requires altering the aspect ratio of Mn1 and Mn2, necessitating circuit modifications, which is highly inconvenient. Furthermore, for current mirror circuits with large mirror ratios, an even larger aspect ratio is required, significantly increasing the circuit area.

[0003] In summary, existing current mirror circuits suffer from inconvenient operation and large circuit area when the current mirror circuit is fixed and a variable output current is required, and these problems urgently need to be solved. Summary of the Invention

[0004] The embodiments described herein provide a current mirror circuit, chip, and electronic device for providing a current mirror circuit with an adjustable mirror ratio.

[0005] According to a first aspect of this disclosure, a current mirror circuit is provided, comprising: a reference current generating circuit, an input stage transistor circuit, and an output stage transistor circuit, wherein the input stage transistor circuit and the output stage transistor circuit form a common-source, common-gate current mirror structure, wherein the reference current generating circuit is configured to generate a reference current; the input stage transistor circuit is configured to adjust the equivalent transconductance of the input stage according to the change of the reference current, thereby adjusting the mirror ratio; and the output stage transistor circuit is configured to output different output currents according to different mirror ratios.

[0006] Optionally, the input stage transistor circuit includes: a first transistor, a second transistor, a third transistor, and a resistor, wherein the first terminal of the first transistor is coupled to the control terminal of the first transistor, the first terminal of the third transistor, and the output terminal of the reference current generating circuit, and the second terminal of the first transistor is coupled to ground; the first terminal of the second transistor is coupled to the second terminal of the third transistor, and the second terminal of the second transistor is coupled to one end of the resistor; the control terminal of the second transistor is coupled to the first terminal of the third transistor and the input terminal of the output stage transistor circuit; the control terminal of the third transistor is coupled to a control voltage; and the other end of the resistor is coupled to ground.

[0007] Optionally, the output stage transistor circuit includes: a fourth transistor, wherein the first terminal of the fourth transistor outputs the output current, the second terminal of the fourth transistor is coupled to a ground terminal, and the control terminal of the fourth transistor serves as the input terminal of the output stage transistor circuit and is coupled to the input stage transistor circuit.

[0008] Optionally, the reference current generating circuit includes a current source, wherein one end of the current source is connected to the power supply voltage, and the other end of the current source is coupled to the input stage transistor circuit as the output terminal of the reference current generating circuit.

[0009] Optionally, the control voltage is greater than or equal to the sum of the gate-source voltage of the third transistor and the overdrive voltage of the second transistor.

[0010] Optionally, the aspect ratio of the second transistor is N times that of the first transistor, where N is greater than or equal to 80.

[0011] Optionally, the aspect ratio of the second transistor is equal to that of the fourth transistor.

[0012] Optionally, the first transistor, the second transistor, the third transistor, and the fourth transistor are N-type transistors.

[0013] According to a second aspect of this disclosure, a chip is provided, including a current mirror circuit according to any one of the first aspects.

[0014] According to a third aspect of this disclosure, an electronic device is provided, including the chip described in the second aspect.

[0015] The current mirror circuit, chip, and electronic device disclosed in this disclosure include a reference current generation circuit, an input stage transistor circuit, and an output stage transistor circuit. The input stage transistor circuit and the output stage transistor circuit form a common-source, common-gate current mirror structure. The reference current generation circuit is configured to generate a reference current. The input stage transistor circuit is configured to adjust the equivalent transconductance of the input stage according to changes in the reference current, thereby adjusting the mirror ratio. The output stage transistor circuit is configured to output different output currents according to different mirror ratios. As can be seen, in the current mirror circuit of this disclosure, the input stage transistor circuit can adjust the equivalent transconductance of the input stage according to changes in the reference current. Given a fixed equivalent transconductance of the output stage, a change in the equivalent transconductance of the input stage is equivalent to changing the ratio of the equivalent transconductance of the input stage to the equivalent transconductance of the output stage. This change in the equivalent transconductance ratio changes the ratio of the output current to the input current, i.e., the mirror ratio changes. This results in a current mirror circuit with an adjustable mirror ratio, allowing for a variable output current to be obtained based on the adjustable mirror ratio without changing the circuit structure. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0017] Figure 1 This is an exemplary circuit diagram of an existing current mirror circuit;

[0018] Figure 2 This is a schematic block diagram of a current mirror circuit according to an embodiment of the present disclosure.

[0019] Figure 3 This is an exemplary circuit diagram of a current mirror circuit according to an embodiment of the present disclosure;

[0020] Figure 4 This is a schematic diagram of the ratio of the output current to the reference current Iref as a function of the reference current Iref, according to an embodiment of this disclosure.

[0021] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0024] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0025] To address the problems of inconvenient operation and large circuit area in existing current mirror circuits when the current mirror circuit is fixed and a variable output current is required, a novel current mirror circuit is proposed. The current mirror circuit of this disclosure allows the input stage transistor circuit to adjust the equivalent transconductance of the input stage according to changes in the reference current Iref, thereby obtaining a current mirror circuit with an adjustable mirror ratio. This allows a variable output current to be obtained based on the adjustable mirror ratio without changing the circuit structure. The current mirror circuit of this disclosure will be described in detail below.

[0026] like Figure 2 The diagram shown is a schematic block diagram of a current mirror circuit 100 according to an embodiment of this disclosure. It includes a reference current generation circuit 110, an input stage transistor circuit 120, and an output stage transistor circuit 130. The input stage transistor circuit 120 and the output stage transistor circuit 130 form a common-source, common-gate current mirror structure. Specifically, the common-source, common-gate current mirror structure refers to a structure where the transistors in the input stage transistor circuit 120 and the output stage transistor circuit 130 are common-source, common-gate structures. This common-source, common-gate structure is a commonly used structure in current mirror circuits.

[0027] Figure 2In the circuit, the reference current generating circuit 110 is configured to generate a reference current Iref. The reference current Iref is the input current in the current mirror circuit. There are no restrictions on the way the reference current Iref is generated, that is, there are no restrictions on the structure of the reference current generating circuit 110. For example, it can be a current source, or a combination of a voltage source and an impedance.

[0028] The input stage transistor circuit 120 is coupled to both the reference current generation circuit 110 and the output stage transistor circuit 130. The input stage transistor circuit 120 is composed of transistors. Specifically, the input stage transistor circuit 120 is configured to adjust the equivalent transconductance of the input stage according to changes in the reference current Iref, thereby adjusting the mirror ratio. The equivalent transconductance of the input stage is the equivalent transconductance corresponding to the branch containing the input current (reference current Iref) in the current mirror structure, which is also the equivalent transconductance of the input stage transistor circuit 120. Given a fixed equivalent transconductance of the output stage, adjusting the equivalent transconductance of the input stage is equivalent to changing the ratio of the equivalent transconductance of the input stage to that of the output stage. This change in the equivalent transconductance ratio changes the ratio of the output current I4 to the input current, thus changing the mirror ratio, resulting in a current mirror circuit with an adjustable mirror ratio.

[0029] The output stage transistor circuit 130 is configured to output different output currents I4 according to different mirror ratios. The ratio of the output current I4 to the input current (reference current Iref) is the mirror ratio, so a corresponding output current I4 can be output according to different mirror ratios. In practical applications, the output stage transistor circuit 130 can be a single output current branch or multiple output current branches connected in parallel, with each output current branch forming a common-source, common-gate current mirror structure with the input stage transistor circuit 120.

[0030] Based on the above description, in the current mirror circuit of this embodiment, the input stage transistor circuit 120 can adjust the equivalent transconductance of the input stage according to the change of the reference current Iref. Under the premise that the equivalent transconductance of the output stage is determined, the change of the equivalent transconductance of the input stage is equivalent to changing the ratio of the equivalent transconductance of the input stage to that of the output stage. When the ratio of the equivalent transconductance changes, the ratio of the output current I4 to the input current (reference current Iref) will change, that is, the mirror ratio will change, thereby obtaining a current mirror circuit with an adjustable mirror ratio.

[0031] Furthermore, such as Figure 3 As shown, this disclosure provides an exemplary circuit diagram of a current mirror circuit. Figure 3In the input stage transistor circuit 120, there are: a first transistor Mn1, a second transistor Mn2, a third transistor Mn3, and a resistor R. The first terminal of the first transistor Mn1 is coupled to the control terminal of the first transistor Mn1, the first terminal of the third transistor Mn3, and the output terminal of the reference current generating circuit 110. The second terminal of the first transistor Mn1 is coupled to ground. The first terminal of the second transistor Mn2 is coupled to the second terminal of the third transistor Mn3. The second terminal of the second transistor Mn2 is coupled to one end of the resistor R. The control terminal of the second transistor Mn2 is coupled to the first terminal of the third transistor Mn3 and the input terminal of the output stage transistor circuit 130. The control terminal of the third transistor Mn3 is coupled to a control voltage. The other end of the resistor R is coupled to ground. The control voltage is greater than or equal to the sum of the gate-source voltage of the third transistor Mn3 and the overdrive voltage of the second transistor Mn2. The aspect ratio of the second transistor Mn2 is N times that of the first transistor Mn1, where N is greater than or equal to 80. Setting N to be greater than or equal to 80 is to ensure that the equivalent transconductance of the second transistor Mn2 is significantly smaller than that of the second transistor Mn2. Of course, the value of N can be adjusted adaptively in practical applications. Furthermore, the first transistor Mn1, the second transistor Mn2, and the third transistor Mn3 are N-type transistors.

[0032] like Figure 3 As shown, the output stage transistor circuit 130 includes a fourth transistor Mn4, wherein the first terminal of the fourth transistor Mn4 outputs the output current I4, the second terminal of the fourth transistor Mn4 is coupled to ground, and the control terminal of the fourth transistor Mn4 serves as the input terminal of the output stage transistor circuit 130 and is coupled to the input stage transistor circuit 120. Furthermore, the fourth transistor Mn4 is an N-type transistor.

[0033] like Figure 3 As shown, the reference current generating circuit 110 includes a current source 111, wherein one end of the current source 111 is connected to the power supply voltage Vdd, and the other end of the current source 111 serves as the output terminal of the reference current generating circuit 110 and is coupled to the input stage transistor circuit 120.

[0034] Combination Figure 3 The circuit diagram in the present disclosure illustrates the working principle of the current mirror circuit 100 in this embodiment: Based on the change of the reference current Iref, the change of the mirror ratio can be divided into four intervals, and the principle of these four intervals is described below.

[0035] Interval 1: The product of the reference current Iref and the resistor R is much smaller than the gate-source voltage of the second transistor Mn2, i.e., Iref*R << Vgs2, and "much smaller" here can specifically be less than 50 times or more, i.e., Iref*R ≤ (Vgs2) / 50. Since Iref*R << Vgs2, the source negative feedback effect formed by the resistor R on the second transistor Mn2 can be ignored, and the equivalent transconductance Gm of the combination of Mn2 and R is approximately equal to gm2. Also, from the fact that the aspect ratio of the second transistor Mn2 is at least 80 times that of the first transistor Mn1, it can be known that gm1 << gm2. Therefore, gm1 << Gm, so almost all of the reference current Iref flows into Mn2. Also, because Iref*R << Vgs2, the voltage drop across the resistor R is much smaller than Vgs2, so the voltage at point A, Vgs2 ≈ VA = Vgs4. If the ratio of the aspect ratio of the second transistor Mn2 to the aspect ratio of the fourth transistor Mn4 is 1:a (a is greater than or equal to 1), then I2:I4 = 1:a. And because almost all of the reference current Iref flows into Mn2, so Iref ≈ I2. Therefore, Iref:I4 ≈ 1:a, and the mirror ratio I4 / Iref ≈ a:1. For example, usually when the aspect ratio of the second transistor Mn2 is equal to the aspect ratio of the fourth transistor Mn4, i.e., a = 1, I4 / Iref ≈ 1:1 can be obtained.

[0036] Interval 2, after Iref exceeds Interval 1, it gradually increases until Iref = (VB - Vgs3) / R. Taking Iref*R ≤ Vgs2 / 50 in Interval 1 as an example, Interval 2 can be expressed as Vgs2 / R*50 < Iref ≤ (VB - Vgs3) / R, where Vgs3 is the gate-source voltage of the third transistor Mn3. In this interval, as Iref gradually increases, the voltage drop across the resistor R continuously increases, and the source negative feedback effect formed by R on Mn2 gradually strengthens. Then the equivalent transconductance Gm of the combination of Mn2 and R is Gm = gm2 / (1 + gm2*R), that is, Gm < gm2. From the fact that the aspect ratio of the second transistor Mn2 is at least 80 times that of the first transistor Mn1, it can be known that gm1 << gm2. Although the equivalent transconductance Gm of the combination of Mn2 and R is less than gm2, the value of Gm is still much greater than gm1. Therefore, in this interval, Iref still remains in the state where almost all of it flows into Mn2. From the circuit connection relationship, although Mn4 still forms a mirror relationship with the combination of Mn2 + R, due to the source negative feedback effect of the resistor R, the equivalent transconductance Gm decreases compared to before (compared to Interval 1). Therefore, the mirror ratio of Mn4 to this combination increases on the basis of the previous a:1, that is, the mirror ratio I4 / Iref > a:1. For example, usually when the aspect ratio of the second transistor Mn2 is equal to the aspect ratio of the fourth transistor Mn4, i.e., a = 1, the mirror ratio I4 / Iref > 1 can be obtained.

[0037] Interval 3, Iref > (VB - Vgs3) / R. When Iref > (VB - Vgs3) / R, the drain-source voltage Vds of Mn2 is almost 0, and Mn2 operates in the linear region. Then the current I2 flowing through Mn2 is as shown in the following formula: I2 = (VB - Vgs3) / R. As Iref continues to increase, the current flowing through Mn2 will also remain the value of the above formula unchanged. At this time, the sum of I2 and the current I1 flowing through Mn1 is equal to Iref, that is, I1 = Iref - I2 = Iref - (VB - Vgs3) / R. Also, since Mn2 operates in the linear region at this time, the combination of Mn2 and R loses the current amplification effect. At this time, the current of Mn4 will mirror the current I1 flowing through Mn1. From the proportional relationship of the width-to-length ratios of Mn1 and Mn4, it can be known that I4 = a * N * I1 = a * N * [Iref - (VB - Vgs3) / R]. And because [Iref - (VB - Vgs3) / R] < Iref, so I4 < a * N * Iref, that is, I4 / Iref < a * N. For example, usually when the width-to-length ratio of the second transistor Mn2 is equal to the width-to-length ratio of the fourth transistor Mn4, that is, a = 1, the mirror ratio I4 / Iref < N can be obtained.

[0038] Interval 4, Iref >> (VB - Vgs3) / R, and the much greater here can be at least greater than 50 times. At this time, almost all of Iref flows through Mn1, then I1 = Iref. From the mirror relationship between Mn1 and Mn4 (that is, the proportional relationship of the width-to-length ratios of Mn1 and Mn4), it can be known that I4 = a * N * I1 = a * N * Iref, that is, I4 / Iref = a * N. For example, usually when the width-to-length ratio of the second transistor Mn2 is equal to the width-to-length ratio of the fourth transistor Mn4, that is, a = 1, the mirror ratio I4 / Iref = N can be obtained.

[0039] In summary, as the reference current Iref changes, this current mirror structure realizes the change effect of the current mirror ratio from a to a * N, where a is the ratio of the width-to-length ratio of Mn4 to Mn2, and N is the ratio of the width-to-length ratio of Mn2 to Mn1. From the description of the above working principle, it can be seen that compared with the existing current mirror circuit, the current mirror circuit of the present disclosure can adjust the mirror ratio in a large range without changing the circuit structure, the operation is more convenient, and it can also save the circuit area.

[0040] Further, in order to more intuitively represent the effect of the change of the current mirror ratio as the reference current Iref changes, Figure 4 the curve showing the ratio of the mirror current (output current I4) to the reference current Iref changing with the reference current Iref is shown, Figure 4 and the curve is a schematic diagram of the corresponding curve when a = 1 and N = 100. From Figure 4As can be seen: in interval 1, the mirror ratio is almost 1; in interval 2, the mirror ratio begins to rise, but the rate of increase is not fast; in interval 3, the mirror ratio begins to rise rapidly; in interval 4, the mirror ratio hardly rises anymore, and is almost 100.

[0041] Embodiments of this disclosure also provide a chip. This chip includes a current mirror circuit according to embodiments of this disclosure. This chip is, for example, a power management chip that requires adjustment of the mirror ratio.

[0042] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. The electronic device is, for example, a smart mobile terminal, a smart home device, or other smart device.

[0043] In summary, the current mirror circuit in this embodiment can obtain different mirror ratios according to the changes in the reference current, and thus can obtain a variable output current based on the adjustable mirror ratio without changing the circuit structure.

[0044] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0045] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0046] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0047] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A current mirror circuit, characterized in that, include: The system includes a reference current generation circuit, an input stage transistor circuit, and an output stage transistor circuit. The input stage transistor circuit and the output stage transistor circuit form a common-source, common-gate current mirror structure. The reference current generating circuit is configured to generate a reference current. The input stage transistor circuit is configured to adjust the equivalent transconductance of the input stage according to the change of the reference current, thereby adjusting the mirror ratio; The output stage transistor circuit is configured to output different output currents according to different mirror ratios; The output stage transistor circuit includes: a fourth transistor, wherein the first terminal of the fourth transistor outputs the output current, the second terminal of the fourth transistor is coupled to a ground terminal, and the control terminal of the fourth transistor serves as the input terminal of the output stage transistor circuit and is coupled to the input stage transistor circuit; The input stage transistor circuit includes: a first transistor, a second transistor, a third transistor, and a resistor. The first terminal of the first transistor is coupled to the control terminal of the first transistor, the first terminal of the third transistor, and the output terminal of the reference current generating circuit. The second terminal of the first transistor is coupled to ground. The first terminal of the second transistor is coupled to the second terminal of the third transistor and one end of the resistor. The control terminal of the second transistor is coupled to the first terminal of the third transistor and the input terminal of the output stage transistor circuit. The control terminal of the third transistor is coupled to a control voltage. The other end of the resistor is coupled to ground. The current mirror ratio of the current mirror circuit is from a to a N varies, where a is the ratio of the width to the length of the fourth transistor to the second transistor in the output stage transistor circuit, and N is the ratio of the width to the length of the second transistor to the first transistor, where N is greater than or equal to 80. According to the change of the reference current, the change of the mirror ratio is divided into four intervals: Interval 1, Iref R ≤ (Vgs2) / 50, and the mirror ratio is a; Interval 2, Vgs2 / R 50 < Iref ≤ (VB - Vgs3) / R, the mirror ratio starts to rise and is greater than a:1; Interval 3, Iref > (VB - Vgs3) / R, the mirror ratio continues to rise and is less than a N; In Interval 4, Iref ≥ 50 (VB - Vgs3) / R, and the mirror ratio is a N; where, Iref is the reference current, R is the resistor, Vgs2 is the gate-source voltage of the second transistor, Vgs3 is the gate-source voltage of the third transistor, and VB is the control voltage coupled to the control electrode of the third transistor.

2. The current mirror circuit according to claim 1, characterized in that, The reference current generating circuit includes: a current source, One end of the current source is connected to the power supply voltage, and the other end of the current source is coupled to the input stage transistor circuit as the output terminal of the reference current generating circuit.

3. The current mirror circuit according to claim 1, characterized in that, The control voltage is greater than or equal to the sum of the gate-source voltage of the third transistor and the overdrive voltage of the second transistor.

4. The current mirror circuit according to claim 1, characterized in that, The aspect ratio of the second transistor is equal to that of the fourth transistor.

5. The current mirror circuit according to claim 1, characterized in that, The first transistor, the second transistor, the third transistor, and the fourth transistor are N-type transistors.

6. A chip, characterized in that, Includes the current mirror circuit according to any one of claims 1-5.

7. An electronic device, characterized in that, Includes the chip according to claim 6.

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