Method for configuring operating frequency during chip power-on process

Abstract

The application discloses a configuration method of working frequency in on-chip power-on process, comprising the following steps: S1, on-chip power-on, and the working frequency is a board-level crystal oscillator frequency; S2, PLL reset setting; S3, PLL frequency parameter configuration; S4, software release of PLL reset, and starting of frequency locking process; S5, software reading of PLL Loc state; S6, output of required output frequency A after PLL locking; and S7, chip software configuration of burr-free frequency switching circuit, and working frequency switching. The method has the advantages that software can configure the chip frequency, chip frequency configuration pins are omitted, and thus chip manufacturing cost is reduced; software can configure the chip frequency, frequency dial switch or resistor of a chip application board is omitted, device materials are reduced, PCB board area is reduced, and thus application board cost is reduced.

Description

Technical Field

[0001] This invention relates to a method for configuring the operating frequency during the power-on process of a chip. Background Technology

[0002] The traditional method for configuring the main frequency during chip power-up is to reserve a frequency configuration pin on the chip, and then select the chip's operating main frequency on the application circuit board by using a DIP switch or by selectively soldering pull-up and pull-down resistors.

[0003] The configurable operating frequency during chip power-up is achieved through a specific software configuration process, enabling dynamic configuration of the chip's operating frequency during power-up. Simultaneously, a dedicated frequency switching circuit is used to filter out glitches generated during frequency switching, preventing chip crashes.

[0004] The disadvantages of traditional methods are: (1) The chip needs to have frequency configuration pins, which increases the number of PADs and increases manufacturing costs; (2) The application circuit board needs to have a frequency DIP switch or a frequency selection resistor, which affects the PCB layout, increases the PCB area, increases the difficulty of PCB design and manufacturing cost.

[0005] The drawbacks of traditional methods are due to the following reasons: (1) The chip PLL frequency module needs to have frequency configuration information. If PAD selection is used, the number of chip package pins needs to be increased. At the same time, if the chip has multiple PLLs, the number of chip frequency configuration pins will increase exponentially. The increase in chip pins will increase the area of ​​the bare die in the case of PAD Limit, thereby increasing the manufacturing cost of the bare die silicon wafer. When packaging the bare die, the increased PADs will also increase the packaging manufacturing cost.

[0006] (2) On the application circuit board, the chip operating frequency is selected by DIP switches or pull-up / pull-down selectable resistors. Adding resistors or DIP switches will increase the difficulty of PCB layout and routing, increase the PCB board area, and thus increase the PCB manufacturing cost. The selected resistors or DIP switches also increase the cost of PCB components. Summary of the Invention

[0007] In response to the above technical problems, the invention proposes a method for configuring the operating frequency of a chip during power-up. The purpose is to (1) reduce the number of chip pins, thereby reducing chip cost; (2) reduce the number of components on the application board, reduce PCB wiring difficulty, and reduce PCB manufacturing cost; and (3) realize dynamic adjustment of the chip main frequency, increasing application flexibility.

[0008] The technical solution adopted is as follows: A method for configuring the operating frequency of a chip during power-up includes the following steps: When the chip is powered on, the operating frequency can be configured to frequency A according to application requirements. S1. After the chip is powered on, it directly operates at the board-level crystal oscillator frequency to perform necessary initialization work. S2. The chip first resets the phase-locked loop (PLL) settings, putting it into a reset and initialization configuration state. S3. According to the required operating frequency A, the chip configures the PLL frequency parameters. At this time, the PLL reset is always effective and the PLL is in the reset state. S4. After completing the PLL frequency parameter configuration word, the software releases the PLL reset, and the PLL starts to execute the frequency locking process according to the frequency configuration word. S5. After the PLL frequency is locked, the PLL outputs the Lock state. If the PLL Lock state is locked when the PLL is locked, the software proceeds to the next step. If it is not locked, the software program reads the PLL Lock state again. S6. After the phase-locked loop (PLL) is locked, the PLL outputs the required output frequency A. S7. The chip software is configured with a glitch-free frequency switching circuit to switch the operating frequency.

[0009] In a preferred embodiment of the present invention, the PLL locking in S5 requires a certain amount of time. The chip software determines whether the PLL locking is complete by cyclically reading the PLL Lock status. This solution combines dedicated frequency configuration circuit logic with frequency configuration software to enable the chip to switch from the board-level crystal oscillator frequency to the normal operating frequency upon startup. Simultaneously, the chip continues to operate normally without any abnormal states during the switching process. This technology saves a significant number of chip frequency configuration pins and components on the chip application board, optimizing chip and application board design and reducing chip and PCB manufacturing costs.

[0010] In a preferred embodiment of the present invention, the chip software is configured with a glitch-free frequency switching circuit to switch from the board-level crystal oscillator clock to the PLL output clock, thereby completing the power-on configuration of the chip's operating frequency. The glitch-free frequency switching circuit is a glitch-free clock switch. The glitch-free clock switch circuit uses basic D-Reg flip-flops, AND gate units, and OR gate units stacked to achieve dual clock switching functionality. This clock circuit receives two clock inputs with different frequencies and phases, generates a clock with the same phase and frequency as the selected input clock, and does not generate glitches during the clock switching process, thus achieving glitch-free clock frequency switching.

[0011] The glitch-free clock switch mentioned in the technical solution of this invention is a known technology, which is known to those skilled in the art.

[0012] Compared with the prior art, the beneficial effects of this invention are: 1. The method of the present invention allows the software to configure the chip frequency, eliminating the need for chip frequency configuration pins, thereby reducing chip manufacturing costs.

[0013] 2. The method of the present invention allows the software to configure the chip frequency, eliminating the need for frequency DIP switches or resistors on the chip application board, reducing component materials, reducing PCB board area, and thus reducing application board cost. Attached Figure Description

[0014] Figure 1 This is a flowchart of the method in this embodiment.

[0015] Figure 2 This is a circuit diagram of the Glitch Free Clock Switch in this embodiment. Detailed Implementation

[0016] The technical solution of the present invention will be described in detail below, but the scope of protection of the present invention is not limited to the embodiments described.

[0017] To make the content of this invention clearer and easier to understand, the following description is in conjunction with the appendix. Figure 1 - Appendix Figure 2 The specific implementation methods will be further described below.

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0019] like Figure 1 As shown, the method for configuring the operating frequency during chip power-up is as follows: When the chip powers on, the operating frequency can be configured to frequency A according to application requirements. The specific operating frequency configuration method includes the following steps: S1. After the chip is powered on, it directly operates at the board-level crystal oscillator frequency to perform necessary initialization work. S2. The chip first resets the phase-locked loop (PLL) settings, putting it into a reset and initialization configuration state. S3. According to the required operating frequency A, the chip configures the PLL frequency parameters. At this time, the PLL reset is always effective and the PLL is in the reset state. S4. After completing the PLL frequency parameter configuration word, the software releases the PLL reset, and the PLL starts to execute the frequency locking process according to the frequency configuration word. S5. After the PLL frequency is locked, the PLL outputs a Lock state. The PLL locking process takes a certain amount of time. The chip software reads the PLL Lock state repeatedly to determine whether the PLL is locked. If the PLL Lock state is locked, the software proceeds to the next step. If it is not locked, the software program reads the PLL Lock state again. S6. After the phase-locked loop (PLL) is locked, the PLL outputs the required output frequency A. S7. The chip software is configured with a glitch-free frequency switching circuit to switch the operating frequency.

[0020] like Figure 2 As shown, the chip software configures a glitch-free frequency switching circuit to switch from the board-level crystal oscillator clock to the PLL output clock, completing the power-on configuration of the chip's operating frequency. The glitch-free frequency switching circuit is a glitch-free clock switch. The glitch-free clock switch circuit uses basic D-Reg flip-flops, AND gate units, and OR gate units stacked to realize the dual clock switching function. This clock circuit receives two clock inputs with different frequencies and phases, generates a clock with the same phase and frequency as the selected input clock, and does not generate glitches during the clock switching process.

[0021] like Figure 2 As shown, it should be noted that both input clocks need to be in a stable state when switching clocks; otherwise, clock switching cannot be completed correctly and the circuit will have no clock output.

[0022] Application Examples The HC3020 series high-performance general-purpose DSP chips, HC3080 series high-performance general-purpose DSP chips, KWDSP high-performance general-purpose DSP chips, and MCU embedded chips jointly developed by Jiangsu Huachuang Microsystems Co., Ltd. and the 14th Research Institute of China Electronics Technology Group Corporation all adopt this technology, realizing software configuration and frequency switching of the main operating frequency during power-on. This technology optimizes chip pins, saves on the number of components used on the chip application board, reduces PCB routing complexity, and lowers design and manufacturing costs.

[0023] All parts not covered in this invention are the same as or can be implemented using existing technologies.

[0024] As described above, although the invention has been shown and described with reference to specific preferred embodiments, it should not be construed as limiting the invention itself. Various changes in form and detail may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for configuring the operating frequency during chip power-on, characterized in that: When the chip is powered on, its operating frequency is configured to frequency A according to application requirements. The specific method for configuring the operating frequency includes the following steps: S1. After the chip is powered on, it directly operates at the board-level crystal oscillator frequency to perform initialization. S2. The chip first resets the phase-locked loop (PLL) settings, putting it into a reset and initialization configuration state. S3. According to the required operating frequency A, the chip configures the PLL frequency parameters. At this time, the PLL reset is always effective and the PLL is in the reset state. S4. After completing the PLL frequency parameter configuration word, the software releases the PLL reset, and the PLL starts to execute the frequency locking process according to the frequency configuration word. S5. After the PLL frequency is locked, the PLL outputs a Lock state. If the PLL Lock state is locked, the software proceeds to the next step. If not locked, the software program will read the PLLlock state of the phase-locked loop (PLL) again. S6. After the phase-locked loop (PLL) is locked, the PLL outputs the required output frequency A. S7. The chip software configures a glitch-free frequency switching circuit to switch the operating frequency. The chip software configures a glitch-free frequency switching circuit to switch from the board-level crystal oscillator clock to the PLL output clock, completing the power-on configuration of the chip's operating frequency. Among them, the glitch-free frequency switching circuit is a glitch-free clock switch circuit. The glitch-free clock switch circuit is configured to perform clock switching only when both the board-level crystal oscillator clock and the PLL output clock are in a stable state. The glitch-free clock switch circuit uses D-Reg flip-flops, AND gate units, and OR gate units stacked to realize the dual clock switching function, which is used to receive two clock inputs with different frequencies and phases and generate a clock with the same phase and frequency as the selected input clock.

2. The method for configuring the operating frequency during chip power-on according to claim 1, characterized in that: In S5, the PLL lock-up requires a certain amount of time. The chip software determines whether the PLL lock-up is complete by cyclically reading the PLL Lock status.

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