A low-power design approach that incorporates power gating and creates an electric ground grid.

Abstract

This invention provides a low-power design method for inserting power gating units and creating a ground grid, comprising: inserting power gating units during the physical implementation layout planning stage to achieve power-off design of macrocell and standard cell regions; completing the cascading of the power scan chain to form a loop chain, facilitating the access of power gating signals from any position; creating the ground grid to enable access of normally-on power supplies and the supply of power to the design by power-off and ground; and inserting boundary cells and tap cells to avoid violations of physical design rules. This method solves problems such as the inability of electronic design automation tools to completely cover the macrocell channel area and adjacent areas above and below when inserting power gating units, the limitations of the power gating signal scan chain on the placement of power gating signal interfaces, and the area waste caused by automatically inserting physical cell tap cells; it can also be used in the physical design of integrated circuits without macrocells.

Description

Technical Field

[0001] This invention belongs to the field of chip digital back-end design technology. Background Technology

[0002] With continuous advancements in manufacturing processes and increases in design complexity and integration, power consumption has become a critical factor affecting chip performance. Simultaneously, the market is increasingly pursuing low-power chip performance. Therefore, more and more designs are employing power gating technology to reduce leakage current and achieve power reduction goals. In physical implementation, electronic design automation (EDA) tools can only simply insert power gates in a left-to-right or right-to-left order with fixed intervals. The power gating signals are then chained together according to the order of addition. However, in designs with macrocells, this method of adding power gates can easily result in situations where power gates are not inserted in the channel area between two macrocells or in adjacent areas above and below macrocells, leading to a lack of power supply in those areas. Furthermore, the power gating signal scan chain restricts the input and output port positions of the power gating signals. In addition, when inserting tap cells to avoid latch-up effects, EDA tools can only simply insert them in a left-to-right or right-to-left order with fixed intervals in each row of the design. However, most power gating units already incorporate latch-up prevention mechanisms in their circuitry. Therefore, it's unnecessary to insert tap cells in every row of the design to reduce wasted space. Finally, each gating unit insertion scheme requires a corresponding power network to supply power. Summary of the Invention

[0003] This invention provides a low-power design method for inserting power gating cells and creating a ground grid, addressing the following issues in the physical implementation of low-power integrated circuit design: First, electronic design automation (EDA) tools cannot completely cover the macrocell channel area and adjacent areas when inserting power gating cells; second, the power gating signal scan chain implemented by EDA tools restricts the placement of power gating signal interfaces; and third, the area wastage caused by the automatic insertion of physical unit tap cells by EDA tools. A corresponding ground grid creation scheme is also provided.

[0004] To solve the above problems, the technical solution of the present invention is as follows:

[0005] A low-power design method for inserting power gating and creating an electric ground grid includes the insertion of physical units, the insertion of power gating units, the implementation of gating signal scan chains, and the creation of corresponding electric ground grids.

[0006] The specific implementation steps include:

[0007] Step 1: Insert boundary elements;

[0008] Step 2: First, insert a column of power gating units on the left and right sides of the macro cell in the order from the bottom up, and name these gating units psw_for_macro. Then, insert power gating units in the other areas of the entire design in the order from bottom to top and from left to right, and at fixed intervals.

[0009] Step 3: Connect the power gating signals of all power gating units except those named psw_for_macro into a loop chain;

[0010] Step 4: Connect the power gating signals of the power gating unit named psw_for_macro into a U-shaped chain for each column, and connect the input and output terminals to the power gating signal loop chain described in step 3).

[0011] Step 5: Calculate the interval of the physical unit tap cell according to the fixed interval of the power gating and the physical design rules, and insert the tap cell according to the interval.

[0012] Step 6: Plan the power ground grid based on the power gating insertion interval, the power ground wiring metal layer used, the line width and line spacing of the wiring metal layer, and the width and height of the minimum standard cell of the process used, and complete the creation of the power ground grid.

[0013] The power gating unit has a latch-up prevention function and, in addition to the power ground interface, has only one pair of input and output power switch control interfaces.

[0014] Both the power gating unit and the physical unit are standard units provided by the process manufacturer.

[0015] The power gating signal scan chain is used to control the opening and closing of the power gating unit.

[0016] The power-to-ground network is used to provide a normally-on power supply (always-on VDD) to the power gating unit and a power-to-ground source (VSS) to the entire design, and to supply the shut-down power supply (shut-down VDD) output by the power gating unit to the macrocell.

[0017] The design method described can also be used in the physical design of integrated circuits without macrocells. Attached Figure Description

[0018] Figure 1 This is a basic flowchart illustrating the specific implementation steps of the present invention;

[0019] Figure 2 This is a diagram showing the effect after implementing step 1 of the present invention;

[0020] Figure 3This is a diagram showing the effect after implementing step 2 of the present invention;

[0021] Figure 4 A schematic diagram of the gate signal scan chain for power gating in even-numbered groups;

[0022] Figure 5 This is a schematic diagram of the gate signal scan chain for power gating in odd-numbered groups;

[0023] Figure 6 A schematic diagram of the gate signal scan chain for even-numbered power supply gates;

[0024] Figure 7 A schematic diagram of the gate signal scan chain for odd-numbered power supply gating;

[0025] Figure 8 This is a diagram showing the effect after implementing step 3 of the present invention;

[0026] Figure 9 A schematic diagram of the gate signal scan chain for power gating to supply power to macrocells;

[0027] Figure 10 This is a diagram showing the effect after implementing step 4 of the present invention;

[0028] Figure 11 This is a diagram showing the effect after implementing step 5 of the present invention;

[0029] Figure 12 This is a schematic diagram of the ground grid in a non-macrocell channel region;

[0030] Figure 13 This is a schematic diagram of the electrical ground grid in the macrocell channel region. Detailed Implementation

[0031] The technical solutions provided in this application will be further described below with reference to specific embodiments and accompanying drawings. The advantages and features of this application will become clearer from the following description.

[0032] It should be noted that the embodiments of this application are preferred for implementation and are not intended to limit the application in any way. The technical features or combinations of technical features described in the embodiments of this application should not be considered isolated; they can be combined with each other to achieve better technical effects. The scope of the preferred embodiments of this application may also include other implementations, and this should be understood by those skilled in the art to which the embodiments of this application pertain.

[0033] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of exemplary embodiments may have different values.

[0034] The accompanying drawings in this application are all in a very simplified form and use non-precise proportions, intended only to facilitate and clarify the illustration of the embodiments of this application, and are not intended to limit the implementation of this application. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and purposes achieved by this application, should fall within the scope of the technical content disclosed in this application. Furthermore, the same reference numerals appearing in the various drawings of this application represent the same features or components, and can be applied to different embodiments.

[0035] In low-power integrated circuit design, power gating is a commonly used low-power design method, widely applied to the implementation of various power-off designs. However, in designs with macrocells (such as memory and IP cores), the automated workflow of Electronic Design Automation (EDA) tools alone cannot effectively insert power gating. This invention involves inserting power gating in designs with macrocells and creating corresponding ground grids. The method includes: inserting power gating cells during the physical implementation layout planning stage to achieve power-off design for macrocell and standard cell regions; completing the cascading of the power scan chain to form a loop chain, facilitating the access of power gating signals from any location; creating the ground grid to enable access to normally-on power supplies and to supply power to the design via power-off and ground. Furthermore, it involves inserting physical cells: boundary cells and tap cells, to avoid violations of physical design rules.

[0036] The following description, in conjunction with the accompanying drawings and embodiments, provides further details.

[0037] Example

[0038] like Figure 1 As shown, the specific implementation steps of the present invention for inserting power gating and creating an electrical-to-ground network are as follows:

[0039] Step 1: Insert boundary elements;

[0040] Step 2: First, insert a column of power gating units on the left and right sides of the macro cell in the order from the bottom up, and name these gating units psw_for_macro. Then, insert power gating units in the other areas of the entire design in the order from bottom to top and from left to right, and at fixed intervals.

[0041] Step 3: Connect the power gating signals of all power gating units except those named psw_for_macro into a loop chain;

[0042] Step 4: Connect the power gating signals of the power gating unit named psw_for_macro into a U-shaped chain for each column, and connect the input and output terminals to the power gating signal loop chain described in Step 3.

[0043] Step 5: Calculate the interval of the physical unit tap cell according to the fixed interval of the power gating and the physical design rules, and insert the tap cell according to the interval.

[0044] Step 6: Plan the power ground grid based on the power gating insertion interval, the power ground wiring metal layer used, the line width and line spacing of the wiring metal layer, and the width and height of the minimum standard cell of the process used, and complete the creation of the power ground grid.

[0045] All of the above steps are performed after the shape and size planning and macro-unit layout of the design are completed.

[0046] In step 1, before inserting boundary cells, the coordinates of the top left and top right corners of the macro cell are captured to calculate the distance from the top and bottom edges of the macro cell to the design bottom edge. It is then determined whether this distance is an integer multiple of the height of four minimum standard cells. If not, a place blockage is created to change the height of each placeable top and bottom edge to an integer multiple of the height of four minimum standard cells. This avoids incomplete coverage of gated cells in the adjacent areas above and below the macro cell. The effect after this step is shown in [the image / description]. Figure 2 .

[0047] Step 2 includes the following steps:

[0048] 2.1 Grab the area of ​​the boundary cell, expand the left and right sides of the area by the width of a power gating cell, create a placement barrier area in the expanded area, and name it pblk1;

[0049] 2.2 Capture all areas of the entire design except pblk1 by passing parameters, create and place barrier areas in these areas, and name them pblk2;

[0050] 2.3 Delete pblk1, create a placement barrier region in the boundary cell region, and name it pblk3;

[0051] 2.4 All regions of the entire design except pblk2 and pblk3 are captured via parameter passing, and the area of ​​each region is described in the form of the lower left corner coordinate plus the upper right corner coordinate. Then, these regions are traversed, and regions that satisfy the condition of having macrocells within a distance of less than 5µm on both sides, and having no macrocells on that region, are placed in a list.

[0052] 2.5 Arrange the region list in ascending order of its bottom left horizontal coordinate. By traversing the arranged list, quickly add power gating units for the regions in the same column in left-to-right order to complete the insertion of power gating units that supply power to the macrocells;

[0053] 2.6 Remove the blocking areas pblk2 and pblk3, and insert the power gating units in the entire design area in a bottom-to-top, left-to-right order with fixed intervals.

[0054] The effect after step 2 above is as follows: Figure 3 .

[0055] Step 3 includes the following steps:

[0056] 3.1 Arrange the x-coordinates of the lower left corner of all power gating units except those named psw_for_macro in ascending order, and determine whether the total number of columns of the gating units is odd or even. When the total number of columns is even, starting from the x-coordinate of the first column, divide the x-coordinate into even-numbered and odd-numbered groups based on the parity of the serial number, using 0 as the starting number. When the total number of columns is odd, the power gating unit of the first column implements a separate scan chain, and starting from the x-coordinate of the second column, divide the x-coordinate into even-numbered and odd-numbered groups based on the parity of the serial number, using 0 as the starting number.

[0057] 3.2 Chain the power gating signals in the even-numbered groups (horizontal coordinates) from left to right, first from bottom to top and then from top to bottom, as shown below. Figure 4 As shown;

[0058] 3.3 Determine whether the total number of power gating signals in the odd-numbered group is even. If yes, chain the gating signals of the power gating signals in the odd-numbered group (horizontal coordinate) from bottom to top and then from top to bottom, in order from right to left. If not, chain the gating signals of the power gating signals in the odd-numbered group (horizontal coordinate) from top to bottom and then from bottom to top, in order from right to left. Figure 5 As shown;

[0059] 3.4 Finally, connect the two scan chains end to end as follows: Figure 6As shown, it determines whether the total number of columns of the power gating units other than those named psw_for_macro is odd. When the determination result is yes, the scan link of the first column of gating units is added to the scan chain that has completed the first-to-last connection, as shown above. Figure 7 As shown.

[0060] After the above steps, the gating signal scan chain for all power gating units except for the one named psw_for_macro is implemented. The result after this step is shown in the image below. Figure 8 As shown.

[0061] Step 4 involves iterating through all macrocell power gating regions to determine if there are macrocells above or below the region or if it is a design boundary. If so, the power gating signal for that region is strung into an inverted U-shape; otherwise, it is strung into a regular U-shape. Figure 9 As shown. Then, by searching for the power gating of the nearest core area in this region, disconnect its power gating signal connection and connect it to the beginning and end of the U-shaped power gating signal chain.

[0062] The result after performing this step is shown in the image below. Figure 10 As shown.

[0063] In step 5, the inserted tap cells are placed in the macrocell power gating area; one tap cell is added to every row except those in power gating areas. In other power gating areas, tap cells are added in a checkerboard pattern. The result after this step is shown in the image below. Figure 11 As shown.

[0064] Step 6, creating the ground grid, involves the following steps: first, creating the ground grid; then, connecting the normally open power supply of the power gating; next, creating the power-off grid; and finally, connecting the power-off macrocell power supply.

[0065] The above description is merely a description of preferred embodiments of this application and is not intended to limit the scope of this application in any way. Any changes or modifications made by those skilled in the art based on the above-disclosed technical content should be considered as equivalent and valid embodiments and fall within the scope of protection of the technical solution of this application.

Claims

1. A low power design method of inserting power gating and creating an electrical ground grid, characterized by, The steps include inserting physical cells, inserting power gating cells, implementing gated signal scan chains, and creating a corresponding power ground grid. The specific implementation steps include: Step 1, inserting boundary cells; Step 2, inserting a column of power gating cells on the left and right sides of the macro cell in a bottom-up order, naming the power gating cells as psw_for_macro, and then inserting power gating cells in other regions of the entire design in a bottom-up and left-to-right order and at a fixed interval; Step 3, stringing the power gating signals of the power gating cells other than the psw_for_macro into a ring chain; Step 4, stringing the power gating signals of the psw_for_macro into a U-shaped chain for each column, and connecting the input and output ends to the power gating signal ring chain described in Step 3; Step 5, calculating the interval of the tap cell according to the fixed interval of the power gating and the physical design rules, and inserting the tap cell at the interval; Step 6, planning the power ground grid according to the insertion interval of the power gating, the used power ground wiring metal layer, the line width and line spacing of the wiring metal layer, and the width and height of the minimum standard cell of the used process, and completing the creation of the power ground grid.

2. The low-power design method of inserting power gating and creating a power ground grid according to claim 1, wherein before inserting the boundary cells in Step 1, the upper and lower edges of the macro cell to the bottom edge of the design are calculated by grabbing the upper left corner and upper right corner coordinates of the macro cell, and it is determined whether the interval is an integer multiple of four minimum standard cell heights, if not, each layoutable upper and lower edge is changed to an integer multiple of four minimum standard cell heights by creating a placement barrier, thus avoiding the case that the macro cell adjacent area is not fully covered by the gating cell.

3. The low power design method of inserting power gated and creating electrical ground mesh of claim 1, wherein, Step 2 includes the following steps: 2.1 Grab the region of the boundary cell, expand the left and right sides of the region by one width of the power gating cell, create a placement barrier in the expanded region, and name it pblk1; 2.2 Grab all regions of the entire design except pblk1 by parameter passing, create a placement barrier in these regions, and name it pblk2; 2.3 Delete pblk1, create a placement barrier in the boundary cell region, and name it pblk3; 2.4 Grab all regions of the entire design except pblk2 and pblk3 by parameter passing, and specify the area of each region in the form of lower left corner coordinates plus upper right corner coordinates; then traverse these regions, and put the regions that meet the conditions of having a macro cell within a distance of less than 5um on the left and right sides and having no macro cell on the region into a list; 2.5 Arrange the region list in the order of left lower corner horizontal coordinates from small to large; traverse the arranged list, and quickly add the power gating cells of the regions in the same column from left to right to complete the insertion of the power gating cells for supplying power to the macro cell. 2.6 delete the placement of the barrier pblk2 and pblk3, in the entire design area by from bottom to top, from left to right order and fixed interval insertion power gate unit.

4. The low power design method of inserting power gated and creating electrical ground mesh of claim 1, wherein, The step 3 comprises the following steps: 3.1 arrange the horizontal coordinates of the lower left corner coordinates of the power gate units except the one named psw_for_macro in ascending order, and determine whether the total number of columns of the gate units is odd or even; when the total number of columns is even, start from the horizontal coordinate of the first column, and divide the horizontal coordinates into even number sequence group and odd number sequence group according to the parity of the sequence number with 0 as the starting sequence number; when the total number of columns is odd, the power gate unit in the first column realizes the scan chain alone, and start from the horizontal coordinate of the second column, and divide the horizontal coordinates into even number sequence group and odd number sequence group according to the parity of the sequence number with 0 as the starting sequence number; 3.2 arrange the gate signals of the power gate units in the even number sequence group in the horizontal coordinates in the order from left to right, first from bottom to top and then from top to bottom into a chain; 3.3 determine whether the total number of columns of the power gate units in the odd number sequence group is even, if yes, arrange the gate signals of the power gate units in the odd number sequence group in the horizontal coordinates in the order from right to left, first from bottom to top and then from top to bottom into a chain; if no, arrange the gate signals of the power gate units in the odd number sequence group in the horizontal coordinates in the order from right to left, first from top to bottom and then from bottom to top into a chain; 3.4 finally connect the head and tail of the two scan chains, and determine whether the total number of columns of the power gate units except the one named psw_for_macro is odd; when the determination result is yes, connect the scan chain of the first column gate unit into the scan chain after the head and tail are connected; After the above steps, the gate signal scan chain of the power gate units except the one named psw_for_macro is realized.

5. The low power design method of inserting power gated and creating electrical ground mesh of claim 1, wherein, The step 4 comprises the following steps: by traversing all the macro unit power gate regions, determine whether there are macro units above and below the region or whether it is the boundary of the design, if yes, connect the power gate signals of the region into an inverted U type, otherwise, connect the power gate signals into a U type; and then search the power gate of the core region near the region, disconnect the power gate signals, and connect the head and tail of the U type power gate signal chain.

6. The low power design method of inserting power gated and creating electrical ground mesh of claim 1, wherein, The step 5 inserts tap cells in the macro unit power gate region, and adds one to all the rows except the power gate; in other power gate regions, add in the form of a chessboard.

7. The low power design method of inserting power gated and creating electrical ground mesh of claim 1, wherein, The step 6 of creating the electrical ground grid comprises the following steps: first, create a ground grid; then, connect the always-on power supply of the power gate; then, create a shutoff power grid; finally, connect the shutoff power of the macro unit.

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