A method of patterning an asymmetric pattern
By decomposing asymmetric patterns into symmetrical and asymmetric patterns and using a two-stage etching process to form asymmetric pattern structures, the problem of pattern distortion in pattern processing is solved, and the electrical performance uniformity of the DRAM active region structure and the transistor off-state current distribution are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2021-12-02
- Publication Date
- 2026-05-12
AI Technical Summary
Existing patterning processes can cause pattern distortion in the active region structure when processing asymmetric patterns, affecting the uniformity of the device's electrical performance.
The method of decomposing asymmetric graphics into symmetric and asymmetric patterns is adopted. The first pattern structure and the second pattern structure are formed by two etching processes, and then superimposed to form an asymmetric graphic structure.
This avoids pattern distortion, improves the uniformity of device electrical performance, makes the off-state current distribution of transistors in the array more concentrated, and improves the operating window.
Smart Images
Figure CN116230500B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device fabrication technology, and in particular to a method for patterning asymmetric patterns. Background Technology
[0002] Current mainstream DRAM products generally adopt the 6F2 device structure, in which the active areas (AA) are designed with staggered arrangement to achieve the densest final capacitor stacking. This staggered arrangement brings challenges to the patterning process, due to the asymmetrical pattern distribution around the active areas and the unavoidable passivation effect in the etching process. Figure 7 Top view of the active area of 1X DRAM devices manufactured by three different manufacturers. The white part is the active area structure. The layout is designed with uniform fins, which ultimately results in a noticeable pattern distortion visible on the product. Figure 8 Analysis of the causes of pattern distortion (a is a top view of the hard mask before etching, b is a comparison of pattern etching in regions A and B, c is a top view of the fin after etching). Due to the asymmetry of the pattern, the open area of the pattern to the left of point A will form more by-products during the etching process. These by-products adhere to point A, causing excessive passivation and resulting in pattern distortion. Moreover, this passivation is a cumulative effect. The pattern distortion at the bottom of the active region is significantly greater than that at the top. The longitudinal cross-sectional morphology of the sample also confirms this. Figure 9 The simulation of device leakage current for DRAM active region shape distortion shows that fin shape has a significant impact on off-state current.
[0003] It is evident that existing pattern processing techniques can cause pattern distortion in the active region structure when processing asymmetric patterns. This distortion significantly affects the electrical performance of the device and reduces the uniformity of its electrical performance. Summary of the Invention
[0004] This invention provides a patterning method for asymmetric patterns to solve the technical problem that existing pattern processing technology causes pattern distortion in the active region structure when processing asymmetric patterns. Pattern distortion in the active region structure significantly affects the electrical performance of the device and reduces the uniformity of the device's electrical performance.
[0005] To address the aforementioned technical problems, this invention discloses a method for patterning asymmetrical graphics, comprising the following steps:
[0006] Provide a base;
[0007] A layer of material to be etched is formed on the substrate;
[0008] A first mask layer is formed on the surface of the material layer to be etched, and a preset symmetrical pattern is defined through the first mask layer;
[0009] The symmetrical pattern is transferred into the material layer to be etched through the first etching process to form the first pattern structure;
[0010] A second mask layer is formed on the surface of the first pattern structure, and a preset asymmetric pattern is defined through the second mask layer;
[0011] The asymmetric pattern is transferred into the material layer to be etched through a second etching process to form a second pattern structure.
[0012] The first pattern structure and the second pattern structure are superimposed to form an asymmetrical graphic structure.
[0013] Preferably, the first mask layer is a hard mask layer with a symmetrical pattern; the second mask layer is an anti-reflection layer with an asymmetrical pattern.
[0014] Preferably, the first pattern structure is a periodic line shape, circle, ellipse or irregular shape.
[0015] Preferably, the second pattern structure is a periodic or non-periodic line shape, circle, ellipse or irregular shape.
[0016] Preferably, the anti-reflective layer is formed by spin coating.
[0017] Preferably, the asymmetric graphic structure is an active region structure.
[0018] Preferably, the first etching process and the second etching process can employ direct exposure, self-aligned multiple exposure, or other standardized patterning processes.
[0019] Preferably, after the antireflective layer is formed by spin coating, the antireflective layer is smoothed by chemical mechanical polishing.
[0020] Preferably, the height of the anti-reflective layer after grinding is higher than that of the hard mask layer.
[0021] Preferably, the second pattern structure is decomposed into several sets of asymmetrical patterns, and the second etching process is repeated until the second pattern structure is formed by superimposing several sets of asymmetrical patterns.
[0022] The technical solution of this invention has the following advantages: This invention provides a patterning method for asymmetric patterns, comprising the following steps: providing a substrate; forming a material layer to be etched on the substrate; forming a first mask layer on the surface of the material layer to be etched, defining a preset symmetrical pattern through the first mask layer; transferring the symmetrical pattern into the material layer to be etched through a first etching process to form a first pattern structure; forming a second mask layer on the surface of the first pattern structure, defining a preset asymmetric pattern through the second mask layer; transferring the asymmetric pattern into the material layer to be etched through a second etching process to form a second pattern structure; the first pattern structure and the second pattern structure are superimposed to form an asymmetric pattern structure. This invention is an improvement on pattern processing technology, mainly by decomposing asymmetric patterns into symmetrical and asymmetric patterns and processing them separately, avoiding pattern distortion caused by asymmetric patterns, improving the uniformity of device electrical performance, and can be widely applied to the active region structure of DRAM, resulting in a more concentrated distribution of transistor off-state current in the array and an improved operating window.
[0023] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the means particularly pointed out in the written description and the accompanying drawings.
[0024] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0025] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:
[0026] Figure 1 This is a schematic diagram illustrating the steps of a method for patterning asymmetrical graphics according to the present invention.
[0027] Figures 2-6 This is a cross-sectional schematic diagram of the process flow of a patterning method for asymmetric graphics according to the present invention.
[0028] Figure 7 This is a top view of the active area of a 1X DRAM device manufactured by three different manufacturers in the background art.
[0029] Figure 8 Analysis of the causes of graphic distortion in the background technology;
[0030] Figure 9 This is a schematic diagram illustrating the device leakage current simulation for the distorted shape of the active region in DRAM, as shown in the background art.
[0031] In the figure: 1. Symmetrical pattern; 2. Material layer to be etched; 3. First pattern structure; 4. Asymmetrical pattern; 5. Second pattern structure; 6. Hard mask layer; 7. Anti-reflection layer. Detailed Implementation
[0032] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.
[0033] Furthermore, in this invention, the use of terms such as "first" and "second" is for descriptive purposes only and does not specifically refer to any order or sequence, nor is it intended to limit the invention. They are merely used to distinguish components or operations described using the same technical terms and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions and features of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If a combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.
[0034] Example 1:
[0035] This invention provides a method for patterning asymmetrical graphics, such as... Figure 1-6 As shown, it includes the following steps:
[0036] Step 1: Provide a substrate;
[0037] Step 2: Form the material layer 2 to be etched on the substrate;
[0038] Step 3: Form a first mask layer on the surface of the material layer 2 to be etched, and define a preset symmetrical pattern 1 through the first mask layer;
[0039] Step 4: Through the first etching process, the symmetrical pattern 1 is transferred into the material layer 2 to be etched, forming the first pattern structure 3;
[0040] Step 5: Form a second mask layer on the surface of the first pattern structure 3, and define a preset asymmetric pattern 4 through the second mask layer;
[0041] Step 6: The asymmetric pattern 4 is transferred into the material layer 2 to be etched through a second etching process to form a second pattern structure 5;
[0042] The first pattern structure 3 and the second pattern structure 5 are superimposed to form an asymmetric graphic structure, which is an active region structure.
[0043] The working principle and beneficial effects of the above technical solution are as follows: The process flow proposed in this invention is applicable to semiconductor device structures with the following characteristics: a. The minimum repeating unit size (Pitch) is less than 80nm; b. The device layout can be decomposed into a uniform symmetrical pattern 1 and an asymmetrical pattern 4, such as the active region structure of a DRAM device, or the fin structure of a FinFET. When using the process of this invention, the asymmetrical pattern of the device layout is first decomposed into a symmetrical pattern 1 and an asymmetrical pattern 4. Then, a substrate is prepared, and a material layer 2 to be etched is formed on the substrate. Next, a first mask layer (such as...) is formed on the surface of the material layer 2 to be etched. Figure 2 As shown), a preset symmetrical pattern 1 is defined through the first mask layer (as shown). Figure 3 As shown), the symmetrical pattern 1 can be fabricated using photolithography, and then transferred to the material layer 2 to be etched through a first etching process to form the first pattern structure 3 (as shown). Figure 4 As shown), a second mask layer is then formed on the surface of the first pattern structure 3, and a preset asymmetric pattern 4 is defined through the second mask layer (as shown). Figure 5 As shown), the asymmetric pattern 4 can be fabricated using photolithography, and then transferred to the material layer 2 to be etched using a second etching process to form the second pattern structure 5. The first pattern structure 3 and the second pattern structure 5 are superimposed to form an asymmetric graphic structure (as shown). Figure 6 As shown in the figure, a device structure with an asymmetric pattern structure is finally formed. The asymmetric pattern structure is an active region structure. The above method avoids the pattern distortion caused by the asymmetric pattern during a single patterning process. The improvement of the pattern processing technology in this invention is mainly to decompose the asymmetric pattern into a symmetric pattern 1 and an asymmetric pattern 4, and process them sequentially. This avoids the problem of pattern distortion in the active region structure caused by the existing pattern processing technology when processing asymmetric patterns, and improves the uniformity of the device's electrical performance. It can be widely used in the active region structure of DRAM, which is manifested in a more concentrated distribution of the off-state current of the transistors in the array and an improved operating window.
[0044] Example 2
[0045] Based on the above embodiment 1, as follows Figure 1-6 As shown, the first mask layer is a hard mask layer 6, which has a symmetrical pattern 1; the second mask layer is an anti-reflection layer 7, which has an asymmetrical pattern 4.
[0046] The first pattern structure 3 is a periodic line shape, circle, ellipse or irregular shape;
[0047] The second pattern structure 5 is a periodic or non-periodic line shape, circle, ellipse or irregular shape;
[0048] The anti-reflective layer 7 is formed by spin coating. After the anti-reflective layer 7 is formed by spin coating, it is smoothed by chemical mechanical polishing. The height of the smoothed anti-reflective layer 7 is higher than that of the hard mask layer 6.
[0049] The working principle and beneficial effects of the above technical solution are as follows: The first mask layer is a hard mask layer 6, which has a symmetrical pattern 1. The actual etching selectivity of the hard mask layer 6 is not lower than the target etching selectivity, thereby ensuring that the material layer 2 to be etched will not be damaged during the etching process. The target etching selectivity is a preset value, which is preset according to different devices. After the hard mask layer 6 is fabricated, a uniform symmetrical pattern 1 that is periodically repeated needs to be photolithographically etched on the surface of the hard mask layer 6. The symmetrical pattern 1 is mirror-symmetrical about the center line of the material layer 2 to be etched (e.g., ...). Figure 3 (As shown), then an etching process is used to transfer the symmetrical pattern 1 into the material layer 2 to be etched. After etching, the symmetrical pattern 1 extends into the material layer 2 to form a first pattern structure 3. The first pattern structure 3 is a periodic line shape, circle, ellipse or irregular shape (such as...). Figure 4 (As shown), then an anti-reflective layer 7 is fabricated on the surface of the first patterned structure 3. The anti-reflective layer 7 is formed by spin coating and is an organic anti-reflective layer. The anti-reflective layer 7 is finally formed on the surface of the hard mask layer 6 and fills into the interior of the first patterned structure 3. Then, an asymmetric pattern 4 (as shown) is photolithographically etched on the surface of the anti-reflective layer 7. Figure 5 As shown), after the asymmetric pattern 4 is fabricated, it is transferred to the material layer 2 to be etched using an etching process. After etching, the asymmetric pattern 4 extends into the material layer 2 and superimposes with the first pattern structure 3 to form the second pattern structure 5. The second pattern structure 5 is a periodic or non-periodic line shape, circle, ellipse, or irregular shape (such as...). Figure 6 As shown in the figure, the above process avoids the pattern distortion caused by asymmetric patterns, improves the uniformity of the electrical performance of the device, and can be widely used in the active region structure of DRAM. It is manifested in the more concentrated distribution of the off-state current of transistors in the array and the improved operating window.
[0050] Optionally, after forming the antireflective layer 7 by spin coating, the antireflective layer 7 is smoothed by chemical mechanical polishing. The height of the smoothed antireflective layer 7 is higher than that of the hard mask layer 6, which makes the antireflective layer 7 smoother and facilitates the accurate photolithography of the asymmetric pattern 4 on the surface of the antireflective layer 7.
[0051] Example 3
[0052] Based on Example 1 or 2, the first etching process and the second etching process may employ direct exposure, self-aligned multiple exposure, or other standardized patterning processes.
[0053] The working principle and beneficial effects of the above technical solution are as follows: The first etching process and the second etching process can adopt direct exposure, self-aligned multiple exposure or other standardized patterning processes. Self-aligned multiple exposure (SADP) is a dual patterning process that replaces the traditional LELE method. The dual patterning technical solution through sidewall self-alignment process is as follows: the axial pattern is formed by a photolithography and etching process, and then the sidewall pattern is formed by atomic layer deposition and etching process on the sidewall. The axial layer (i.e., the sacrificial layer) is removed, and a sidewall hard mask pattern with half pitch is formed.
[0054] Example 4
[0055] Based on Example 2, the second pattern structure 5 is decomposed into several groups of asymmetric patterns 4, and the second etching process is repeated until the second pattern structure 5 is formed by superimposing several groups of asymmetric patterns 4.
[0056] The working principle and beneficial effects of the above technical solution are as follows: According to the layout and process requirements, the second pattern structure 5 is decomposed into several groups of asymmetric patterns 4, and the second etching process is repeated until the second pattern structure 5 is composed of several groups of asymmetric patterns 4 superimposed. Specifically, the more complex the second pattern structure 5 is, the more combinations of asymmetric patterns 4 are decomposed from the asymmetric pattern. The asymmetric patterns 4 are divided into several groups. First, the first group of asymmetric patterns 4 is photolithographically etched on the surface of the anti-reflection layer 7 and etched. Then, the anti-reflection layer 7 is re-fabricated on the surface of the hard mask layer 6, and photolithography is performed on the surface of the anti-reflection layer 7. The second set of asymmetric patterns 4 is then etched. The first set of asymmetric patterns 4, the second set of asymmetric patterns 4, and the first pattern structure 3 are superimposed. The above steps are repeated until several sets of asymmetric patterns 4 are etched into the material layer 2 to be etched. At this time, several asymmetric patterns 4 etched into the material layer 2 to be etched constitute the second pattern structure 5, and are superimposed with the first pattern structure 3 to form an active region structure, thereby completing the processing of complex asymmetric patterns, avoiding pattern distortion caused by asymmetric patterns, and further improving the uniformity of the electrical performance of the device.
[0057] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A method for patterning asymmetrical graphics, characterized in that, Includes the following steps: Provide a base; A layer of material to be etched is formed on the substrate (2); A first mask layer is formed on the surface of the material layer (2) to be etched, and a preset symmetrical pattern (1) is defined by the first mask layer; the first mask layer is a hard mask layer (6), and the hard mask layer (6) has a symmetrical pattern (1); The symmetrical pattern (1) is transferred to the material layer (2) to be etched through the first etching process to form the first pattern structure (3); A second mask layer is formed on the surface of the first pattern structure (3), and a preset asymmetric pattern (4) is defined through the second mask layer; the second mask layer is an anti-reflection layer (7), and the anti-reflection layer (7) has an asymmetric pattern (4); The asymmetric pattern (4) is transferred into the material layer (2) to be etched through a second etching process to form a second pattern structure (5); The first pattern structure (3) and the second pattern structure (5) are superimposed to form an asymmetrical graphic structure.
2. The method for patterning asymmetrical graphics according to claim 1, characterized in that, The first pattern structure (3) is a periodic line shape, circle, ellipse or irregular shape.
3. The method for patterning asymmetrical graphics according to claim 1, characterized in that, The second pattern structure (5) is a periodic or non-periodic line shape, circle, ellipse or irregular shape.
4. The method for patterning asymmetrical graphics according to claim 1, characterized in that, The anti-reflective layer (7) is formed by spin coating.
5. The method for patterning asymmetrical graphics according to claim 1, characterized in that, The asymmetric graphic structure is an active region structure.
6. The method for patterning asymmetrical graphics according to claim 1, characterized in that, The first etching process and the second etching process can employ direct exposure, self-aligned multiple exposure, or other standardized patterning processes.
7. The method for patterning asymmetrical graphics according to claim 4, characterized in that, After the anti-reflective layer (7) is formed by spin coating, the anti-reflective layer (7) is smoothed by chemical mechanical polishing.
8. The method for patterning asymmetrical graphics according to claim 7, characterized in that, The height of the anti-reflective layer (7) after grinding is higher than that of the hard mask layer (6).
9. The method for patterning asymmetrical graphics according to claim 3, characterized in that, The second pattern structure (5) is decomposed into several sets of asymmetric patterns (4), and the second etching process is repeated until the second pattern structure (5) is formed by superimposing several sets of asymmetric patterns (4).