Chip yield analysis method and device, electronic equipment and storage medium

Abstract

The present disclosure relates to a chip yield analysis method and device, electronic equipment and computer readable storage medium, and relates to the technical field of semiconductor production and manufacturing. The method comprises: obtaining failure chip information based on chip testing, and obtaining pre-stored failure pattern information and defect process information; based on the failure pattern information and the defect process information, performing data screening processing on the failure chip information to obtain a failure pattern type corresponding to the failure chip; performing position matching processing on the failure pattern position in the failure pattern type and the process defect position to obtain a matched failure pattern matched in position; determining a to-be-analyzed failure data pair corresponding to the matched failure pattern, performing yield loss calculation based on the to-be-analyzed failure data pair, and obtaining a yield loss ratio corresponding to each defect process. The present disclosure can predict the proportion of yield loss caused by the increase of each process defect on yield, and quickly find out the defect process with larger yield loss.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor production and manufacturing, and in particular, to a chip yield analysis method, a chip yield analysis device, an electronic device, and a computer readable storage medium. BACKGROUND

[0002] Chip yield refers to the qualified rate of chips. In the production process, chips that meet the requirements and chips that do not meet the requirements may be produced due to process reasons. The ratio of the number of qualified chips on a wafer to the total number of chips is greater, indicating that the number of useful chips is greater and the waste is less. The factors affecting the chip yield mainly come from two aspects, including: the influence of design, the influence of process defects or disturbance on yield.

[0003] For process defects, the correlation between the process defect position (Defect) and the yield failure area (Failure Shape Analysis, FSA) is currently used to determine the correlation between the two. However, the existing analysis scheme between process defects and yield loss cannot quantify the loss of yield caused by process defects.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to provide a chip yield analysis method, a chip yield analysis device, an electronic device, and a computer readable storage medium, thereby at least partially overcoming the problem of being unable to analyze process defects that have a greater impact on yield loss and being unable to predict the impact of increasing a certain process defect on yield loss.

[0006] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0007] According to a first aspect of the present disclosure, a chip yield analysis method is provided, comprising: obtaining failure chip information based on chip testing, and obtaining pre-stored failure pattern information and defect process information; based on the failure pattern information and the defect process information, performing data screening processing on the failure chip information to obtain a failure pattern type corresponding to the failure chip; performing position matching processing on the failure pattern position in the failure pattern type and the process defect position to obtain a matching failure pattern matched in position; determining a to-be-analyzed failure data pair corresponding to the matching failure pattern, performing yield loss calculation based on the to-be-analyzed failure data pair, and obtaining a yield loss ratio corresponding to each defect process.

[0008] In an example embodiment of the present disclosure, the chip testing comprises a function test; the obtaining of the failure chip information based on the chip testing comprises: obtaining a chip test result based on the function test; obtaining a target wafer based on the chip test result, the target wafer comprising a failure-shaped wafer with more than a preset number of process station data; obtaining a failure chip identifier and chip position information of a failure chip based on the target wafer; and generating the failure chip information based on the failure chip identifier and the failure position information.

[0009] In an example embodiment of the present disclosure, the obtaining of the pre-stored failure pattern information and defect process information comprises: obtaining a pre-stored failure pattern type, determining failure pattern detail information corresponding to each of the failure pattern types; generating the failure pattern information based on the failure pattern detail information of each of the failure pattern types; and obtaining the pre-stored defect process information, the defect process information comprising any one or a combination of defect process types, defect process identifiers, defect process patterns, and defect process positions.

[0010] In an example embodiment of the present disclosure, the obtaining of the pre-stored failure pattern type comprises: determining a pre-defined failure pattern type, and storing the failure pattern type to a failure pattern database; the failure pattern type comprising any one or a combination of a bit failure type, a word line failure type, a bit line failure type, a cross failure type, and a block failure type; the bit failure type comprising a single cell failure type, a double cell failure type, and a cluster cell failure type; the word line failure type comprising a single word line failure type and a multiple word line failure type; the bit line failure type comprising a single bit line failure type and a multiple bit line failure type; the cross failure type being formed by the intersection of the word line failure type and the bit line failure type; and the block failure type comprising at least one failure area block.

[0011] In an example embodiment of the present disclosure, the defect process information comprises a target defect process; and the data screening processing of the failure chip information based on the failure pattern information and the defect process information to obtain a failure pattern type corresponding to the failure chip comprises: determining a target defect process matching a target wafer; and performing data screening processing on the failure chip information based on the failure pattern information and the target defect process to obtain the failure pattern type.

[0012] In an example embodiment of the present disclosure, the position matching processing of the failure pattern positions in the failure pattern types with the process defect positions to obtain matched failure patterns includes: matching each of the failure pattern positions in the failure pattern types with the process defect positions one by one to obtain matching results; and taking the failure pattern whose matching result is that the failure pattern position matches the process defect position as the matched failure pattern.

[0013] In an example embodiment of the present disclosure, the taking the failure pattern whose matching result is that the failure pattern position matches the process defect position as the matched failure pattern includes: when the failure pattern position matches the process defect position, obtaining failure-related information corresponding to the failure pattern position; determining a failure chip identifier based on the failure-related information, and determining the matched failure pattern according to the failure chip identifier.

[0014] In an example embodiment of the present disclosure, the determining the to-be-analyzed failure data pair corresponding to the matched failure pattern includes: obtaining a process pattern data pair formed by the defect process and the matched failure pattern; when one defect process corresponds to multiple matched failure patterns, screening out a matched failure pattern with the highest failure level from the multiple matched failure patterns as a target failure pattern; and generating the to-be-analyzed failure data pair based on the target failure pattern and the defect process.

[0015] In an example embodiment of the present disclosure, the determining the to-be-analyzed failure data pair corresponding to the matched failure pattern further includes: when one matched failure pattern corresponds to multiple defect processes, randomly selecting a defect process from the multiple defect processes as a target defect process; and generating the to-be-analyzed failure data pair based on the target defect process and the matched failure pattern.

[0016] In an example embodiment of the present disclosure, the yield loss calculation based on the to-be-analyzed failure data pair to obtain a yield loss ratio corresponding to each defect process includes: determining a total failure ratio according to the to-be-analyzed failure data pair; determining a to-be-analyzed defect process included in the to-be-analyzed data pair, and determining a process matching ratio corresponding to each to-be-analyzed defect process; and determining yield loss ratios corresponding to multiple to-be-analyzed processes according to the total failure ratio and each process matching ratio.

[0017] In an example embodiment of the present disclosure, the determining of the process matching ratio corresponding to each of the defect processes to be analyzed comprises: determining a total number of failed chips based on the failure data to be analyzed; obtaining a number of process failed chips corresponding to each of the processes to be analyzed; and determining the process matching ratio based on the total number of failed chips and the number of process failed chips.

[0018] In an example embodiment of the present disclosure, the method further comprises: obtaining a preconfigured failure ratio threshold; and taking a defect process with a yield loss ratio greater than the failure ratio threshold as a defect process to be corrected; and performing process adjustment processing on the defect process to be corrected.

[0019] According to a second aspect of the present disclosure, a chip yield analysis device is provided, comprising: an information obtaining module, configured to obtain failure chip information based on chip testing, and obtain pre-stored failure pattern information and defect process information; a failure type determining module, configured to perform data filtering processing on the failure chip information based on the failure pattern information and the defect process information, to obtain a failure pattern type corresponding to a failure chip; a failure pattern matching module, configured to perform position matching processing on a failure pattern position in the failure pattern type and a process defect position, to obtain a matched failure pattern with a matched position; and a yield loss calculating module, configured to determine a failure data pair corresponding to the matched failure pattern, and perform yield loss calculation based on the failure data pair, to obtain a yield loss ratio corresponding to each defect process.

[0020] In an example embodiment of the present disclosure, the chip testing comprises functional testing; the information obtaining module comprises a failure information obtaining module: obtaining chip testing results based on the functional testing; obtaining a target wafer according to the chip testing results, the target wafer comprising a wafer with a failure shape regularity and a number of process site data greater than a preset number; obtaining failure chip identification and chip position information of a failure chip according to the target wafer; and generating failure chip information based on the failure chip identification and the failure position information.

[0021] In an example embodiment of the present disclosure, the information obtaining module comprises a pattern process obtaining unit, configured to: obtain pre-stored failure pattern types, and determine failure pattern detail information corresponding to each of the failure pattern types; generate the failure pattern information based on the failure pattern detail information of each of the failure pattern types; and obtain pre-stored defect process information; the defect process information comprising any one or a combination of a plurality of defect process types, defect process identifications, defect process patterns, and defect process positions.

[0022] In an example embodiment of the present disclosure, the graphic process acquisition unit comprises a graphic type acquisition subunit, configured to: determine a predefined failure graphic type, and store the failure graphic type into a failure graphic database; the failure graphic type comprises any one or a combination of a bit failure type, a word line failure type, a bit line failure type, a cross failure type, and a block failure type; the bit failure type comprises a single cell failure type, a double cell failure type, and a cluster cell failure type; the word line failure type comprises a single word line failure type and a multiple word line failure type; the bit line failure type comprises a single bit line failure type and a multiple bit line failure type; the cross failure type is formed by the word line failure type and the bit line failure type; and the block failure type comprises at least one failure area block.

[0023] In an example embodiment of the present disclosure, the defect process information comprises a target defect process; the failure type determination module comprises a failure type determination unit, configured to: determine a target defect process matched with a target wafer; and perform data screening processing on the failure chip information based on the failure graphic information and the target defect process, to obtain the failure graphic type.

[0024] In an example embodiment of the present disclosure, the failure graphic matching module comprises a failure graphic matching unit, configured to: one-to-one match the failure graphic position in each of the failure graphic types with the process defect position, to obtain a matching result; and take a failure graphic with a matching result of the failure graphic position matching the process defect position as a matching failure graphic.

[0025] In an example embodiment of the present disclosure, the failure graphic matching unit comprises a failure graphic matching subunit, configured to: when the failure graphic position matches the process defect position, acquire failure related information corresponding to the failure graphic position; determine a failure chip identifier based on the failure related information, and determine the matching failure graphic according to the failure chip identifier.

[0026] In an example embodiment of the present disclosure, the yield loss calculation module comprises a first data pair determination unit, configured to: acquire a process graphic data pair constituted by the defect process and the matching failure graphic; when one defect process corresponds to multiple matching failure graphics, screen out a matching failure graphic with a highest failure level from the multiple matching failure graphics as a target failure graphic; and generate the to-be-analyzed failure data pair based on the target failure graphic and the defect process.

[0027] In an example embodiment of the present disclosure, the yield loss calculation module further comprises a second data pair determination unit, configured to: when one of the matched failure patterns corresponds to multiple defect processes, randomly select one defect process from the multiple defect processes as a target defect process; and generate the failure data pair to be analyzed based on the target defect process and the matched failure pattern.

[0028] In an example embodiment of the present disclosure, the yield loss calculation module comprises a yield loss calculation unit, configured to: determine a total failure ratio based on the failure data pair to be analyzed; determine defect processes to be analyzed in the failure data pair to be analyzed, and determine a process matching ratio corresponding to each of the defect processes to be analyzed; and determine yield loss ratios corresponding to the defect processes to be analyzed based on the total failure ratio and the process matching ratios.

[0029] In an example embodiment of the present disclosure, the yield loss calculation unit comprises a failure ratio determination sub-unit, configured to: determine a total number of failed chips based on the failure data pair to be analyzed; obtain a number of process failed chips corresponding to each of the defect processes to be analyzed; and determine the process matching ratio based on the total number of failed chips and the number of process failed chips.

[0030] In an example embodiment of the present disclosure, the chip yield analysis apparatus further comprises a process correction module, configured to: obtain a preconfigured failure ratio threshold; determine defect processes with yield loss ratios greater than the failure ratio threshold as defect processes to be corrected; and perform process adjustment processing on the defect processes to be corrected.

[0031] According to a third aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory having computer readable instructions stored thereon, the computer readable instructions being executed by the processor to implement the chip yield analysis method according to any one of the above.

[0032] According to a fourth aspect of the present disclosure, a computer readable storage medium is provided, having a computer program stored thereon, the computer program being executed by a processor to implement the chip yield analysis method according to any one of the above.

[0033] The technical solutions provided by the present disclosure can have the following beneficial effects:

[0034] The chip yield analysis method in the exemplary embodiments of the present disclosure, on one hand, determines the yield loss proportion by matching the defect process with the yield loss pattern, which can quickly quantitatively analyze the yield loss caused by each process defect. On the other hand, by calculating the yield loss proportion, the loss degree of the yield caused by the increase of a certain process defect can be predicted in advance. The yield loss proportion can be used to determine whether the defect process needs to be adjusted and corrected to improve the chip yield.

[0035] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and are not limiting to the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0036] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. It is readily apparent to one skilled in the art that the following description in the drawings is only some embodiments of the present disclosure, and other drawings can be obtained from these drawings without creative labor. In the drawings:

[0037] Figure 1 A flowchart of a chip yield analysis method according to an exemplary embodiment of the present disclosure is schematically shown;

[0038] Figure 2 A system diagram for bidirectional analysis of yield loss and process defects according to an exemplary embodiment of the present disclosure is schematically shown;

[0039] Figure 3 A flowchart of bidirectional analysis of yield loss and process defects according to an exemplary embodiment of the present disclosure is schematically shown;

[0040] Figure 4 A test result diagram obtained after functional testing of a wafer according to an exemplary embodiment of the present disclosure is schematically shown;

[0041] Figure 5 An interface diagram for obtaining relevant data in a chip yield analysis scheme from a database according to an exemplary embodiment of the present disclosure is schematically shown;

[0042] Figure 6 A result diagram for determining the pattern and type of a defect process according to an exemplary embodiment of the present disclosure is schematically shown;

[0043] Figures 7(a)-7(e) A detail diagram of a failure pattern type according to an exemplary embodiment of the present disclosure is schematically shown;

[0044] Figure 8A schematic diagram illustrating a defect location overlaid with a yield failure pattern according to an example embodiment of the present disclosure is shown schematically;

[0045] Figure 9 A diagram illustrating a positional relationship between a defect process location and a failed chip according to an example embodiment of the present disclosure is shown schematically;

[0046] Figure 10 A flowchart illustrating a process of predicting a yield loss ratio caused by a newly added defect using a bidirectional analysis system according to an example embodiment of the present disclosure is shown schematically;

[0047] Figure 11 A block diagram of a chip yield analysis device according to an example embodiment of the present disclosure is shown schematically;

[0048] Figure 12 A block diagram of an electronic device according to an example embodiment of the present disclosure is shown schematically;

[0049] Figure 13 A diagram of a computer readable storage medium according to an example embodiment of the present disclosure is shown schematically. DETAILED DESCRIPTION

[0050] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views.

[0051] Moreover, described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the disclosure.

[0052] The block diagrams in the drawings show functions and functionality as they can be implemented in software / firmware. In other words, the block diagrams show a function specified in software or firmware. Should the software / firmware be implemented in software / firmware, the software / firmware can be stored in a memory such as, for example, RAM memory, flash memory, a hard disk, or the like. The block diagrams in the drawings show functions and functionality as they can be implemented in software / firmware. In other words, the block diagrams show a function specified in software or firmware. Should the software / firmware be implemented in software / firmware, the software / firmware can be stored in a memory such as, for example, RAM memory, flash memory, a hard disk, or the like.

[0053] Currently, the analysis scheme for the influence of process on chip yield is to determine the correlation between the two by using whether the defect position and the yield failure pattern overlap. However, the above scheme cannot quantify the loss caused by process defects to the yield.

[0054] Based on this, in the present example embodiment, a chip yield analysis method is first provided. The chip yield analysis method of the present disclosure can be implemented by a server, or the method of the present disclosure can be implemented by a terminal device. The terminal described in the present disclosure can include mobile terminals such as mobile phones, tablet computers, notebook computers, palmtop computers, personal digital assistants (PDA), portable media players (PMP), navigation devices, wearable devices, smart bracelets, pedometers, and the like, as well as fixed terminals such as desktop computers. Figure 1 A schematic diagram of a chip yield analysis method flow according to some embodiments of the present disclosure is schematically shown. Referring to Figure 1 The chip yield analysis method can include the following steps:

[0055] In step S110, failure chip information obtained based on chip testing is acquired, and pre-stored failure pattern information and defect process information are acquired.

[0056] According to some example embodiments of the present disclosure, chip testing can be a processing procedure according to the test requirements of functional elements themselves. The failure chip can be a chip that is determined to be failed after chip testing. The failure chip information can be related information of the failure chip determined after chip testing. The failure pattern information can be related information of all possible patterns corresponding to the failure chip. The defect process information can be related information of the process with defects.

[0057] In the process of semiconductor production and manufacturing, chip testing can be performed on the target wafer to determine the failure chip information of the test failure from the target wafer. Referring to Figure 2 , Figure 2 A system diagram for bidirectional analysis of yield loss and process defects in an example embodiment of the present disclosure is schematically shown. Figure 2 In the present embodiment, the data obtained after chip testing can be stored in a chip database (bin database) 210. The bin database stores process-related information, including, for example, site information, machine information, chamber information, and electrical and physical information obtained after different types of testing. Therefore, the failure chip information can be obtained from the bin database.

[0058] In addition, the failure pattern information corresponding to the failed chip and the defect process information that can cause the chip failure can be obtained from a failure pattern database (e.g., FSA database) 220 and a defect process database (DEF database) 230, respectively. The DEF database stores information about defect sites and defects as a data basis for subsequent chip yield analysis.

[0059] At step S120, data screening processing is performed on the failed chip information based on the failure pattern information and the defect process information to obtain a failure pattern type corresponding to the failed chip.

[0060] According to some example embodiments of the present disclosure, the data screening processing can be a failure pattern type related to the failed chip screened from the failure pattern information and the defect process information. The failure pattern type can be a specific type of the failure pattern contained in the failed chip.

[0061] Continuing to refer to Figure 2 After obtaining the above information, the failed chip information obtained from the chip database 210, the failure pattern information obtained from the failure pattern database 220, and the defect process information obtained from the defect process database 230 can all be input into the data screening module 230 to perform data screening processing on the failed chip information to determine the failure pattern type corresponding to the failed chip.

[0062] At step S130, position matching processing is performed on the failure pattern position in the failure pattern type and the process defect position to obtain a matched failure pattern.

[0063] According to some example embodiments of the present disclosure, the failure pattern position can be a specific position of the failure pattern position in the yield failure area. The process defect position can be a specific position of the defect process in the yield failure area. The position matching processing can be a process of determining whether the failure pattern position and the process defect position match in the yield failure area. The matched failure pattern can be a failure pattern whose failure pattern position and process defect position are consistent.

[0064] Continuing to refer to Figure 2After the failure pattern type corresponding to the failed chip is determined by the data screening module 240, the matched failure pattern type can be further input into the yield failure pattern / defect process matching module 250 for matching processing of the yield failure pattern (FSA) and the defect process (DEF), and the FSA failure position with killing effect in the failure pattern type and the defect position of each DEF are matched one by one. If the positions of the two are matched, the matched failure pattern matched with the defect process position can be obtained. For example, the bin item, chip ID, matched failure pattern, defect layer, and defect ID, etc. can be automatically displayed in the visualization interface.

[0065] In step S140, the matched failure pattern corresponding to the to-be-analyzed failure data pair is determined, yield loss calculation is performed based on the to-be-analyzed failure data pair, and the yield loss ratio corresponding to each defect process is obtained.

[0066] According to some example embodiments of the present disclosure, the to-be-analyzed failure data pair can be a data pair composed of a matched failure pattern and a corresponding defect process. The yield loss calculation can be a specific calculation process for determining the yield loss ratio of a chip caused by a defect process. The defect process can be a process with defects. The yield loss ratio can be the proportion of chip failure caused by the defect process.

[0067] Since different processes will cause different types of failure patterns FSA, after the matched failure pattern is determined, the defect process corresponding to the matched failure pattern can be further determined, and the to-be-analyzed failure data pair can be generated. Referring to Figure 2 After the matched failure pattern is obtained, the to-be-analyzed failure data pair corresponding to the matched failure pattern can be determined by the screening rule in the yield failure pattern / defect process matching data screening module 260.

[0068] After the to-be-analyzed failure data pair is obtained, yield loss calculation can be performed based on the to-be-analyzed failure data pair, and the yield loss ratio corresponding to each defect process is obtained. For example, the yield loss ratio caused by each defect process can be calculated according to the total yield loss corresponding to all defect processes and the proportion of the number of chips caused by each defect process in the failed chips.

[0069] According to the chip yield analysis method in the example embodiment, on one hand, the yield loss proportion is determined by whether the defect process matches the yield loss pattern, so that the yield loss caused by each process defect can be quickly quantitatively analyzed. On the other hand, the yield loss caused by the increase of a certain process defect can be predicted in advance by calculating the yield loss proportion, and the yield loss proportion can be used to determine whether the defect process needs to be adjusted and corrected to improve the chip yield.

[0070] In the following, the chip yield analysis method in the example embodiment will be further described.

[0071] In an example embodiment of the disclosure, for step S110, the failure chip information obtained based on the chip test includes: obtaining a chip test result based on a function test; obtaining a target wafer based on the chip test result, the target wafer including a failure shape wafer with process site data greater than a preset number; obtaining a failure chip identifier and chip position information of the failure chip based on the target wafer; and generating the failure chip information based on the failure chip identifier and the failure position information.

[0072] The function test can be a verification of each function of the chip, and each function is tested according to the function test case to check whether the product meets the user's required function. The chip test result can be a specific result obtained after the function test of the chip. The target wafer can be a wafer used for bidirectional analysis and processing of defect processes and failure yield. The failure shape can be a specific shape corresponding to the failure chip in the failure pattern area of the target wafer. The process site data can be related information data of the site where the process is located. The failure chip identifier can be a unique identifier corresponding to the chip with a failure result after the function test. The position information of the failure chip can be related information of the specific position of the failure pattern in the failure area.

[0073] Reference Figure 3 , Figure 3 A flowchart for bidirectional analysis of yield loss and process defects according to an example embodiment of the disclosure is schematically shown. In step S301, a target wafer is obtained. Before obtaining the target wafer, a batch of wafers can be functionally tested according to a function test case to obtain a chip test result. Reference Figure 4 , Figure 4 A test result diagram obtained after a wafer is functionally tested according to an example embodiment of the disclosure is schematically shown. As can be seen from Figure 4 , there can be a failure chip on the wafer after the function test.

[0074] After the functional test is completed, the wafers that meet the following conditions can be selected as target wafers from the chip test results according to the process requirements, including: the product yield is slightly higher than the product yield average, there is no special failure functional test pattern, and the wafer has more than 20 process defects, and further more than 40 process defects, to match all DEF sites. These target wafers can represent the average situation of the current process, so as to better find the yield loss ratio corresponding to each defect process.

[0075] Reference Figure 5 , Figure 5 An interface diagram for obtaining relevant data in a chip yield analysis scheme from a database in an example embodiment according to the present disclosure is schematically shown. Since each wafer has a corresponding unique identifier, the corresponding wafer identifier (wafer ID) can be input through the visual interface. After obtaining the target wafer, the failure chip identifier (Fail chip ID) and chip position information of each failure chip in each target wafer can be obtained according to the target wafer, i.e. the unique identifier of each failure chip and the specific position in the corresponding target wafer. After obtaining the failure chip identifier and failure position information, the failure chip information of the failure chip can be generated based on the failure chip identifier and failure position information as the data basis for defect process and failure yield analysis.

[0076] In an example embodiment of the present disclosure, for step S110, the pre-stored failure pattern information and defect process information are obtained, including: obtaining pre-stored failure pattern types, determining failure pattern detail information corresponding to each failure pattern type; generating failure pattern information based on the failure pattern detail information of each failure pattern type; obtaining pre-stored defect process information; the defect process information includes any one or a combination of more than one of defect process type, defect process identifier, defect process pattern, and defect process position.

[0077] Wherein, the failure pattern detail information can be information composed of pattern description information and specific illustrations corresponding to each failure pattern type. The failure pattern information can be specific information corresponding to each failure pattern type. The defect process type can be the specific type of the defect process. The defect process identifier can be the unique identifier corresponding to the defect process. The defect process position can be the specific position of the defect process in the failure pattern area.

[0078] Continuing to refer to Figure 3In step S302, failure pattern information is acquired. Failure pattern types are acquired in advance, such as selecting FSAs that cause chip failure (i.e., are lethal) from a pre-configured FSA database as failure pattern types. For example, failure pattern types that cause chip failure can include Bit, Single / Multi WL / BL, cross, block type, and the like. After the above failure pattern types are acquired, failure pattern detail information corresponding to each failure pattern type can be determined. The failure pattern detail information can generally include type name, type code, pattern distribution example, pattern description information, location, and the like for each failure pattern type. After the failure pattern detail information for all failure pattern types is acquired, failure pattern information can be generated based on the failure pattern detail information for each failure pattern type. The data basis for subsequent matching is performed.

[0079] In step S303, defect process information is acquired. Defect process information is acquired in advance from a pre-configured defect process (Defect, DEF) database. For example, the defect process information can include any one or a combination of defect process type (Defect class), defect process identification (Defect ID), defect process pattern (DEF image), and defect process location, which can include detailed information of a specific site where the process is located. Figure 6 , Figure 6 A result map showing the determined pattern and type of defect process according to an example embodiment of the present disclosure is schematically shown. The defect process information acquired from the DEF database is shown in detail in Figure 6 By the above steps, the acquired failure pattern information and defect process information can be used as the data basis for subsequent yield analysis.

[0080] In an example embodiment of the present disclosure, the pre-stored failure pattern types are acquired by determining pre-defined failure pattern types and storing the failure pattern types to a failure pattern database. The failure pattern types include any one or a combination of Bit failure type, Wordline failure type, Bitline failure type, Cross failure type, and Block failure type. The Bit failure type includes single cell failure type, double cell failure type, and cluster cell failure type. The Wordline failure type includes single wordline failure type and multi wordline failure type. The Bitline failure type includes single bitline failure type and multi bitline failure type. The Cross failure type is formed by the intersection of the Wordline failure type and the Bitline failure type. The Block failure type is formed by at least one failure area block.

[0081] The failure pattern database can be a database for storing all failure patterns. The bit type can be a failure type caused by one or more bit errors. The word line type (WL Type) can be a failure type caused by a word line error. The bit line type (BL Type) can be a failure type caused by a bit line error. The cross type (Cross Type) can be a failure type caused by a cross word line and bit line error. The block type (Block Type) can be a failure type formed by a piece of failed chip. The failure region block (blockType) can be a region position where the failed chip is located.

[0082] Referring to FIG. 7, FIG. 7 schematically shows a detail diagram of a failure pattern type according to an example embodiment of the present disclosure. In FIG. 7(a), a cell failure type and a cluster failure type are shown, including the definition of the failure type, failure type coding, pattern description, diagram details, and the position where it is located, etc. The cell failure type can be a single bit or multiple bits randomly distributed in a bank or a segment in a chip. For example, the cell failure type can include a single cell failure type, i.e., a single bit cell failure (SBIT), a double cell failure type, i.e., a two-bit cell failure (DBIT), and the failed cells are randomly distributed in the bank.

[0083] In addition, the cluster failure type, i.e., a multiple cell failure (Cluster Bit), can refer to multiple failed cells gathered together to form a whole block of failed cell region, as shown in the element details of the first row of FIG. 7(a). The distribution area of the cluster cell failure type can be randomly distributed among multiple bits, which can or can not have the characteristics of cluster aggregation.

[0084] In FIG. 7(b), a bit line failure type is shown, which can include a unit line failure type (single WL failure) and a multiple bit line failure type (multiple WL failure). The unit line failure type can be a failure type in which only one bit line (BL) is failed, and the length of the bit line can be equal to the length of a bank or a segment.

[0085] In FIG. 7(c), a word line failure type is shown, which includes a single word line failure type (single BL failure) and a multiple word line failure type (multiple BL failure).

[0086] In FIG. 7(d), a cross failure type is shown, which is a failure type formed by the intersection of a multiple word line failure type and a bit line failure type.

[0087] The block failure type is shown in FIG. 7(e). One or more array failures, in which multiple bits fail and have an aggregated feature, thus forming a corresponding block failure type.

[0088] Among the above-mentioned various failure pattern types, each of the failure types Cluster Bit, Multi WL / BL, cross, and block type has a killing effect, and the killing effect of the failure pattern on the chip failure is ranked as follows: Block > Cross > Multi BL / WL > Cluster bit.

[0089] Through the above steps, the specific type of the failure pattern type, the detailed description information of each FSA type, and the killing effect of different types of FSA on the chip failure are defined in advance, which facilitates subsequent determination of the to-be-analyzed data pair.

[0090] In an exemplary embodiment of the present disclosure, for step S120, based on the failure pattern information and the defect process information, the failure chip information is subjected to data screening processing to obtain the failure pattern type corresponding to the failure chip, including: determining a target defect process matched with the target wafer; based on the failure pattern information and the target defect process, the failure chip information is subjected to data screening processing to obtain the failure pattern type.

[0091] The target defect process can be a defect process matched with the failure chip in the target wafer.

[0092] After obtaining the relevant data for chip yield analysis, continuing to refer to Figure 3 In step S304, a single FSA is matched with defects of different processes, and the defect information overlapping with the FSA region is counted. Specifically, the target defect process matched with the target wafer is first determined. For example, in the data acquisition step, multiple wafers can be acquired, and multiple different types of defect processes are stored in the DEF database. In order to improve the efficiency of subsequent data analysis, for each target wafer, the target defect process matched with each target wafer can be determined, i.e., the defect process that causes the target wafer to produce chip failure.

[0093] For example, the target wafer identifier (wafer ID) is input through the visual interface. The target wafer can be a wafer that has no special failure shape and has more than a DEF number threshold (such as 40 DEF sites) data in the wafer. In addition, all defect process sites to be matched are selected on the visual interface, and the failure pattern (such as the failure Merge Bin in Region A / B / C / D) obtained after functional testing is selected. After inputting the above data, the system will automatically screen out the FSA type with a killing effect as the failure pattern type.

[0094] After the target defect process matching the target wafer is determined, the failure chip information in the target wafer can be data filtered based on the failure pattern information contained in the target wafer and the target defect process, so as to determine the failure pattern type in the target wafer related to the target defect process, that is, to determine the failure pattern type contained in the target wafer. If no failure pattern related to the target defect process is filtered through the data filtering step, no data result is obtained in step S305. Through the above steps, the relevant failure pattern for performing the defect process and chip yield correlation analysis can be determined.

[0095] In an exemplary embodiment of the present disclosure, for step S130, the position matching process of the failure pattern position in the failure pattern type and the process defect position is performed to obtain the matched failure pattern, including: matching the failure pattern position in each failure pattern type with the process defect position one by one to obtain the matching result; and taking the failure pattern whose matching result is that the failure pattern position matches the process defect position as the matched failure pattern.

[0096] The matching result can be the result obtained after the position matching of the failure pattern position and the process defect position.

[0097] Since there are many factors that can cause chip failure, it can be caused by defect process or other production factors. When the position of the defect process and the chip failure coincide, it can be considered that the failure chip is related to the overlapped defect process. Therefore, in order to determine the failure chip caused by the defect process, after the failure pattern type matching the target wafer is obtained, a data filtering matching operation can be further performed, which continues to refer to Figure 3 In step S306, unreasonable data is removed through data filtering matching.

[0098] Specifically, after the failure pattern type contained in the target wafer is filtered, the failure pattern position in each failure pattern type is matched with the process defect position one by one, whether the failure pattern position and the process defect position coincide is determined, and the matching result of the two is obtained. If the matching result shows that the failure pattern position matches the process defect position, such failure pattern is taken as the matched failure pattern. If the matching result shows that the two positions do not match, the data of the failure pattern is removed. Through the above processing steps, the matched failure pattern coinciding with the defect process position can be determined, which is taken as the chip yield failure rate caused by the defect process.

[0099] In an example embodiment of the present disclosure, the matching result of the failure pattern matched with the process defect position is taken as the matching failure pattern, including: when the failure pattern position matches the process defect position, obtaining failure-related information corresponding to the failure pattern position; determining a failure chip identifier based on the failure-related information, and determining the matching failure pattern according to the failure chip identifier.

[0100] The failure chip identifier can be a unique identifier of the failure chip.

[0101] For the failure pattern in the target wafer and the defect process matched with the target wafer, the position matching processing can be performed on both of them. Referring to Figure 8 , Figure 8 An example schematic diagram of the overlap of the defect position and the yield failure pattern is schematically shown in an example embodiment of the present disclosure. Figure 8 The left side in the example can represent the case that the defect process position overlaps with the yield failure area, for example, the yield failure pattern and the process defect overlap together. Figure 8 The right side in the example can be the case that the defect process position does not overlap with the yield failure area, for example, the yield failure pattern and the process defect deviate and are located above the yield failure pattern.

[0102] For Figure 8 In the case that the defect process position overlaps with the yield failure area, the failure-related information corresponding to the failure pattern position can be obtained, for example, the matching failure chip identifier, failure detail information and other failure-related information can be obtained based on the failure pattern position. After obtaining the failure-related information, the failure chip identifier is obtained from the failure-related information to determine the matching failure pattern corresponding to the failure chip identifier, which is used as the data basis for subsequent calculation of chip yield loss.

[0103] In an example embodiment of the present disclosure, for step S140, the matching failure pattern corresponding to the to-be-analyzed failure data pair is determined, including: obtaining the process pattern data pair formed by the defect process and the matching failure pattern; when a defect process corresponds to multiple matching failure patterns, the matching failure pattern with the highest failure level is selected from the multiple matching failure patterns as the target failure pattern; and generating the to-be-analyzed failure data pair based on the target failure pattern and the defect process.

[0104] The target failure pattern can be the matching failure pattern with the highest failure level matched with the defect process position.

[0105] After the matched failure pattern is determined, a to-be-analyzed data pair for chip yield analysis can be further generated based on the matched failure pattern. Specifically, first, a process pattern data pair composed of a defect process and the matched failure pattern is obtained, and the process pattern data pair can be a data pair composed of the defect process and the matched failure pattern that are positionally coincident. After the process pattern data pair is obtained, a corresponding relationship between the defect process and the matched failure pattern can be obtained, and the corresponding relationship between the two can include one-to-many, many-to-one, and the like. When the one-to-one corresponding relationship does not exist between the defect process and the matched failure pattern, data screening processing is required to be performed on the process pattern data pair according to a screening rule, and a reasonable matching result is retained.

[0106] With reference to the foregoing Figure 3 In step S307, it is determined whether one defect process (DEF) matches multiple matched failure patterns (FSA). For example, when one defect process corresponds to multiple matched failure patterns, the matched failure pattern with the highest failure level is screened out from the multiple matched failure patterns as a target failure pattern. That is, in step S308, at most one FSA is retained. Taking site 1 as an example, if the defect process of the site matches four matched failure patterns (FSAtype) of Cross, BL, WL, and Cluster Bit that are positionally coincident, the matched failure pattern should only retain the reasonable and most damaging FSA to chip failure, i.e., the Cross type, as the target failure pattern. After the target failure pattern matched with the defect process is determined, a to-be-analyzed failure data pair can be generated based on the target failure pattern and the defect process. For example, the two can be stored in a key-value pair data format, and can also be stored in other data formats. After the to-be-analyzed failure data pair is obtained through the foregoing steps, it is used for subsequent yield failure ratio calculation.

[0107] In an exemplary embodiment of the present disclosure, determining the to-be-analyzed failure data pair corresponding to the matched failure pattern further includes: when one matched failure pattern corresponds to multiple defect processes, randomly selecting one defect process from the multiple defect processes as a target defect process; and generating the to-be-analyzed failure data pair based on the target defect process and the matched failure pattern.

[0108] The target defect process can be a defect process that matches the target failure pattern and meets a specific condition.

[0109] When the one-to-one corresponding relationship does not exist between the defect process and the matched failure pattern, there is also a case where one matched failure pattern corresponds to multiple defect processes. With reference to the foregoing Figure 3For the obtained process pattern data pair, if one matched failure pattern (FSA) corresponds to multiple defect processes (DEF) in step S309, at least one DEF site is reserved, for example, a defect process is randomly selected from the multiple defect processes as a target defect process in step S310. Taking a word line failure pattern type (WL FSA) as an example, if three DEF sites such as site 1, site 2, and site 3 are matched at the same time, only site 1 should be reserved.

[0110] After determining the target defect process corresponding to the matched failure pattern, a to-be-analyzed failure data pair can be generated based on the target defect process and the matched failure pattern. The storage manner of the to-be-analyzed failure data pair has been described in the above embodiment, which will not be described here again. Through the above steps, data screening can also be performed on the case that one matched failure pattern corresponds to multiple defect processes, and a to-be-analyzed failure data pair used for yield analysis calculation is obtained.

[0111] In an exemplary embodiment of the present disclosure, for step S140, yield loss calculation is performed based on the to-be-analyzed failure data pair to obtain a yield loss ratio corresponding to each defect process, including: determining a total failure ratio according to the to-be-analyzed failure data pair; determining a to-be-analyzed defect process contained in the to-be-analyzed failure data pair, and determining a process matching ratio corresponding to each to-be-analyzed defect process; and determining a yield loss ratio corresponding to multiple to-be-analyzed defect processes according to the total failure ratio and each process matching ratio.

[0112] Among them, the total failure ratio can be the chip failure ratio caused by all defect processes. The to-be-analyzed defect process can be a defect process used for chip yield analysis. The process matching ratio can be the ratio of each type of defect process causing chip failure.

[0113] After obtaining the to-be-analyzed failure data pair, the yield loss ratio calculation process can be performed, continuing to refer to Figure 3 In step S311, the number of different types of defect processes DEF of different sites matched is counted, and the proportion and the total yield loss related to the defect process DEF are counted, that is, the total failure ratio is determined according to the to-be-analyzed failure data pair. Since the defect process DEF randomly falls on the wafer chip, not every defect process DEF will cause chip failure, so there is a failure ratio, therefore, the total failure ratio of the chip failure caused by all defect processes can be calculated first. Referring to Figure 9 , Figure 9 A schematic diagram of the positional relationship between the defect process position and the failed chip is shown according to the exemplary embodiment of the present disclosure. The positions of the failed chip and the defect process may or may not coincide.

[0114] In step S312, the yield loss proportion caused by different defect processes is calculated. Before the yield loss proportion is calculated, the defect processes to be analyzed included in the data pair to be analyzed can be determined. The data pair to be analyzed can include multiple different types of defect processes. For each determined defect process to be analyzed, the proportion of each defect process to be analyzed in the total data pair to be analyzed, i.e., the process matching proportion, can be determined. Specifically, the process matching proportion can be calculated according to formula 1.

[0115] Process matching proportion = target type defect process matching number / all defect process matching number x 100%

[0116] (Formula 1)

[0117] After the process matching proportion of each defect process is calculated, the yield loss proportion corresponding to multiple defect processes to be analyzed can be determined according to the total failure proportion and the process matching proportion. For example, the yield failure proportion can be calculated according to formula 2.

[0118] Yield loss proportion of different defect processes = total yield loss related to defect processes x process matching proportion of different defect processes (Formula 2)

[0119] For example, if the total yield loss related to the defect process DEF is 10%, and the total number of different types of DEF matching is 100. For example, layer1 / Class1 type DEF matches 40, then the process matching proportion of layer1 / Class1 type defect process = 40 / 100 x 100% = 40%. Therefore, the yield loss proportion caused by layer1 / Class1 type defect process = 10% x 40% = 4%.

[0120] Through the above calculation steps, the yield loss proportion caused by each defect process can be determined, so that subsequent processing such as process improvement operation of the defect process can be determined according to the yield failure proportion to accurately improve the defect process that causes greater loss to the yield.

[0121] In an exemplary embodiment of the present disclosure, determining the process matching proportion corresponding to each defect process to be analyzed includes: determining the total number of failed chips based on the failure data pair to be analyzed; obtaining the number of process failed chips corresponding to each defect process to be analyzed; and determining the process matching proportion based on the total number of failed chips and the number of process failed chips.

[0122] The total number of failed chips can be the number of all failed chips in the target wafer. The number of process failed chips can be the number of failed chips caused by a defect process.

[0123] The process matching ratio can be calculated by the following steps: determining the total number of failed chips based on the failure data to be analyzed, i.e., determining the total number of failed chips caused by the defect process. Since there can be multiple different defect processes causing the chips on the wafer to fail, after determining the total number of failed chips, the number of failed chips corresponding to each process to be analyzed can be obtained. For example, the total number of failed chips in a wafer is 100, and the defect process corresponding to the wafer includes four types, so the number of failed chips caused by each of the four defect processes, i.e., the number of process failed chips, can be determined. After determining the number of failed chips caused by each defect process, the process matching ratio is determined based on the total number of failed chips and the number of process failed chips. For example, the number of failed chips corresponding to defect process 1 is 30, so the process matching ratio corresponding to defect process 1 is 0.3. The calculated process matching ratio is used in the subsequent yield loss ratio calculation process.

[0124] Reference Figure 10 , Figure 10 A flowchart for predicting the yield loss ratio caused by a newly added defect using a bidirectional analysis system in an exemplary embodiment according to the present disclosure is schematically shown. In step S1001, a wafer with defect process DEF data is selected. In step S1002, the chip test type (Bin item) and the failed chip identification (chip ID) of the wafer with defect process DEF are counted. In step S1003, a failed chip bin is selected and a reasonable matching failure pattern FSA is matched. In step S1004, it is determined whether the defect process DEF matches the matching failure pattern FSA and its type. If the defect process DEF does not match the matching failure pattern FSA, the process ends in step S1005, and it is predicted that the process defect will not cause yield loss. If the defect process DEF matches the matching failure pattern FSA, unreasonable data is removed in step S1006. In step S1007, the number of defect processes DEF matching the reasonable matching failure pattern FSA is counted. In step S1008, the defect process failure ratio and the chip number ratio of the defect process are calculated. In step S1009, the yield loss caused by the addition of the defect process on line is predicted; wherein the yield loss = defect process failure ratio x chip number ratio of the defect process. After calculating the yield loss, if the yield loss is large, the defect process needs to be improved in priority.

[0125] In this embodiment, the calculation process of the yield loss ratio will be described with an example. For example, if the added failure type DEF falls on 50 chips, and the product has a total of 1000 chips, the ratio corresponding to the defect process is 50 / 1000 x 100% = 5%.

[0126] In addition, for the failure ratio, if the matched wafer has 100 chips with the same failure type of process defects, and 50 of the DEFs are matched to the FSA, the failure ratio is 50 / 100 x 100% = 50%. According to the above calculation, the ratio of yield loss is obtained, i.e., loss = the number of chips with DEFs / total number of chips x calculated failure ratio = 5% x 50% = 2.5%.

[0127] In an exemplary embodiment of the present disclosure, a pre-configured failure ratio threshold is obtained; a defect process with a yield loss ratio greater than the failure ratio threshold is regarded as a process to be corrected; and a process adjustment process is performed on the process to be corrected.

[0128] The failure ratio threshold can be a specific value for comparison with the process matching ratio. The process to be corrected can be a defect process that needs to be adjusted.

[0129] After calculating the yield loss ratio caused by different defect processes, the yield loss ratio of each defect process can be compared with the failure ratio threshold respectively, and the defect process with a yield loss ratio greater than the failure ratio threshold is regarded as a process to be corrected. These processes to be corrected can be considered as defect processes that have a greater impact on chip yield. Therefore, in order to improve chip yield, the process to be corrected needs to be adjusted to reduce the impact of such defect processes on chip yield. For example, through the above calculation, it is found that the yield loss of layer1 / Class1 type DEF is large, therefore, yield improvement needs to be performed on this process first to reduce the impact of such defect processes on chip yield.

[0130] In summary, the chip yield analysis method of the present disclosure obtains failure chip information based on chip testing, and obtains pre-stored failure pattern information and defect process information; based on the failure pattern information and the defect process information, the failure chip information is subjected to data screening processing to obtain a failure pattern type corresponding to the failure chip; the failure pattern position in the failure pattern type and the process defect position are subjected to position matching processing to obtain a matching failure pattern that is position-matched; a to-be-analyzed failure data pair corresponding to the matching failure pattern is determined, yield loss calculation is performed based on the to-be-analyzed failure data pair, and a yield loss ratio corresponding to each defect process is obtained. On the one hand, the yield loss ratio is determined by whether the defect process and the yield loss pattern match, which can quickly quantify and analyze the yield loss caused by each process defect. On the other hand, by calculating the yield loss ratio, the loss degree of the yield caused by the increase of a certain process defect can be predicted in advance, and the yield loss ratio can be used to determine whether the defect process needs to be adjusted and corrected to improve the chip yield. On the other hand, by adjusting and improving the defect process that causes the yield loss ratio to be greater than a loss ratio threshold, the proportion of failure chips caused by the defect process can be reduced, and the chip yield can be effectively improved.

[0131] It should be noted that although the steps of the method in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired result. In addition or alternatively, some steps can be omitted, a plurality of steps can be combined into one step, and / or one step can be divided into a plurality of steps, etc.

[0132] In addition, in the present example embodiment, a chip yield analysis device is also provided. Referring to Figure 11 The chip yield analysis device 1100 can include an information acquisition module 1110, a failure type determination module 1120, a failure pattern matching module 1130, and a yield loss calculation module 1140.

[0133] Specifically, the information acquisition module 1110 is configured to obtain failure chip information based on chip testing, and obtain pre-stored failure pattern information and defect process information; the failure type determination module 1120 is configured to, based on the failure pattern information and the defect process information, perform data screening processing on the failure chip information to obtain a failure pattern type corresponding to the failure chip; the failure pattern matching module 1130 is configured to perform position matching processing on a failure pattern position in the failure pattern type and a process defect position to obtain a matching failure pattern that is position-matched; and the yield loss calculation module 1140 is configured to determine a to-be-analyzed failure data pair corresponding to the matching failure pattern, perform yield loss calculation based on the to-be-analyzed failure data pair, and obtain a yield loss ratio corresponding to each defect process.

[0134] In an example embodiment of the present disclosure, the chip testing includes a function test; the information acquisition module 1110 includes a failure information acquisition module, configured to: acquire a chip test result based on the function test; acquire a target wafer based on the chip test result, the target wafer including a wafer with a failure shape and process station data greater than a preset number; acquire a failure chip identifier and chip position information of a failure chip based on the target wafer; and generate failure chip information based on the failure chip identifier and the failure position information.

[0135] In an example embodiment of the present disclosure, the information acquisition module 1110 includes a graphic process acquisition unit, configured to: acquire a pre-stored failure graphic type, determine failure graphic detail information corresponding to each failure graphic type, generate failure graphic information based on the failure graphic detail information of each failure graphic type, and acquire pre-stored defect process information; the defect process information includes any one or a combination of defect process types, defect process identifiers, defect process graphics, and defect process positions.

[0136] In an example embodiment of the present disclosure, the graphic process acquisition unit includes a graphic type acquisition subunit, configured to: determine a pre-defined failure graphic type, and store the failure graphic type to a failure graphic database; the failure graphic type includes any one or a combination of a bit failure type, a word line failure type, a bit line failure type, a cross failure type, and a block failure type; the bit failure type includes a single cell failure type, a double cell failure type, and a cluster cell failure type; the word line failure type includes a single word line failure type and a multi-word line failure type; the bit line failure type includes a single bit line failure type and a multi-bit line failure type; the cross failure type is formed by the intersection of the word line failure type and the bit line failure type; and the block failure type is composed of at least one failure area block.

[0137] In an example embodiment of the present disclosure, the defect process information includes a target defect process; the failure type determination module includes a failure type determination unit, configured to: determine a target defect process matched with the target wafer; and perform data screening processing on the failure chip information based on the failure graphic information and the target defect process to obtain a failure graphic type.

[0138] In an example embodiment of the present disclosure, the failure graphic matching module includes a failure graphic matching unit, configured to: one-to-one match the failure graphic position in each failure graphic type with the process defect position respectively to obtain a matching result; and take a failure graphic with a matching result of matching the failure graphic position with the process defect position as a matching failure graphic.

[0139] In an example embodiment of the present disclosure, the failed pattern matching unit comprises a failed pattern matching subunit, configured to: when the failed pattern position matches the process defect position, acquire failed-related information corresponding to the failed pattern position; determine a failed chip identifier based on the failed-related information, and determine a matching failed pattern according to the failed chip identifier.

[0140] In an example embodiment of the present disclosure, the yield loss calculation module 1140 comprises a first data pair determination unit, configured to: acquire process pattern data pairs formed by the defect process and the matching failed pattern; when one defect process corresponds to multiple matching failed patterns, filter out a matching failed pattern with the highest failed level from the multiple matching failed patterns as a target failed pattern; and generate a failed data pair to be analyzed based on the target failed pattern and the defect process.

[0141] In an example embodiment of the present disclosure, the yield loss calculation module 1140 further comprises a second data pair determination unit, configured to: when one matching failed pattern corresponds to multiple defect processes, randomly select a defect process from the multiple defect processes as a target defect process; and generate a failed data pair to be analyzed based on the target defect process and the matching failed pattern.

[0142] In an example embodiment of the present disclosure, the yield loss calculation module 1140 comprises a yield loss calculation unit, configured to: determine a total failed proportion according to the failed data pair to be analyzed; determine a defect process to be analyzed in the failed data pair to be analyzed, and determine a process matching proportion corresponding to each defect process to be analyzed; and determine yield loss proportions corresponding to multiple defect processes to be analyzed according to the total failed proportion and the process matching proportion.

[0143] In an example embodiment of the present disclosure, the yield loss calculation unit comprises a failed proportion determination subunit, configured to: determine a total number of failed chips based on the failed data pair to be analyzed; acquire a number of process failed chips corresponding to each defect process to be analyzed; and determine the process matching proportion based on the total number of failed chips and the number of process failed chips.

[0144] In an example embodiment of the present disclosure, the chip yield analysis device 1100 further comprises a process correction module, configured to: acquire a preconfigured failed proportion threshold value; determine a defect process to be corrected as a defect process with a yield loss proportion greater than the failed proportion threshold value; and perform process adjustment processing on the defect process to be corrected.

[0145] The specific details of the virtual modules of the chip yield analysis devices in the above embodiments have been described in detail in the corresponding chip yield analysis methods, and thus will not be described here again.

[0146] It should be noted that although several modules or units of the chip yield analysis apparatus are mentioned in the foregoing detailed description, such division is not mandatory. In fact, according to the embodiments of the present disclosure, features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, features and functions of one module or unit described above can be further divided into embodied by multiple modules or units.

[0147] Furthermore, in the exemplary embodiments of the present disclosure, an electronic device capable of implementing the above-described method is also provided.

[0148] Those skilled in the art can understand that various aspects of the present disclosure can be implemented as a system, a method or a program product. Therefore, various aspects of the present disclosure can be embodied as a complete hardware embodiment, a complete software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects, which can be collectively referred to as "circuitry", "module" or "system" here.

[0149] The electronic device 1200 according to such embodiments of the present disclosure will be described below with reference to Figure 12 Figure 12 The display electronic device 1200 is merely an example and should not impose any limitation on the functions and use range of the embodiments of the present disclosure.

[0150] As shown in Figure 12 The electronic device 1200 is in the form of a general computing device. The components of the electronic device 1200 can include, but are not limited to, the at least one processing unit 1210 described above, the at least one storage unit 1220 described above, a bus 1230 connecting different system components (including the storage unit 1220 and the processing unit 1210), and a display unit 1240.

[0151] The storage unit stores program code which can be executed by the processing unit 1210, so that the processing unit 1210 performs the steps according to various exemplary embodiments of the present disclosure described in the "Exemplary Method" section of the present specification.

[0152] The storage unit 1220 can include a readable medium in the form of a volatile storage unit, such as a random access memory (RAM) 1221 and / or a cache memory unit 1222, and can further include a read-only memory (ROM) 1223.

[0153] ​The storage unit 1220 can also include a program / utility 1224 having a set of programs / modules 1225, each of which performs one or more tasks of the electronic device 1200, such as one or more of the tasks described above. The programs / utility 1224 can include, for example, booting, loading, configuring, and / or initializing programs associated with the operating system 1222. The programs / utility 1224 can also include one or more applications suitable for carrying out one or more processes or defining one or more techniques. The programs / utility 1224 can also include installation programs, demonstration programs, word processing programs, spreadsheet programs, email programs, or other types of software programs.

[0154] The bus 1230 can represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration bus, a processor or local bus using any of a variety of bus architectures, and so on.

[0155] The electronic device 1200 can also communicate with one or more external devices 1270 such as a keyboard or pointing device, a Bluetooth device, etc.; one or more devices that enable a user to interact with the electronic device 1200; and / or one or more devices (e.g., a router, a modem, a server, etc.) that enable the electronic device 1200 to communicate with one or more other computing devices. Such communication can occur via an input / output (I / O) interface 1250. Still yet, the electronic device 1200 can communicate with one or more networks, such as one or more local area networks (LANs), one or more wide area networks (WANs), and / or one or more public networks, such as the Internet, via the network adapter 1260. As depicted, the network adapter 1260 can communicate with the other components of the electronic device 1200 via the bus 1230. It should be appreciated that the electronic device 1200 can be a part of a larger system, and that there can be additional devices

[0156] Those skilled in the art will readily understand that the example embodiments described herein can be implemented by software and / or firmware in addition to or instead of necessarily hardware. Thus, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of a software product. The software product can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash disk, a mobile hard disk, or the like) or a network, and includes a number of instructions to make a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) execute the methods according to the embodiments of the present disclosure.

[0157] In exemplary embodiments of the present disclosure, a computer readable storage medium having stored thereon a program product capable of implementing the above-described method of the specification is also provided. In some possible embodiments, various aspects of the present application can also be implemented in the form of a program product including program code, which, when run on a terminal device, is used to cause the terminal device to perform the steps described in the above "Exemplary Method" section according to various exemplary embodiments of the present application.

[0158] Reference Figure 13 As shown, a program product 1300 for implementing the above-described method according to embodiments of the present application is described, which can take the form of a portable compact disc read-only memory (CD-ROM) and include program code, and can be run on a terminal device, such as a personal computer. However, the program product of the present application is not limited thereto, and in the present document, the readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus or device.

[0159] The program product can take any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium, for example, can be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0160] The computer readable signal medium can include a data signal propagated in baseband or propagated as a carrier wave, in which readable program code is carried. Such propagated data signal can take various forms, including but not limited to electromagnetic signal, optical signal or any suitable combination thereof. The readable signal medium can also be any readable medium other than the readable storage medium, which can send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device.

[0161] The program code contained on the readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination thereof.

[0162] The program code may be implemented in any of various ways, including procedure-based, narrative-based, object-based, and / or architectural-based versions. In procedure-based implementations, the program code is implemented in a series of isolated procedures, which rely primarily on extrinsic (or global) variables to communicate with one another. In narrative-based implementations, the program code is implemented at various levels by an interpreter or virtual machine. In object-based versions, the program code is implemented as a series of objects, which interact to perform the functionality of the present application. In architectural-based versions, the program code is implemented based on a component model, which organizes functionality into components that are interconnected to achieve the functionality of the present application.

[0163] Furthermore, the above-described diagrams are only schematic and are non-limiting. As such, the processes described above, and shown in the diagrams, are not intended to be limiting. For example, it will be readily apparent to those skilled in the art that the orders of the processes described above can be modified in various ways. Furthermore, the processes can be implemented by hardware that is functionally coupled to the modules in the illustrated software, including the modules that are not explicitly shown or discussed. Additionally, it will be readily apparent that the processes can be performed in parallel, or in an order different than that described above.

[0164] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features of the disclosure disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the disclosure being indicated by the following claims.

[0165] It is to be understood that the disclosure is not limited to the precise construction described above and shown in the attached drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the disclosure. The scope of the disclosure is limited only by the claims that follow.

Claims

1. A chip yield analysis method, characterized in that, include: Acquire information on failed chips obtained from chip testing, and acquire pre-stored failure pattern information and defective process information; Based on the failure pattern information and the defect process information, the failure chip information is subjected to data filtering processing to obtain the failure pattern type corresponding to the failure chip; The failure pattern location in the failure pattern type is matched with the process defect location to obtain a matched failure pattern. The pair of failure data to be analyzed corresponding to the matching failure pattern is determined, and the yield loss is calculated based on the pair of failure data to be analyzed to obtain the yield loss ratio corresponding to each defect process.

2. The method according to claim 1, characterized in that, The chip testing includes functional testing; obtaining the failed chip information based on the chip testing includes: Obtain the chip test results based on the aforementioned functional tests; The target wafer is obtained based on the chip test results. The target wafer includes a wafer with regular failure shape and more than a preset number of process station data. Based on the target wafer, obtain the failure chip identifier and chip location information of the failed chip; Based on the failed chip identifier and the chip location information, failed chip information is generated.

3. The method according to claim 1, characterized in that, The acquisition of pre-stored failure graphic information and defect process information includes: Obtain pre-stored failure graphic types and determine the failure graphic details information corresponding to each failure graphic type; The failure graphic information is generated based on the failure graphic details for each failure graphic type; Obtain the pre-stored defective process information; the defective process information includes any one or more combinations of defective process type, defective process identifier, defective process graphic, and defective process location.

4. The method according to claim 3, characterized in that, The acquisition of pre-stored failure graphic types includes: The predefined failure pattern type is determined and stored in the failure pattern database; the failure pattern type includes any one or a combination of multiple types of bit failure type, word line failure type, bit line failure type, cross failure type and block failure type; The bit failure types include single-cell failure types, double-cell failure types, and cluster-cell failure types; The word line failure types include single word line failure types and multi-word line failure types; The bit line failure types include single bit line failure types and multi-bit line failure types; The crossover failure type is formed by the intersection of the word line failure type and the bit line failure type. The block failure type consists of at least one failure region block.

5. The method according to claim 1, characterized in that, The defective process information includes the target defective process; the data filtering process for the failed chip information based on the failure pattern information and the defective process information to obtain the failure pattern type corresponding to the failed chip includes: Identify the target defect process that matches the target wafer; Based on the failure pattern information and the target defect process, the failure chip information is subjected to data filtering processing to obtain the failure pattern type.

6. The method according to claim 1, characterized in that, The step of performing position matching processing on the failure pattern position and the process defect position in the failure pattern type to obtain a position-matched failure pattern includes: The position of the failure pattern in each failure pattern type is matched one by one with the position of the process defect to obtain the matching result; The failure pattern whose matching result is that the failure pattern position matches the process defect position is taken as the matched failure pattern.

7. The method according to claim 6, characterized in that, The step of using the failure pattern whose matching result is a match between the failure pattern location and the process defect location as the matched failure pattern includes: When the location of the failure pattern matches the location of the process defect, obtain failure-related information corresponding to the location of the failure pattern. The failed chip identifier is determined based on the failure-related information, and the matching failure pattern is determined based on the failed chip identifier.

8. The method according to claim 1, characterized in that, The step of determining the pair of failure data to be analyzed corresponding to the matching failure graph includes: Obtain the process pattern data pair consisting of the defective process and the matching failure pattern; When a defective process corresponds to multiple matching failure patterns, the matching failure pattern with the highest failure level is selected from the multiple matching failure patterns as the target failure pattern. Based on the target failure pattern and the defective process, the failure data pair to be analyzed is generated.

9. The method according to claim 8, characterized in that, The step of determining the pair of failure data to be analyzed corresponding to the matching failure graph further includes: When a matching failure pattern corresponds to multiple defective processes, a defective process is randomly selected from the multiple defective processes as the target defective process. Based on the target defect process and the matching failure pattern, the failure data pair to be analyzed is generated.

10. The method according to claim 1, characterized in that, The process of calculating yield loss based on the failure data to be analyzed, and obtaining the yield loss ratio corresponding to each defective process, includes: The total failure rate is determined based on the failure data to be analyzed. Determine the defective process to be analyzed contained in the failure data pair to be analyzed, and determine the process matching ratio corresponding to each defective process to be analyzed; Based on the total failure ratio and the matching ratio of each process, the yield loss ratio corresponding to the defects in the processes to be analyzed is determined.

11. The method according to claim 10, characterized in that, Determining the process matching ratio corresponding to each of the defective processes to be analyzed includes: The total number of failed chips is determined based on the failure data to be analyzed. Obtain the number of process failure chips corresponding to each of the defective processes to be analyzed; The process matching ratio is determined based on the total number of failed chips and the number of process-failed chips.

12. The method according to any one of claims 1-11, characterized in that, The method further includes: Obtain the pre-configured failure rate threshold; Defective processes with a yield loss ratio greater than the failure ratio threshold are designated as processes to be corrected. The process to be corrected is then subjected to process adjustment.

13. A chip yield analysis device, characterized in that, include: The information acquisition module is used to acquire information on failed chips obtained from chip testing, as well as pre-stored failure pattern information and defect process information; The failure type determination module is used to perform data filtering processing on the failure chip information based on the failure pattern information and the defect process information to obtain the failure pattern type corresponding to the failure chip. The failure pattern matching module is used to perform position matching processing on the position of the failure pattern in the failure pattern type and the position of the process defect to obtain the position-matched failure pattern. The yield loss calculation module is used to determine the failure data pair to be analyzed corresponding to the matching failure pattern, and to calculate the yield loss based on the failure data pair to be analyzed, so as to obtain the yield loss ratio corresponding to each defect process.

14. An electronic device, characterized in that, include: processor; as well as A memory storing computer-readable instructions that, when executed by the processor, implement the chip yield analysis method according to any one of claims 1 to 12.

15. A computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the chip yield analysis method according to any one of claims 1 to 12.

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