Low-noise amplifier and radio frequency chip

Abstract

The present invention provides a low-noise amplifier and radio frequency chip, which include a signal input terminal, a common-source and common-gate low-noise amplifier link including a source-level negative feedback inductor, an output matching network, an output resistance attenuation network, and a signal output terminal, which are connected in sequence. The low-noise amplifier also includes multiple switches, a bypass matching circuit, and a transistor bias access circuit. The common-source and common-gate low-noise amplifier link includes a first inductor, a first capacitor, a first transistor, a second transistor, a second inductor, a third inductor, and a second capacitor. The multiple switches include a first switch, a second switch, a third switch, and a fourth switch. The second end of the first inductor is respectively connected to the first end of the first switch and the first end of the second switch, the second end of the first switch is respectively connected to the first end of the bypass matching circuit and the first end of the fourth switch, the first end of the fourth switch is grounded, and the second end of the bypass matching circuit is connected to the first end of the third switch. The low-noise amplifier of the present invention has diverse modes and functions, high reliability, and a wide range of applications.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a low noise amplifier and a radio frequency chip. Background Art

[0002] As humanity enters the information age, wireless communication technology has developed rapidly. From mobile phones to wireless LANs and Bluetooth, these technologies have become an integral part of social life and development. The advancement of wireless communication technology is inseparable from the development of radio frequency circuits. In wireless transceiver systems, the radio frequency low-noise amplifier (LNA) is a crucial component. The LNA amplifies the signal power, obtaining sufficient RF power before the signal is fed to the antenna for radiation. Among these, the LNA's gain and return loss are crucial performance indicators.

[0003] Existing low-noise amplifiers (LNAs) include an input matching circuit, a cascode amplifier, and an output matching circuit. The cascode amplifier processes the power signal input from the input matching circuit and then outputs it through the output matching circuit, thereby achieving low noise.

[0004] However, the above-mentioned low-noise amplifier performs signal amplification through a common-gate common-source amplifier and outputs a fixed low-noise power signal, has a single function, and has poor reliability. Summary of the Invention

[0005] In view of the above deficiencies in the prior art, the present invention proposes a low noise amplifier to solve the problems of single function and poor reliability of the prior low noise amplifier.

[0006] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0007] In a first aspect, an embodiment of the present invention provides a low-noise amplifier, comprising a signal input terminal, a common-source common-gate low-noise amplifier link including a source-level negative feedback inductor, an output matching network, an output resistance attenuation network, and a signal output terminal, connected in sequence. The low-noise amplifier also includes a plurality of switches, a bypass matching circuit, and a transistor bias access circuit.

[0008] The common-source common-gate low-noise amplifier link includes a first inductor, a first capacitor, a first transistor, a second transistor, a second inductor, a third inductor, and a second capacitor; the plurality of switches include a first switch, a second switch, a third switch, and a fourth switch;

[0009] The first end of the first inductor is connected to the signal input end, and the second end of the first inductor is connected to the first end of the first switch and the first end of the second switch respectively;

[0010] The second end of the first switch is connected to the input end of the bypass matching circuit and the first end of the fourth switch respectively, and the second end of the fourth switch is grounded;

[0011] The output end of the bypass matching circuit is connected to the first end of the third switch, and the second end of the third switch is connected to the first end of the output matching network;

[0012] The second end of the second switch is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the gate of the first transistor;

[0013] The source of the first transistor is connected to the first end of the second inductor, the second end of the second inductor is connected to the first end of the transistor connected to the bias circuit, the second end of the transistor connected to the bias circuit is grounded, and the third end of the transistor connected to the bias circuit is used to connect to an external control logic circuit to control the actions of the multiple switches;

[0014] The drain of the first transistor is connected to the source of the second transistor, the gate of the second transistor is grounded, the drain of the second transistor is respectively connected to the first end of the second capacitor and the first end of the third inductor, and the second end of the third inductor is connected to the supply voltage;

[0015] The second end of the second capacitor is connected to the first end of the output matching network, the second end of the output matching network is connected to the first end of the output resistance attenuation network, the second end of the output resistance attenuation network is connected to the signal output end, and the third end of the output matching network and the third end of the output resistance attenuation network are grounded respectively.

[0016] Preferably, the low noise amplifier further includes a third capacitor, a first end of the third capacitor is connected to the gate of the second transistor, and a second end of the third capacitor is grounded.

[0017] Preferably, the low noise amplifier further includes a first resistor, and the gate of the first transistor is connected to a first bias voltage by being connected in series with the first resistor.

[0018] Preferably, the low noise amplifier further includes a second resistor, and the gate of the second transistor is connected to a second bias voltage by being connected in series with the second resistor.

[0019] Preferably, the bypass matching circuit includes a fourth capacitor and a fifth capacitor, the first end of the fourth capacitor is connected to the first end of the fifth capacitor as the input end of the bypass matching circuit, the second end of the fourth capacitor is grounded, and the second end of the fifth capacitor serves as the output end of the bypass matching circuit.

[0020] Preferably, the output matching network includes a sixth capacitor and a seventh capacitor, the first end of the sixth capacitor serves as the first end of the output matching network, the second end of the sixth capacitor is connected to the first end of the seventh capacitor and serves as the second end of the output matching network, and the second end of the seventh capacitor serves as the third end of the output matching network.

[0021] Preferably, the output resistance attenuation network includes a fifth switch, a sixth switch, a third resistor, a fourth resistor and a fifth resistor. The first end of the third resistor is connected to the first end of the fifth switch and serves as the first end of the output resistance attenuation network. The second end of the third resistor is respectively connected to the first end of the fourth resistor and the first end of the fifth resistor. The second end of the fifth switch is connected to the second end of the fourth resistor, and the second end of the fourth resistor serves as the second end of the output resistance attenuation network. The second end of the fifth resistor is connected to the first end of the sixth switch, and the second end of the sixth switch serves as the third end of the output resistance attenuation network.

[0022] Preferably, the transistor connected to the bias circuit includes a third transistor, the source of the third transistor serves as the second end of the transistor connected to the bias circuit, the drain of the third transistor serves as the first end of the transistor connected to the bias circuit, and the gate of the third transistor serves as the third end of the transistor connected to the bias circuit.

[0023] Preferably, the first transistor, the second transistor and the third transistor are all NMOS transistors.

[0024] In a second aspect, an embodiment of the present invention provides a radio frequency chip, wherein the radio frequency chip includes the above-mentioned low noise amplifier.

[0025] Compared with the related art, in an embodiment of the present invention, a signal input terminal, a common-source common-gate low-noise amplifier link including a source-level negative feedback inductor, a plurality of switches, a bypass matching circuit, a transistor bias access circuit, an output matching network, an output resistance attenuation network, and a signal output terminal are sequentially connected; the common-source common-gate low-noise amplifier link includes a first inductor, a first capacitor, a first transistor, a second transistor, a second inductor, a third inductor, and a second capacitor; the plurality of switches include a first switch, a second switch, a third switch, and a fourth switch; the first end of the first inductor is connected to the signal input terminal, the second end of the first inductor is respectively connected to the first end of the first switch and the first end of the second switch, the second end of the first switch is respectively connected to the first end of the bypass matching circuit and the first end of the fourth switch, the first end of the fourth switch is grounded, and the second end of the bypass matching circuit is connected to the first end of the third switch. In this way, by connecting the bypass matching circuit to both ends of the common-source common-gate low-noise amplifier link and controlling the on / off of the bypass matching circuit through the plurality of switches, multiple bypass mode functions are realized, so that the return loss of the low-noise amplifier operating frequency is small and the reliability is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention will be described in detail below with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made with reference to the following drawings. In the accompanying drawings:

[0027] Figure 1 is a circuit diagram of a low noise amplifier in an embodiment of the present invention;

[0028] Figure 2 This is a circuit schematic diagram of an implementation form of a low noise amplifier in an embodiment of the present invention;

[0029] Figure 3 FIG. 4 is an equivalent circuit diagram of a low noise amplifier in an embodiment of the present invention operating in a bypass mode.

[0030] Among them, 100, low noise amplifier, 1, signal input end, 2, common source and common gate low noise amplifier link, 3, multiple switches, 4, bypass matching circuit, 5, transistor bias access circuit, 6, output matching network, 7, output resistance attenuation network, 8, signal output end. DETAILED DESCRIPTION

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of the application are for the purpose of describing specific embodiments only and are not intended to limit this application. The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0032] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0034] Example 1

[0035] See also Figure 1-3 As shown, an embodiment of the present invention provides a low-noise amplifier 100, which includes a signal input terminal 1, a cascode low-noise amplifier link 2 including a source-level negative feedback inductor, an output matching network 6, an output resistor attenuation network 7, and a signal output terminal 8. The low-noise amplifier 100 also includes multiple switches 3, a bypass matching circuit 4, and a transistor bias access circuit 5.

[0036] The cascode low-noise amplifier link 2 includes a first inductor LG, a first capacitor CB1, a first transistor M1, a second transistor M2, a second inductor LS, a third inductor LD, and a second capacitor CB2; the multiple switches include a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4. The first inductor LG and the second inductor LS are both commonly used inductors, and the third inductor LD is an RF choke inductor used to provide a DC operating point. The first transistor M1 is a common-source amplifier, and the second transistor M2 is a common-gate amplifier. The first capacitor CB1 and the second capacitor CB2 are DC blocking capacitors used to isolate the passage of DC power.

[0037] A first end of the first inductor LG is connected to the signal input terminal 1 , and a second end of the first inductor LG is connected to a first end of the first switch S1 and a first end of the second switch S2 , respectively.

[0038] The second end of the first switch S1 is connected to the input end of the bypass matching circuit 4 and the first end of the fourth switch S4 respectively, and the second end of the fourth switch S4 is grounded.

[0039] The output end of the bypass matching circuit 4 is connected to the first end of the third switch S3 , and the second end of the third switch S3 is connected to the first end of the output matching network 6 .

[0040] The second end of the second switch S2 is connected to the first end of the first capacitor CB1, the second end of the first capacitor CB1 is connected to the gate of the first transistor M1, the source of the first transistor M1 is connected to the first end of the second inductor LS, the second end of the second inductor LS is connected to the first end of the transistor connected to the bias circuit 5, and the second end of the transistor connected to the bias circuit 5 is grounded. The third end of the transistor connected to the bias circuit 5 is used to connect to an external control logic circuit to control the operation of the multiple switches 3. The drain of the first transistor M1 is connected to the source of the second transistor M2, the gate of the second transistor M2 is grounded, the drain of the second transistor M2 is respectively connected to the first end of the second capacitor CB2 and the first end of the third inductor LD, the second end of the third inductor LD is connected to the supply voltage VDD, the second end of the second capacitor CB2 is connected to the first end of the output matching network 6, the second end of the output matching network 6 is connected to the first end of the output resistance attenuation network 7, the second end of the output resistance attenuation network 7 is connected to the signal output terminal 8, and the third end of the output matching network 6 and the third end of the output resistance attenuation network 7 are respectively grounded.

[0041] Specifically, when the input signal at the signal input terminal 1 is large, a passive bypass matching circuit 4 can be used to achieve low-power reception. The first off-chip inductor LG can meet the user's flexible adjustment of the frequency / noise figure / input impedance in the amplification mode. In the bypass mode, the third inductor LD and the output matching network 6 can achieve the effect of reducing circuit expenses and area.

[0042] The input signal enters the low-noise amplifier 100 via the first inductor LG. In the amplifier mode, the first and third switches S1 and S3 are off, while the second and fourth switches S2 and S4 are on. The gate of the transistor bias circuit 5 is set high, enabling normal operation of the cascode amplifier. The signal is input to the first transistor M1 via the first capacitor CB1. The source-stage negative feedback of the second inductor LS provides a noise-free real part of the input matching. The signal is amplified by the first transistor M1 and then amplified by the second transistor M2 before being output. The third inductor LD provides a DC operating point and forces the RF signal to enter the output matching circuit through the second output capacitor CB2. Finally, it reaches the output terminal through the resistor attenuation network. In the bypass mode, the first and third switches S1 and S3 are on, while the second and fourth switches S2 and S4 are off. The gate of the transistor bias circuit 5 is set low, disconnecting the cascode amplifier circuit and reducing the parasitic capacitance to ground after the first inductor LG. Simultaneously, the first bias voltage BIAS1 drops to a low voltage, placing the second transistor M2 in the cutoff region and disconnecting the signal from the first transistor M1. The switched bypass link consists of a first inductor LG, a bypass matching circuit 4, a second capacitor CB2, a third inductor LD, an output matching network 6, and an output resistor attenuation network 7. The signal is input into the bypass matching circuit 4 via the first inductor LG. The bypass matching circuit 4 sets the output impedance of the third switch S3 equal to the output impedance of the second transistor M2 in the amplification mode. Since the second capacitor CB2 does not provide additional impedance transformation and the parasitic capacitance of the drain of the second transistor M2 to ground is very small, the third inductor LD and the output matching network 6 together cause the signal to resonate at the resonant frequency in the amplification mode, thereby ensuring a low return loss at the operating frequency. Finally, the signal is output to the resistor attenuation network.

[0043] In this embodiment, the low-noise amplifier 100 further includes a third capacitor CCG, a first end of which is connected to the gate of the second transistor M2, and a second end of which is grounded, so that the gate of the second transistor M2 is DC-isolated and the second transistor M2 operates stably.

[0044] In this embodiment, the low-noise amplifier 100 further includes a first resistor R1. The gate of the first transistor M1 is connected to a first bias voltage via the first capacitor R1 in series. The first bias voltage BTAS1 is connected via the first resistor R1, so that the first bias voltage BTAS1 is stepped down by the first resistor R1 and then output to the gate of the first transistor M1, resulting in high overall circuit stability.

[0045] In this embodiment, the low-noise amplifier 100 further includes a second resistor R2. The gate of the second transistor M2 is connected to a second bias voltage BTAS2 via the second capacitor R2 in series. Connecting the second bias voltage via the second resistor R2 allows the second bias voltage BTAS2 to be stepped down by the second resistor R2 and then output to the gate of the second transistor M2, resulting in high overall circuit stability.

[0046] In this embodiment, the bypass matching circuit 4 includes a fourth capacitor CBP and a fifth capacitor CBS. The first end of the fourth capacitor CBP is connected to the first end of the fourth switch S4 and the first end of the fifth capacitor CBS as the input end of the bypass matching circuit 4. The second end of the fourth capacitor CBP is grounded, and the second end of the fifth capacitor CBS is connected to the first end of the third switch S3 as the output end of the bypass matching circuit 4. Bypass matching is achieved by the fourth capacitor CBP and the fifth capacitor CBS. The amplification mode is achieved when the first switch S1 and the third switch S3 are disconnected and the second switch S2 and the fourth switch S4 are turned on. When the first switch S1 and the third switch S3 are disconnected and the second switch S2 and the fourth switch S4 are turned on, the transistor bias circuit 5 is disconnected, achieving the bypass mode. Multi-mode switching and adjustment control enhances the reliability of the low-noise amplifier 100.

[0047] In this embodiment, the output matching network 6 includes a sixth capacitor CSE and a seventh capacitor CPA. The first end of the sixth capacitor CSE serves as the first end of the output matching network 6 and is respectively connected to the second end of the third switch S3 and the second end of the second capacitor CB2. The second end of the sixth capacitor CSE is respectively connected to the first end of the seventh capacitor CPA and serves as the second end of the output matching network 6. The second end of the seventh capacitor CPA serves as the second end of the output matching network 6 and is grounded. This enables the cascode low-noise amplifier chain 2 to output a higher RF power signal.

[0048] In this embodiment, the output resistance attenuation network 7 includes a fifth switch S5, a sixth switch S6, a third resistor RA1, a fourth resistor RA2, and a fifth resistor RA3. The first end of the third resistor RA1 is connected to the first end of the fifth switch S5 and serves as the first end of the output resistance attenuation network 7. The second end of the third resistor RA1 is connected to the first end of the fourth resistor RA2 and the first end of the fifth resistor RA3. The second end of the fifth switch S5 is connected to the second end of the fourth resistor RA2, which serves as the second end of the output resistance attenuation network 7 and is connected to the signal output terminal 8. The second end of the fifth resistor RA3 is connected to the first end of the sixth switch S6, and the second end of the sixth switch S6 serves as the third end of the output resistance attenuation network 7 and is grounded. The fifth switch S5, the sixth switch S6, the third resistor RA1, the fourth resistor RA2, and the fifth resistor RA3 form a resistance attenuation network to achieve a resistance attenuation function. The fifth switch S5 is turned on in the amplification mode and off in the bypass mode. The sixth switch S6 is turned off in the amplification mode and turned on in the bypass mode.

[0049] In this embodiment, the first inductor LG, the fifth capacitor CBS, the sixth capacitor CSE, the third resistor RA1, and the fourth resistor RA2 are connected in series in sequence; the first end of the fourth capacitor CBP is connected between the first inductor LG and the fifth capacitor CBS, and the second end of the fourth capacitor CBP is grounded; the first end of the third inductor LD is connected between the fifth capacitor CBS and the sixth capacitor CSE, and the second end of the third inductor LD is grounded; the first end of the seventh capacitor CPA is connected between the sixth capacitor CSE and the third resistor RA1, and the second end of the seventh capacitor CPA is grounded; the first end of the fifth resistor RA3 is connected between the third resistor RA1 and the fourth resistor RA2, and the second end of the fifth resistor RA3 is grounded. Since the second capacitor CB2 has little effect on impedance, the second transistor M2 is equivalent to an RF short circuit, and the power signal is output to the signal output terminal 8 through the first inductor LG, the fifth capacitor CBS, the sixth capacitor CSE, the third resistor RA1, and the fourth resistor RA2.

[0050] In this embodiment, the transistor connected to the bias circuit includes a third transistor M3. The source of the third transistor M3 serves as the second end of the transistor connected to the bias circuit and is grounded. The drain of the third transistor M3 serves as the first end of the transistor connected to the bias circuit and is connected to the second end of the second inductor LS. The gate of the third transistor M3 serves as the third end of the transistor connected to the bias circuit and is connected to a control logic circuit for controlling the on and off of the multiple switches.

[0051] In this embodiment, the first transistor M1 , the second transistor M2 , and the third transistor M3 are all NMOS transistors.

[0052] In this embodiment, an input signal enters the low-noise amplifier 100 via the first inductor LG. In the amplification mode, the first and third switches S1 and S3 are disconnected, while the second and fourth switches S2 and S4 are turned on. The gate of the third transistor M3 is set high, enabling normal operation of the cascode amplifier. The signal is input to the first transistor M1 via the first capacitor CB1. The source-stage negative feedback of the second inductor LS provides a noise-free real part of the input matching. The signal is amplified by the first transistor M1 and then amplified by the second transistor M2 before being output. The third inductor LD provides a DC operating point and forces the RF signal to enter the output matching circuit through the second output capacitor CB2, ultimately reaching the output terminal through the resistor attenuation network. In the bypass mode, the first and third switches S1 and S3 are turned on, while the second and fourth switches S2 and S4 are turned off. The gate of the third transistor M3 is set low, disconnecting the cascode amplifier circuit and reducing the parasitic capacitance to ground after the first inductor LG. Simultaneously, the second bias voltage BIAS2 drops to a low voltage, placing the second transistor M2 in a cutoff region, disconnecting the signal from the first transistor M1. The switched bypass link consists of a first inductor LG, a bypass matching circuit 4, a second capacitor CB2, a third inductor LD, an output matching network 6, and an output resistor attenuation network 7. The signal is input into the bypass matching circuit 4 via the first inductor LG. The bypass matching circuit 4 sets the output impedance of the third switch S3 equal to the output impedance of the second transistor M2 in the amplification mode. Since the second capacitor CB2 does not provide additional impedance transformation and the parasitic capacitance of the drain of the second transistor M2 to ground is very small, the third inductor LD and the output matching network 6 together cause the signal to resonate at the resonant frequency in the amplification mode, thereby ensuring a low return loss at the operating frequency. Finally, the signal is output to the resistor attenuation network.

[0053] Example 2

[0054] An embodiment of the present invention provides a radio frequency chip, which includes the low noise amplifier 100 of the first embodiment.

[0055] It should be noted that the various embodiments described above with reference to the accompanying drawings are intended only to illustrate the present invention and are not intended to limit the scope of the present invention. Those skilled in the art should understand that any modifications or equivalent substitutions to the present invention that do not depart from the spirit and scope of the present invention are intended to be encompassed within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include the plural form, and vice versa. Furthermore, unless otherwise specified, all or part of any embodiment may be used in combination with all or part of any other embodiment.

Claims

1. A low-noise amplifier comprising a signal input terminal, a common-source and common-gate low-noise amplifier link including a source-level negative feedback inductor, an output matching network, an output resistance attenuation network, and a signal output terminal connected in sequence, characterized in that: The low noise amplifier further includes a plurality of switches, a bypass matching circuit and a transistor bias access circuit; The common-source common-gate low-noise amplifier link includes a first inductor, a first capacitor, a first transistor, a second transistor, a second inductor, a third inductor, and a second capacitor; the plurality of switches include a first switch, a second switch, a third switch, and a fourth switch; The first end of the first inductor is connected to the signal input end, and the second end of the first inductor is connected to the first end of the first switch and the first end of the second switch respectively; The second end of the first switch is connected to the input end of the bypass matching circuit and the first end of the fourth switch respectively, and the second end of the fourth switch is grounded; The output end of the bypass matching circuit is connected to the first end of the third switch, and the second end of the third switch is connected to the first end of the output matching network; The second end of the second switch is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the gate of the first transistor; The source of the first transistor is connected to the first end of the second inductor, the second end of the second inductor is connected to the first end of the transistor connected to the bias circuit, the second end of the transistor connected to the bias circuit is grounded, and the third end of the transistor connected to the bias circuit is used to connect to an external control logic circuit to control the actions of the multiple switches; The drain of the first transistor is connected to the source of the second transistor, the gate of the second transistor is grounded, the drain of the second transistor is respectively connected to the first end of the second capacitor and the first end of the third inductor, and the second end of the third inductor is connected to the supply voltage; The second end of the second capacitor is connected to the first end of the output matching network, the second end of the output matching network is connected to the first end of the output resistance attenuation network, the second end of the output resistance attenuation network is connected to the signal output end, and the third end of the output matching network and the third end of the output resistance attenuation network are grounded respectively.

2. The low noise amplifier according to claim 1, wherein The low noise amplifier further includes a third capacitor, a first end of the third capacitor is connected to the gate of the second transistor, and a second end of the third capacitor is grounded.

3. The low noise amplifier according to claim 1, wherein The low noise amplifier further includes a first resistor, and the gate of the first transistor is connected to a first bias voltage by being connected in series with the first resistor.

4. The low noise amplifier according to claim 2, wherein: The low noise amplifier further includes a second resistor, and the gate of the second transistor is connected to a second bias voltage through the second resistor in series.

5. The low noise amplifier according to claim 1, wherein: The bypass matching circuit includes a fourth capacitor and a fifth capacitor, the first end of the fourth capacitor is connected to the first end of the fifth capacitor as the input end of the bypass matching circuit, the second end of the fourth capacitor is grounded, and the second end of the fifth capacitor serves as the output end of the bypass matching circuit.

6. The low noise amplifier according to claim 1, wherein: The output matching network includes a sixth capacitor and a seventh capacitor, the first end of the sixth capacitor serves as the first end of the output matching network, the second end of the sixth capacitor is connected to the first end of the seventh capacitor and serves as the second end of the output matching network, and the second end of the seventh capacitor serves as the third end of the output matching network.

7. The low noise amplifier according to claim 6, wherein: The output resistance attenuation network includes a fifth switch, a sixth switch, a third resistor, a fourth resistor and a fifth resistor. The first end of the third resistor is connected to the first end of the fifth switch and serves as the first end of the output resistance attenuation network. The second end of the third resistor is respectively connected to the first end of the fourth resistor and the first end of the fifth resistor. The second end of the fifth switch is connected to the second end of the fourth resistor. The second end of the fourth resistor serves as the second end of the output resistance attenuation network. The second end of the fifth resistor is connected to the first end of the sixth switch. The second end of the sixth switch serves as the third end of the output resistance attenuation network.

8. The low noise amplifier according to claim 1, wherein: The transistor connected to the bias circuit includes a third transistor, the source of the third transistor serves as the second end of the transistor connected to the bias circuit, the drain of the third transistor serves as the first end of the transistor connected to the bias circuit, and the gate of the third transistor serves as the third end of the transistor connected to the bias circuit.

9. The low noise amplifier according to claim 8, wherein: The first transistor, the second transistor and the third transistor are all NMOS transistors.

10. A radio frequency chip, characterized in that: The radio frequency chip includes the low noise amplifier according to any one of claims 1 to 9.

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