Display substrate, method for manufacturing display substrate, and display panel

Abstract

The display substrate, the manufacturing method of the display substrate and the display panel belong to the technical field of display and aim to reduce display brightness difference between display panels. The display substrate comprises a substrate, a plurality of pixel units on the substrate, and each pixel unit comprises a pixel electrode, and the pixel electrode comprises a plurality of sub-electrodes with uniform intervals. At least two different layout structures of the pixel electrode exist, and the layout structure comprises the interval between the sub-electrodes and / or the size of the sub-electrodes in a target direction, and the target direction is the direction of one sub-electrode towards the adjacent sub-electrode.

Description

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate, a manufacturing method of the display substrate, and a display panel. BACKGROUND

[0002] With the development of display technology, there are active matrix organic light-emitting displays (hereinafter referred to as “OLED”), liquid crystal displays (hereinafter referred to as “LCD”), and the like. Among them, the light-emitting effect of the display is related to the quality of the display picture. However, in the related art, due to the process fluctuation existing in the manufacturing of the display panel, the light-emitting effect between the display panels will appear different. SUMMARY

[0003] The present disclosure provides a display substrate, comprising:

[0004] a substrate;

[0005] a plurality of pixel units located on the substrate, and each of the pixel units comprises a pixel electrode, the pixel electrode comprising a plurality of sub-electrodes with uniform spacing;

[0006] wherein there are at least two different layout structures of the pixel electrodes, the layout structure comprising the spacing between the sub-electrodes and / or the size of the sub-electrodes in a target direction, the target direction being the direction of one sub-electrode towards the adjacent other sub-electrode.

[0007] Optionally, between the pixel electrodes with different layout structures, the size of the sub-electrodes is the same and the spacing between the sub-electrodes is different; or the spacing between the sub-electrodes is the same and the size of the sub-electrodes is different.

[0008] Optionally, between the pixel electrodes with different layout structures, the size of the sub-electrodes and the spacing between the sub-electrodes are different.

[0009] Optionally, the layout structure comprises a first layout structure and a second layout structure, the corresponding structure parameter of the first layout structure being greater than 1, and the corresponding structure parameter of the second layout structure being less than 1.

[0010] The structure parameter is the ratio of the spacing between the adjacent two sub-electrodes to the size of the sub-electrodes.

[0011] Optionally, the spacing between the sub-electrodes of the pixel electrode with the first layout structure is the same as the size of the sub-electrodes of the pixel electrode with the second layout structure; and the size of the sub-electrodes of the pixel electrode with the first layout structure is the same as the spacing between the sub-electrodes of the pixel electrode with the second layout structure.

[0012] Optionally, the structural parameter corresponding to the first layout structure is greater than or equal to 1.4 and less than or equal to 2.

[0013] Optionally, the structural parameter corresponding to the second layout structure is greater than or equal to 0.5 and less than or equal to 0.71.

[0014] Optionally, different pixel electrodes with the first layout structure correspond to the same or different structural parameters.

[0015] Optionally, different pixel electrodes with the second layout structure correspond to the same or different structural parameters.

[0016] Optionally, the layout structure further comprises a third layout structure, and the structural parameter corresponding to the third layout structure is different from the structural parameters corresponding to the first layout structure and the second layout structure, respectively.

[0017] Optionally, the structural parameter corresponding to a third pixel electrode with the third layout structure is 1.

[0018] Optionally, pixel units with different layout structures are staggered on the substrate.

[0019] Optionally, a plurality of pixel electrode arrays are arranged; wherein pixel electrodes with the same layout structure are arranged in columns or rows on the substrate.

[0020] Optionally, a plurality of pixel electrode arrays are arranged; wherein pixel electrodes with one layout structure and pixel electrodes with another different layout structure are alternately arranged in columns or rows on the substrate.

[0021] Optionally, pixel electrodes with one layout structure are arranged in multiple columns in succession, or pixel electrodes with one layout structure are arranged in multiple rows in succession.

[0022] Optionally, one pixel electrode is adjacent to at least one pixel electrode with a different layout structure.

[0023] Optionally, the sub-electrodes are in a strip shape, and a plurality of the sub-electrodes of each pixel electrode are arranged in parallel.

[0024] In some embodiments, a preparation method of a display substrate is also provided, the method comprising:

[0025] providing a substrate;

[0026] forming a plurality of spaced thin film transistors on the substrate;

[0027] forming pixel electrodes with at least two different layout structures on the plurality of thin film transistors, wherein the pixel electrodes comprise a plurality of sub-electrodes in a strip shape;

[0028] The layout structure includes a spacing between the sub-electrodes and / or a size of the sub-electrodes in a target direction, the target direction being a direction in which one sub-electrode faces another adjacent sub-electrode.

[0029] In some embodiments, a display panel is also provided, including a counter substrate and the display substrate, and a liquid crystal layer filled between the display substrate and the counter substrate.

[0030] The display substrate of the present disclosure includes a substrate and a plurality of pixel units located on the substrate, each pixel unit including a pixel electrode; wherein the pixel electrode includes a plurality of sub-electrodes, and there are at least two different layout structures of the plurality of pixel electrodes, the layout structure including a spacing between the sub-electrodes and / or a size of the sub-electrodes.

[0031] The display substrate has at least two different layout structures of the spacing between the sub-electrodes and / or the size of the sub-electrodes in the plurality of pixel units, so that the at least two different layout structures are present in the pixel electrodes of different display panels. When the same voltage is applied to the different display panels, for the same display panel, the pixel electrodes of one layout structure can compensate for the difference in the electric field formed by the pixel electrodes of another layout structure. Thus, the difference between the electric fields formed by the pixel electrodes of the display panel as a whole can be reduced, so that the difference in light transmittance between different display panels is reduced. Thus, the problem of large difference in luminous brightness between display panels and low product yield caused by the difference in the process of manufacturing the pixel electrodes when a single layout structure of the pixel electrodes is used can be solved.

[0032] The above description is only a summary of the technical solutions of the present disclosure. In order to more clearly understand the technical means of the present disclosure, the specific embodiments of the present disclosure can be implemented according to the content of the description, and in order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the following will specifically describe the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or related art description. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor. It should be noted that the size and shape of each figure in the drawings do not reflect the true proportion, and the purpose is only to illustrate the content of the present disclosure. The same or similar reference numerals in the drawings represent the same or similar elements or elements with the same or similar functions.

[0034] Figure 1Schematically shows VT curves between multiple display panels in the related art;

[0035] Figure 2 Schematically shows the Gamma curves between multiple display panels in the related art;

[0036] Figure 3 Schematically shows a cross-sectional structural diagram of a display substrate disclosed herein;

[0037] Figure 4 Schematically shows a layout diagram of pixel electrodes of a top-view display substrate of the present disclosure;

[0038] Figure 5 Schematically shows another layout diagram of pixel electrodes of a top-view display substrate of the present disclosure;

[0039] Figure 6 Schematically shows another layout diagram of pixel electrodes of a top view display substrate of the present disclosure;

[0040] Figure 7a Schematically shows a staggered arrangement of pixel electrodes when looking down at the display substrate of the present disclosure;

[0041] Figure 7b Schematically shows another staggered arrangement of pixel electrodes when looking down at the display substrate of the present disclosure;

[0042] Figure 7c FIG1 schematically shows another staggered arrangement of pixel electrodes when looking down at the display substrate of the present disclosure;

[0043] Figure 7d Schematically shows a staggered arrangement of pixel electrodes when looking down at the display substrate of the present disclosure;

[0044] Figure 7e Schematically shows another staggered arrangement of pixel electrodes when looking down at the display substrate of the present disclosure;

[0045] Figure 7f Schematically shows a staggered arrangement of pixel electrodes when looking down at the display substrate of the present disclosure;

[0046] Figure 7g Schematically shows another staggered arrangement of pixel electrodes when looking down at the display substrate of the present disclosure;

[0047] Figure 8a Schematically shows the gamma curves of display panels manufactured when a single pixel electrode design is performed based on a structural parameter of 1.4;

[0048] Figure 8b Schematically shows the gamma curves of display panels manufactured when a single pixel electrode is designed based on a structural parameter of 0.71;

[0049] Figure 8c The gamma curves of the display panels manufactured when the pixel electrodes are designed according to two structural parameters are schematically shown in the present disclosure;

[0050] Figure 9 Schematically shows a cross-sectional structural diagram of a display panel disclosed herein;

[0051] Figure 10 Schematically shows a schematic diagram of a method for manufacturing a display substrate disclosed in the present invention;

[0052] Description of reference numerals:

[0053] 101-substrate, 102-gate insulating layer, 103-first passivation layer, 104-second passivation layer, 105-orientation layer, 106-common electrode line, 107-gate line, 108-thin film transistor, 109-light shielding layer, 1091-black matrix, 110-encapsulation layer, 200-pixel electrode, 201-sub-electrode, 300-common electrode, 400-liquid crystal layer, W-spacing between sub-electrodes, S-size of sub-electrode in the target direction. DETAILED DESCRIPTION

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0055] In the related art, when manufacturing display panels, such as liquid crystal display panels, fluctuations in manufacturing processes can lead to differences in pixel electrodes between different display panels. An LCD panel typically includes red, green, and blue pixel units. The brightness of the color light emitted by each pixel unit is related to the deflection of the liquid crystal molecules, that is, the electric field applied to the liquid crystal cell. This electric field is provided by the pixel electrode under the drive of the pixel driver circuit.

[0056] Therefore, when the pixel electrodes of different display panels have differences, the electric field distribution in the liquid crystal cell of different display panels is different under the same applied voltage, which leads to the difference in the deflection of liquid crystal molecules, and the light transmittance of different liquid crystal panels is inconsistent, so that the display brightness of different display panels is different.

[0057] The light emitting effect of the display panel can be characterized by light transmittance and Gamma curve. Therefore, the inventors of the present disclosure tested the VT curve and Gamma curve of a plurality of display panels manufactured under the same design of pixel electrode.

[0058] Referring to Figure 1 and Figure 2 , the VT curve and the Gamma curve between a plurality of display panels are shown respectively; wherein, Figure 1 and Figure 2 The three display panels are panel A, panel B and panel C respectively, wherein the three display panels are all pixel electrodes with the same design, but the process fluctuation of different display panels causes certain differences between the pixel electrodes of panel A, panel B and panel C.

[0059] As shown in Figure 1 , the VT curve is shown, which reflects the relationship curve between the liquid crystal voltage and the transmittance. It can be seen that due to the difference between the pixel electrodes, the light transmittance of the three display panels is quite different under the same voltage.

[0060] As shown in Figure 2 , the Gamma curve is shown, which represents the corresponding relationship between brightness and gray scale. It can be seen that the difference in brightness becomes larger and larger as the gray scale increases. That is, under the same voltage applied to the pixel unit, the display brightness of different display panels should be the same, but the test shows that the Gamma curve difference is large, especially as the brightness increases, the difference is more obvious.

[0061] In order to avoid the difference in brightness between the display panels, the inventors try to improve the process to minimize the difference in process of different display panels, for example, by improving the photoetching, etching and other processes to reduce the size difference of the pixel electrode, but this way is very expensive.

[0062] Therefore, the inventors propose another solution to reduce the display difference between display panels while reducing the cost. Specifically, the pixel electrode is composed of multiple sub-electrodes, and in one display panel, the multiple pixel electrodes have at least two different layout structures, wherein the layout structure mainly refers to at least one of the spacing between the sub-electrodes of one pixel electrode and the size of the sub-electrodes; so that the pixel electrodes with different layout structures can compensate for each other when the same voltage is applied, thereby reducing the difference between the display panels as a whole.

[0063] First, the present disclosure provides a display substrate, as shown in Figure 3 、 Figure 4 、 Figure 5 and Figure 6 , the present disclosure provides a display substrate, as shown in Figure 3 , a schematic diagram of the cross-sectional structure of the display substrate of the present disclosure is shown, Figure 4 , a schematic diagram of one layout of the pixel electrode of the display substrate is shown in plan view; Figure 5 , a schematic diagram of another layout of the pixel electrode of the display substrate is shown in plan view; Figure 6 , a schematic diagram of another layout of the pixel electrode of the display substrate is shown in plan view.

[0064] As shown in Figures 3-6 , the display substrate provided by the present disclosure includes a substrate 101 and multiple pixel units located above the substrate 101, each pixel unit including a pixel electrode 200.

[0065] The pixel electrode 200 includes multiple spaced sub-electrodes 201, and the multiple pixel electrodes 200 have at least two different layout structures, wherein the layout structure includes the spacing W between the sub-electrodes 201 and / or the size S of the sub-electrodes in the target direction.

[0066] The target direction refers to the direction of one sub-electrode towards the adjacent other sub-electrode.

[0067] As shown in Figure 3 , the substrate is also provided with the following structures, as shown in

[0068] The gate line 107 is provided on the substrate 101.

[0069] The gate insulating layer 102 is provided on the gate line and the exposed substrate 101.

[0070] The common electrode line 106 is provided on the gate insulating layer 102.

[0071] The data line is provided on the gate insulating layer 102 and crosses the gate line.

[0072] The thin film transistor 108 is disposed on the gate insulating layer 102 and connected to the data line and the gate line. The pixel electrode 200 is connected to the thin film transistor. Specifically, the plurality of sub-electrodes 201 are electrically connected to the thin film transistor 108.

[0073] A first passivation layer 103 is provided on a side of the thin film transistor 108 facing away from the substrate 101 and has openings therein for the common electrode 300 and the pixel electrode 200 to pass through;

[0074] The pixel electrode 200 is disposed on a side of the thin film transistor 108 facing away from the substrate 101 , and the pixel electrode 200 includes a plurality of sub-electrodes 201 located on a side of the first passivation layer 103 facing away from the substrate 101 ;

[0075] The second passivation layer 104 is disposed on a side of the pixel electrode 200 facing away from the substrate 101 , and the orthographic projection of the second passivation layer 104 on the substrate 101 does not overlap with the orthographic projection of the sub-electrode 201 on the substrate 101 .

[0076] The common electrode 300 is disposed on a side of the second passivation layer 104 facing away from the substrate 101 and is directly connected to the common electrode line 106 via openings provided in the second passivation layer 104 and the first passivation layer 103. The common electrode 300 is planar and connected to the common electrode line 106. In some embodiments, the orthographic projections of the common electrodes 300 of different pixel units on the substrate 101 do not overlap. In other embodiments, the common electrode 300 may entirely cover the second passivation layer 104, thereby simplifying the manufacturing process.

[0077] The alignment layer 105 is disposed on a side of the common electrode 300 facing away from the substrate 101 and is used to align the liquid crystal molecules.

[0078] in, Figure 3 The display substrate shown can be used in an FFS (Fringe Field Switching) display mode.

[0079] like Figure 3As shown, the target direction refers to the direction of one sub-electrode 201 towards the adjacent other sub-electrode 201. Since the multiple sub-electrodes 201 of each pixel electrode 200 are uniformly spaced, the spacing between each adjacent two sub-electrodes 201 in the pixel electrode 200 is the same. Therefore, different layout structures can refer to that there are two pixel electrodes 200, the spacing of the sub-electrodes 201 in one of the two pixel electrodes 200 is different from the spacing of the sub-electrodes 201 in the other pixel electrode 200, or the size of the sub-electrodes 201 in one of the pixel electrodes 200 is different from the size of the sub-electrodes 201 in the other pixel electrode 200, or both the size and the spacing of the sub-electrodes 201 in one of the pixel electrodes 200 are different from the size and the spacing of the sub-electrodes 201 in the other pixel electrode 200.

[0080] As shown in FIG. 1, the pixel electrodes 200 in the display substrate 101 can have different layout structures. As shown, the pixel electrodes 200 on the left side and the pixel electrodes 200 on the right side have different spacing and size. Figure 3 As shown, the pixel electrodes 200 on the left side and the pixel electrodes 200 on the right side have different spacing and size. In this way, there are at least two pixel electrodes 200 with different layout structures in the display substrate 101.

[0081] As shown in FIG. 1, the pixel electrodes 200 in the display substrate 101 can have different layout structures. As shown, the pixel electrodes 200 on the left side and the pixel electrodes 200 on the right side have different spacing and size. Figure 3 As shown, the pixel electrodes 200 on the left side and the pixel electrodes 200 on the right side have different spacing and size. In this way, there are at least two pixel electrodes 200 with different layout structures in the display substrate 101.

[0082] As shown, the pixel electrodes 200 on the left side and the pixel electrodes 200 on the right side have different spacing and size. In this way, there are at least two pixel electrodes 200 with different layout structures in the display substrate 101.

[0083] In some embodiments, the sub-electrodes 201 of each pixel electrode 200 can be strip-shaped electrodes, and the number of the multiple sub-electrodes 201 of one pixel electrode 200 can be three, four or even more, preferably three. These sub-electrodes 201 can be arranged in parallel with equal spacing, and the target direction in this case can refer to the width of the sub-electrodes 201. As described above, the spacing or the width between the sub-electrodes 201 of the pixel electrode 200 can be changed, or both can be changed, to form different layout structures of the pixel electrodes 200.

[0084] In yet some embodiments, the sub-electrodes 201 of each pixel electrode 200 can also be square electrodes, and as such, the number of the sub-electrodes 201 of one pixel electrode 200 can be three, four or even more, and these square sub-electrodes 201 can also be arranged equidistantly, and the size of the target direction can refer to the side length of the sub-electrodes 201.

[0085] In which, the shape and size of the sub-electrodes 201 included in each pixel electrode 200 can be the same to simplify the process difficulty, and as shown in Figure 3 for example, if the sub-electrodes 201 are strips, then the sub-electrodes 201 included in one pixel electrode 200 are all rectangular strips with consistent size, and are arranged equidistantly and in parallel on the first passivation layer.

[0086] In which, since there are at least two layout structures, then in all pixel electrodes 200, the number of pixel electrodes 200 under each layout structure can be multiple, and as an example, a part of the pixel electrodes 200 belong to one layout structure 1, a part of the pixel electrodes 200 belong to layout structure 2, and a part of the pixel electrodes 200 belong to layout structure 3.

[0087] In which, for the pixel electrodes 200 with different layout structures, the size of the target direction of the sub-electrodes 201 is different from each other, or the spacing between the sub-electrodes 201 is different from each other, or both the spacing and the size of the target direction of the sub-electrodes 201 are different. For the pixel electrodes 200 with the same layout structure, the spacing between the sub-electrodes 201 and the size of the target direction can be the same, or can at least meet the same condition.

[0088] As shown in Figure 3 for example, as shown in the left and right pixel electrodes 200, the spacing and width of the sub-electrodes 201 in the left pixel electrode 200 are different from the spacing and width of the sub-electrodes 201 in the right pixel electrode 200.

[0089] As shown in Figures 4-6 for example, as shown in the layout structure design schematic diagram of the pixel electrodes 200 shown in the top view of the display substrate 101, as shown in Figure 4 for example, the pixel electrodes 200 include three layout structures, in which, the size S of the sub-electrodes 201 in the pixel electrodes 200 with different layout structures is the same in the target direction, and the spacing W between the sub-electrodes 201 in the pixel electrodes 200 is different, such as including three spacings W1, W2 and W3.

[0090] As shown in Figure 5As shown, the pixel electrodes 200 include three layout structures, wherein the size S of the sub-electrodes 201 in the target direction of the pixel electrodes 200 with different layout structures is different, while the spacing W between the sub-electrodes 201 in the pixel electrodes 200 is the same, such as including three sizes S1, S2 and S3.

[0091] like Figure 6 As shown, the pixel electrodes 200 include three layout structures, wherein the size S of the sub-electrodes 201 in the target direction of the pixel electrodes 200 with different layout structures is different, and the spacing W between the sub-electrodes 201 in the pixel electrodes 200 is different, such as including three combinations (W1, S1), (W2, S3) and (W3, S3).

[0092] In this embodiment, the sub-electrodes 201 of each pixel electrode 200 may be strip electrodes, the pitch between the sub-electrodes 201 is 2.7-4.3 μm, and the dimension in the target direction, ie, the width, is 1.7-3.3 μm.

[0093] Use Figure 3 In the display substrate 101 shown, when a voltage is applied to the source of the thin-film transistor via a data line, and when the gate line turns on the thin-film transistor, the voltage is applied to the multiple sub-electrodes 201 of the pixel electrode 200 through the thin-film transistor. Under the interaction of the multiple sub-electrodes 201 and the common electrode, an electric field is provided for the liquid crystal molecules. Since there are at least two layout structures for the pixel electrode 200, there are at least two types of sub-electrode 201 spacing designs, at least two types of sub-electrode 201 size designs, or at least two types of sub-electrode 201 size and spacing designs. The spacing and size of the sub-electrodes 201 affect the persistence, stability, and intensity of the generated electric field. Therefore, different spacing and / or sizes of the sub-electrodes 201 can compensate for differences in the generated electric field. For example, if one type of pixel electrode 200 generates a stronger electric field, while another type of pixel electrode 200 generates a weaker electric field, the stronger electric field can compensate for the weaker electric field. The strength of the electric field affects the deflection of the liquid crystal molecules, which in turn affects the overall light transmittance of the display panel.

[0094] Therefore, after the pixel electrode 200 with at least two layout structures is adopted, the layout structures of the pixel electrode 200 of different display panels each have at least two, even if process fluctuation occurs, and process differences in the size and spacing of the sub-electrode 201 between the display panels are caused, the differences can be compensated by the pixel electrode 200 with different layout structures inside the display substrate 101, so that the transmittance difference between the display panels is significantly reduced, so that the display brightness between the display panels will not be greatly different due to the process fluctuation. In actual production, the process flow can be allowed to be improved without fine improvement, thereby reducing the production cost and improving the yield of the display substrate 101.

[0095] In some embodiments, the sub-electrode 201 can be a strip-shaped sub-electrode 201, and the sub-electrodes 201 are arranged in parallel in the plane direction of the display substrate 101. The size of the sub-electrode 201 in the target direction can refer to the size in the short edge direction, that is, the width.

[0096] As described in the above embodiments, the layout structure can include the spacing between the sub-electrodes 201 and the size of the sub-electrode 201. In the case of a strip-shaped electrode, in some embodiments, different layout structures can be realized by changing the spacing without changing the width; or different layout structures can be realized by changing the width without changing the spacing.

[0097] Correspondingly, between the pixel electrodes 200 with different layout structures, the size of the sub-electrode 201 is the same and the spacing between the sub-electrodes 201 is different; or the spacing between the sub-electrodes 201 is the same and the size of the sub-electrode 201 is different.

[0098] In this embodiment, one design method is that the widths of the sub-electrodes 201 of all pixel electrodes 200 are the same, and at least two different layout structures are achieved by changing the spacing of the sub-electrodes 201, as shown in FIG. 2B. Figure 4 Specifically, for the pixel electrodes 200 with different layout structures, the sizes of the orthographic projections of the sub-electrodes 201 on the substrate 101 are the same, such as the width and length being the same, and the spacing between the orthographic projections of the sub-electrodes 201 on the substrate 101 is different.

[0099] Another design method is that the spacing of the sub-electrodes 201 of all pixel electrodes 200 is the same, and at least two different layout structures are achieved by changing the width of the sub-electrode 201, as shown in FIG. 2C. Figure 5As shown in FIG. 6, the pixel electrode 200 is designed in such a way that the width of the orthographic projection of the sub-electrode 201 on the substrate 101 is different for different layout structures of the pixel electrode 200, and the spacing between the orthographic projections of the sub-electrodes 201 on the substrate 101 is the same.

[0100] By changing the spacing alone or changing the width of the sub-electrode 201 alone, at least two different layout structures can be achieved, and the difference between the electric fields generated under the same voltage can be compensated to compensate for the difference between the light transmittances.

[0101] In some embodiments, different layout structures can be achieved by changing the spacing and the width simultaneously, and the size of the sub-electrode 201 and the spacing between the sub-electrodes 201 are different between the pixel electrodes 200 of different layout structures. As shown in FIG. 7, the pixel electrode 200 is designed in such a way that the size of the orthographic projection of the sub-electrode 201 on the substrate 101 is different for different layout structures of the pixel electrode 200, e.g., the length is the same but the width is different, and the spacing between the orthographic projections of the sub-electrodes 201 on the substrate 101 is also different. Figure 6 and Figure 3 As shown in FIG. 7, the pixel electrode 200 is designed in such a way that the size of the orthographic projection of the sub-electrode 201 on the substrate 101 is different for different layout structures of the pixel electrode 200, e.g., the length is the same but the width is different, and the spacing between the orthographic projections of the sub-electrodes 201 on the substrate 101 is also different.

[0102] By changing the spacing and the width simultaneously, at least two different layout structures can be achieved, and the difference between the electric fields generated under the same voltage can be compensated to a greater extent, thereby reducing the difference between the light transmittances.

[0103] Next, the arrangement of the pixel electrodes 200 with different layout structures on the substrate 101 is described again.

[0104] In some embodiments, to reduce the difference in display brightness between different pixel units under the same voltage and improve the uniformity of the display brightness in different regions, the pixel electrodes 200 with different layout structures can be arranged in an interleaved manner on the substrate 101. The interleaved arrangement can mean that the pixel electrodes 200 of the same layout structure are spaced apart by the pixel electrodes 200 of different layout structures, so that the electric fields generated by each other can be compensated under the same voltage of the data line, i.e., the difference in deflection of the liquid crystal molecules is compensated, to achieve the uniformity of the display brightness. As shown in FIG. 8, the pixel electrodes 200 are arranged in an interleaved manner. Figures 4-6 As shown in FIG. 8, the pixel electrodes 200 are arranged in an interleaved manner.

[0105] The interleaved arrangement can also mean that the pixel electrodes 200 of one layout structure form the peripheral electrode ring of the pixel electrodes 200 of another layout structure, as shown in FIG. 9. Figure 7aAs shown in FIG. 1, a top view of an embodiment of the display substrate 101 is shown. As shown, the pixel electrodes 200 are arranged in an interleaved manner. As can be seen, the pixel electrodes 200 of one layout structure A form an electrode ring, which surrounds the pixel electrodes 200 of another layout structure B, which are in turn surrounded by another electrode ring of the layout structure B.

[0106] Another arrangement of the interleaved layout can also refer to that the display substrate 101 is divided into a plurality of regions, and the pixel electrodes 200 in each region are of one layout structure, and the pixel electrodes 200 of different layout structures are arranged between adjacent regions. As shown in FIG. 2, a top view of an embodiment of the display substrate 101 is shown. As shown, the display substrate 101 is divided into a plurality of regions at random, and the pixel electrodes 200 of different layout structures are arranged in adjacent regions. Figure 7b

[0107] In addition, in some other embodiments, the interleaved arrangement can also include that the pixel electrodes 200 of a plurality of layout structures are arranged in a periodic interleaved manner. For example, three layout structures are included, and two adjacent pixel units of the pixel unit of the layout structure 1 are of the layout structure 2, and two adjacent pixel units of the pixel unit of the layout structure 2 are of the layout structure 1.

[0108] In this embodiment, the plurality of pixel electrodes 200 can be arranged in an array on the substrate 101. In this case, the following arrangements of the embodiments are exemplarily shown:

[0109] In some embodiment #1, referring to Figure 7c and Figure 7d As shown in FIG. 3, a top view of an embodiment of the display substrate 101 is shown. As shown, the plurality of pixel electrodes 200 are arranged in an array. In particular, the pixel electrodes 200 of the same layout structure are arranged in columns or rows on the substrate 101.

[0110] In particular, the pixel electrodes 200 of one layout structure and the pixel electrodes 200 of another different layout structure are arranged in columns or rows alternately on the substrate 101. As shown in FIG. 4, the pixel electrodes 200 of the same layout structure are arranged in a row on the substrate 101, and the pixel electrodes 200 of different layout structures are arranged in rows alternately on the substrate 101, that is, the pixel electrodes 200 of the layout structure A and the pixel electrodes 200 of the layout structure B are adjacent in two rows. Figure 7c Figure 7d As shown in FIG. 5, the pixel electrodes 200 of the same layout structure can be arranged in a column on the substrate 101, and the pixel electrodes 200 of different layout structures are arranged in columns alternately on the substrate 101, that is, the pixel electrodes 200 of the layout structure A and the pixel electrodes 200 of the layout structure B are adjacent in two columns.

[0111] ​​In some embodiments #2, the pixel electrodes 200 having one layout structure are arranged in a plurality of columns, or the pixel electrodes 200 having one layout structure are arranged in a plurality of rows. In other words, the pixel electrodes 200 having one layout structure in each target number of columns are adjacent to the pixel electrodes 200 having another layout structure in each target number of columns; Figure 7e As shown, in the array arrangement of pixel electrodes 200, the pixel electrodes 200 of layout structure A can be arranged in 3 consecutive columns, and the pixel electrodes 200 of layout structure B can be arranged in 3 consecutive columns, and every 3 columns of pixel electrodes 200 of layout structure A are adjacent to every 3 columns of pixel electrodes 200 of layout structure B.

[0112] In some embodiments #3, a pixel electrode 200 is adjacent to at least one pixel electrode 200 having a different layout structure. Figure 7f As shown, specifically, in each row of pixel electrodes 200 , the layout structures of every two adjacent pixel electrodes 200 are different, and in each column of pixel electrodes 200 , the layout structures of every two adjacent pixel electrodes 200 are also different.

[0113] The following describes several specific layout structures:

[0114] In some embodiments #3, the layout structure may refer to the size and spacing of the sub-electrodes 201. Specifically, the sub-electrode 201 of each pixel electrode 200 is a strip electrode and the multiple strip-shaped sub-electrodes 201 of each pixel electrode 200 are arranged in parallel and at equal intervals. The size of the sub-electrode 201 may refer to the width of the sub-electrode 201, that is, the width in the short side direction.

[0115] Specifically, two layout structures may be included. In one layout structure, the spacing between the sub-electrodes 201 is small and the size is large; in the other layout structure, the spacing between the sub-electrodes 201 is large and the size is small. Figure 6 That is, the spacing between the sub-electrodes 201 in one layout structure is smaller than the spacing between the sub-electrodes 201 in another layout structure, and the size of the sub-electrodes 201 in one layout structure is larger than the size of the sub-electrodes 201 in another layout structure. Under this layout structure design, the ratio of the spacing to the size of the pixel electrodes 200 in different layout structures can be different.

[0116] In the present disclosure, this ratio can be characterized by a structural parameter, that is, a layout structure can be characterized by a structural parameter. In a specific implementation, the layout structure of the plurality of pixel electrodes 200 includes a first layout structure and a second layout structure, wherein the structural parameter corresponding to the first layout structure is greater than 1, and the structural parameter corresponding to the second layout structure is less than 1;

[0117] The structural parameter may be: the ratio of the spacing between two adjacent sub-electrodes 201 to the size of the sub-electrode 201 . When the sub-electrode 201 is a strip electrode, the structural parameter may refer to the ratio of the spacing to the width of the sub-electrode 201 .

[0118] The values ​​of the structural parameters corresponding to the two layout structures included in Example #3 may be as follows:

[0119] In a specific example 1, the structural parameter corresponding to the first layout structure is greater than or equal to 1.4 and less than or equal to 2, preferably, it can be 1.4, for example, the spacing of the sub-electrodes 201 can be 3.5μm, and the width of the sub-electrodes 201 can be 2.5μm.

[0120] In which, when the structural parameter corresponding to the first layout structure is greater than 1, there may be multiple pixel electrodes 200 with structural parameters greater than 1. Among these multiple pixel electrodes 200 with the first layout structure, different pixel electrodes 200 may correspond to the same or different structural parameters.

[0121] For example, there are 20 pixel electrodes 200 corresponding to the first layout structure, and the corresponding structural parameters are all greater than 1. Specifically, the structural parameters corresponding to each of the 20 pixel electrodes 200 can be the same, such as all 1.4; or, the 20 pixel electrodes 200 correspond to multiple structural parameters greater than 1, such as the structural parameters of some pixel electrodes 200 are 1.4, and the structural parameters of other pixel electrodes 200 are 1.7, or the structural parameters corresponding to the 20 pixel electrodes 200 are different, but they are all distributed in the range greater than or equal to 1.4 and less than or equal to 2. Of course, a preferred example is that multiple pixel electrodes 200 with the first layout structure correspond to the same structural parameters, which not only simplifies the manufacturing process, but also achieves a better compensation effect when compensating for the difference in electric field between pixel electrodes 200 with different layout structures.

[0122] In a specific example 2, the structural parameter corresponding to the second layout structure is greater than or equal to 0.5 and less than or equal to 0.71. Preferably, it can be 0.71. For example, the pitch of the sub-electrodes 201 can be 2.5 μm, and the width of the sub-electrodes 201 can be 3.5 μm.

[0123] In which, when the structural parameter corresponding to the second layout structure is less than 1, there may be multiple pixel electrodes 200 with structural parameters less than 1. Among these multiple pixel electrodes 200 with the second layout structure, different pixel electrodes 200 may correspond to the same or different structural parameters.

[0124] For example, 30 pixel electrodes 200 correspond to the second layout structure, and the corresponding structure parameters are all less than 1. Specifically, the structure parameters of the 30 pixel electrodes 200 can be the same, for example, all being 0.71; or the structure parameters of the 30 pixel electrodes 200 are less than 1, for example, the structure parameters of some pixel electrodes 200 are 0.5, the structure parameters of other pixel electrodes 200 are 0.71, or the structure parameters of the 30 pixel electrodes 200 are different, but all are distributed in the range of greater than or equal to 0.5 and less than or equal to 0.71.

[0125] In another specific example 3, the structure parameter corresponding to the first layout structure and the structure parameter corresponding to the second layout structure can be reciprocals of each other; that is, the distance between the sub-electrodes 201 of the pixel electrodes 200 with the first layout structure is the same as the size of the sub-electrodes 201 of the pixel electrodes 200 with the second layout structure; and the size of the sub-electrodes 201 of the pixel electrodes 200 with the first layout structure is the same as the distance between the sub-electrodes 201 of the pixel electrodes 200 with the second layout structure.

[0126] In this example 3, the structure parameter corresponding to the first layout structure can be 1.4, and the structure parameter corresponding to the second layout structure can be 0.71. For example, the distance between the sub-electrodes 201 of the pixel electrodes 200 with the first layout structure is 3.5 μm, and the width of the sub-electrodes 201 is 2.5 μm. The distance between the sub-electrodes 201 of the pixel electrodes 200 with the first layout structure is 2.5 μm, and the width of the sub-electrodes 201 is 3.5 μm. Of course, in this example 3, the multiple pixel electrodes 200 with the first layout structure correspond to the same structure parameter 1.4, and the multiple pixel electrodes 200 with the second layout structure correspond to the same structure parameter 0.71.

[0127] In the specific example 3, the inventors tested and compared three display panels manufactured according to the related art under the design of the pixel electrodes 200, and the comparison results are shown in Figure 8a , Figure 8b and Figure 8c

[0128] Among them, Figure 8a is the Gamma curve between the display panels manufactured by only designing the pixel electrodes according to the structure parameter 1.4, i.e., the distance between the sub-electrodes is 3.5 μm, and the width of the sub-electrodes is 2.5 μm, Figure 8b is the Gamma curve between the display panels manufactured by only designing the pixel electrodes according to the structure parameter 0.71 in the related art, i.e., the distance between the sub-electrodes is 2.5 μm, and the width of the sub-electrodes is 3.5 μm, Figure 8c ​is the design of two pixel electrodes in the present disclosure according to example 3, the Gamma curve between the manufactured display panels.

[0129] As shown in Figure 8a , the designed pixel electrode structure parameter is 3.5 / 2.5, but due to the process fluctuation, three display panels appear three different structure parameters of 3.5 / 2.5, 3.3 / 2.7 and 3.7 / 2.3, it can be seen that the Gamma curves of the three display panels are different, which makes the display brightness of the three display panels on high-order gray level have large difference, and the yield is not high.

[0130] As shown in Figure 8b , the designed pixel electrode structure parameter is 2.5 / 3.5, but due to the process fluctuation, three display panels appear three different structure parameters of 2.5 / 3.5, 2.7 / 3.3 and 2.3 / 3.7, it can be seen that the Gamma curves of the three display panels are different, which makes the display brightness of the three display panels on high-order gray level have large difference, and the yield is not high.

[0131] As shown in Figure 8a and Figure 8b , under the design of single layout structure and structure parameter less than 1, the distance is reduced, and the Gamma value is offset to high; the distance is increased, and the Gamma value is offset to low; and under the design of structure parameter greater than 1, the distance is reduced, and the Gamma value is offset to low; the distance is increased, and the Gamma value is offset to high.

[0132] As shown in Figure 8c , by designing two layout structures, and the structure parameter of one layout structure is greater than 1, and the structure parameter of the other layout structure is less than 1, the Gamma curves of the three display panels have little difference, and almost coincide, that is, even if the process fluctuation causes the error of the distance and size to be within 0.2 μm, the display brightness difference between the display panels is not large, and the yield is improved. Figure 8c

[0133] In some example #3, three layout structures can also be included, in which the distance between the sub-electrodes in one layout structure is small and the size is large; in another layout structure, the distance between the sub-electrodes is large and the size is small; and in the remaining one layout structure, the distance and size between the sub-electrodes are between the distance and size corresponding to the first two layout structures.

[0134] In this example #3, in addition to the above-mentioned first layout structure and second layout structure, a third layout structure can also be included, and the corresponding structure parameter of the third layout structure is different from the respective corresponding structure parameters of the first layout structure and the second layout structure. ​

[0135] In a specific example 4, the structural parameter corresponding to the third pixel electrode of the third layout structure may be 1; alternatively, among the pixel electrodes having the third layout structure, at least one third pixel electrode has a structural parameter corresponding to 1, i.e., the spacing and size between the sub-electrodes are the same. Specifically, the structural parameters of multiple third pixel electrodes having the third layout structure may all be 1.

[0136] In this embodiment #3, when the display substrate has pixel electrodes with three or more layout structures, the arrangement of the pixel electrodes can be a cross arrangement of pixel electrodes with different layout structures. Specifically, the pixel electrodes with the same layout structure can be arranged in a row on the substrate, and the pixel electrodes with different layout structures can be arranged in a staggered manner by rows on the substrate. Alternatively, the pixel electrodes with the same layout structure can be arranged in a column on the substrate, and the pixel electrodes with different layout structures can be arranged in a staggered manner by columns on the substrate. Figure 7g As shown, it is a schematic diagram of the top view arrangement of pixel electrodes of three layout structures, wherein the third layout structure is Figure 7g The structure shown in C is shown in the figure.

[0137] Next, a specific embodiment #4 of a display substrate is provided. In this embodiment #4, the display substrate includes:

[0138] substrate;

[0139] A gate line is provided on the substrate;

[0140] a gate insulating layer, disposed on the gate line and the exposed substrate;

[0141] A common electrode line is provided on the gate insulating layer;

[0142] A data line is provided on the gate insulating layer and crosses the gate line;

[0143] A plurality of spaced-apart thin film transistors are disposed on the gate insulating layer, wherein the source of each thin film transistor is connected to the data line, and the gate is connected to the gate line;

[0144] A first passivation layer 103 is provided on a side of the thin film transistor 108 facing away from the substrate 101 and has openings therein for the common electrode 300 and the pixel electrode 200 to pass through;

[0145] A plurality of pixel electrodes 200, the pixel electrodes 200 being spaced apart and disposed on a side of the thin film transistor 108 facing away from the substrate 101, and the pixel electrodes 200 comprising a plurality of sub-electrodes 201 being located on a side of the first passivation layer 103 facing away from the substrate 101; the plurality of sub-electrodes being strip-shaped and arranged in parallel and at equal intervals;

[0146] A second passivation layer 104 is disposed on the side of the pixel electrode 200 facing away from the substrate 101, and the orthogonal projection of the second passivation layer 104 on the substrate 101 does not overlap with the orthogonal projection of the sub-electrode 201 on the substrate 101.

[0147] A common electrode 300 is disposed on the side of the second passivation layer 104 facing away from the substrate 101, and directly overlaps with the common electrode line 106 through the opening in the second passivation layer 104 and the first passivation layer 103; wherein the common electrode 300 is in a planar form and connected with the common electrode line 106.

[0148] An alignment layer 105 is disposed on the side of the common electrode 300 facing away from the substrate 101, for orienting the liquid crystal molecules.

[0149] Some of the plurality of pixel electrodes 200 have a first layout structure, and the remaining pixel electrodes 200 have a second layout structure; the values of the structural parameters of the first layout structure are as follows: the interval is 3.5 μm, and the width of the sub-electrode 201 is 2.5 μm; the values of the structural parameters of the second layout structure are as follows: the interval is 2.5 μm, and the width of the sub-electrode 201 is 3.5 μm; wherein the arrangement mode of the pixel electrode 200 is as shown in Figure 7d The above is done to facilitate the process and improve the efficiency.

[0150] Based on the same inventive concept, the disclosure also provides a display panel, comprising an opposed substrate, and the display substrate as described above, and a liquid crystal layer filled between the display substrate and the opposed substrate.

[0151] As shown in Figure 9 As shown in Figure 9 As shown in Figure 3 As shown in the display substrate, and the opposed substrate, the opposed substrate comprises an alignment layer 105, a light shielding layer 109 disposed on the alignment layer 105, the light shielding layer 109 comprising a black matrix 1091, the orthogonal projection of the black matrix 1091 on the substrate 101 covering the thin film transistor 108, and the orthogonal projection of the opening between the black matrix 1091 on the substrate 101 being located in the orthogonal projection of the pixel electrode 200 on the substrate 101; an encapsulation layer 110 on the light shielding layer 109, the encapsulation layer 110 can comprise a color filter layer.

[0152] After the opposed substrate and the display substrate are aligned, a liquid crystal layer 400 is filled between the opposed substrate and the display substrate, thereby forming a display panel.

[0153] The display panel provided by the present disclosure has at least two layout structures of the pixel electrode, and even if the process difference of the size and the spacing of the sub-electrode between the display panels is caused by the process fluctuation, the layout structures of the pixel electrode with different layout structures can compensate for the difference inside the display substrate, so that the transmittance difference between the display panels is significantly reduced, and the display brightness between the display panels will not be greatly different due to the process fluctuation. In actual production, the production cost can be reduced and the yield of the display substrate can be improved without fine improvement of the process flow.

[0154] Based on the same inventive concept, the present disclosure further provides a preparation method of a display substrate. Figure 10 As shown in FIG. 6, a step flow diagram of the preparation method of the display substrate is shown, which can specifically include the following steps: Figure 1 As shown in FIG. 6, a step flow diagram of the preparation method of the display substrate is shown, which can specifically include the following steps:

[0155] Step S1: providing a substrate;

[0156] Step S2: forming a plurality of thin film transistors on the substrate;

[0157] Step S3: forming a pixel electrode with at least two different layout structures on the plurality of thin film transistors, wherein the pixel electrode includes a plurality of strip-shaped sub-electrodes.

[0158] The layout structure includes the spacing between the sub-electrodes and / or the size of the sub-electrode in the target direction, and the target direction is the direction of one sub-electrode to the adjacent sub-electrode.

[0159] In the embodiment, the substrate 101 can include gate lines 107 arranged in rows on the substrate 101; the process of forming a plurality of thin film transistors on the substrate 101 can be: forming a gate insulating layer 102 on the substrate 101, forming a common electrode line 106 and a data line on the gate insulating layer 102, wherein the data line is arranged in columns and is used to form a thin film transistor 108 in the region where the data line crosses the gate line 107.

[0160] First, the gate of the thin film transistor 108 is formed on the gate insulating layer 102, and the drain and the source are formed on the side of the source of the thin film transistor 108 away from the substrate 101, and the source is overlapped with the data line, so that the voltage applied to the gate line 107 is used to turn on or turn off the thin film transistor 108.

[0161] One thin film transistor 108 is used to control the pixel voltage of one sub-pixel.

[0162] A first passivation layer 103 is formed on the side of the thin film transistor 108 facing away from the substrate 101. The first passivation layer 103 is patterned and has openings for subsequent pixel electrodes to pass through.

[0163] When forming pixel electrodes 200 of at least two layout structures, the pixel electrodes 200 of the first layout structure may be formed first with each alternate row of thin film transistors 108. Figure 7c As shown, a pixel electrode of a first layout structure can be formed on the side of the drain of the corresponding thin film transistor 108 away from the substrate 101. The pixel electrode is strip-shaped and arranged in parallel with equal spacing. The sub-electrodes of the pixel electrode of the first layout structure have a spacing of 3.5 microns and a width of 2.5 microns. Then, a pixel electrode of a second layout structure is formed on the side of the drain of the remaining thin film transistor 108 away from the substrate. The pixel electrode is strip-shaped and arranged in parallel with equal spacing. The sub-electrodes of the pixel electrode of the second layout structure have a spacing of 2.5 microns and a width of 3.5 microns. In this way, a pixel electrode of a first layout structure can be formed. Figure 7c The plan layout shown;

[0164] Of course, in some other planar layouts, the pixel electrode 200 can be formed by referring to the above process;

[0165] Next, a second passivation layer 104 is formed on the side of the pixel electrode 200 facing away from the substrate 101, and a common electrode 300 is formed on the side of the second passivation layer 104 facing away from the substrate 101. The common electrode 300 is directly connected to the common electrode line 106 through openings formed in the second passivation layer 104 and the first passivation layer 103.

[0166] An alignment layer 105 is formed on the side of the second passivation layer 104 facing away from the substrate 101;

[0167] In this way, the display substrate is manufactured.

[0168] By adopting the manufacturing method of the above embodiment, since pixel electrodes with at least two layout structures are manufactured, the layout structures of the pixel electrodes of different display panels have at least two types. Even if there are process fluctuations, which cause process differences in the size and spacing of the sub-electrodes between the display panels, the pixel electrodes with different layout structures can compensate for the differences inside the display substrate, thereby significantly reducing the transmittance differences between the display panels. In this way, the display brightness between the display panels will no longer show large differences due to process fluctuations. In actual production, the existing process can be used for the process flow, and there is no need to pay too much attention to process fluctuations, thereby reducing production costs and improving the yield of the display substrate.

[0169] Based on the same inventive concept, the present disclosure also provides an electronic device, which may include the above-mentioned display substrate or display device.

[0170] Finally, it should be noted that "first", "second", and similar terms are used herein, unless otherwise defined, to connote "order of importance" or "order of consideration" and do not imply a required order of occurrence, rather, these terms are used to distinguish one element from another. Also, the terms "comprise", "comprising", or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article or apparatus that comprises the element. The terms "connected" or "coupled" or similar terms as used herein, can relate to physical or mechanical connections, but can also relate various types of electrical connections, whether direct or indirect.

[0171] The display substrate, the manufacturing method of the display substrate and the display panel provided by the present disclosure are described in detail above, the principles and implementation manners of the present disclosure are described by applying specific examples in the present disclosure, the above description of the embodiments is only used to help understand the method of the present disclosure and the core idea thereof; meanwhile, according to the idea of the present disclosure, the specific implementation manners and application ranges can be changed by those skilled in the art, and the above description of the present disclosure should not be understood as a limitation.

[0172] Other embodiments of the present disclosure will be apparent to those skilled in the art upon consideration of the specification and practice of the present disclosure. The present disclosure is intended to cover any and all variations which come within the scope of the present disclosure, taking into account the normal equivalents used in the art and the ranges of values which exist for elements within the same. The specification and examples given are intended as illustrative only and not restrictive of the present disclosure. The true scope of the present disclosure is set forth in the claims which follow.

[0173] It should be understood that the present disclosure is not limited to the precise construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the present disclosure. The scope of the present disclosure is limited only by the claims that follow.

[0174] As used herein, the terms "one embodiment", "an embodiment” or "one or more embodiments” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0175] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0176] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word 'comprising' does not exclude the presence of elements or steps other than those listed in a claim. The word 'a' or 'an' preceding an element does not exclude the presence of a plurality of such elements. The disclosure can be implemented by means of both hardware and software, and any combination thereof. In a unitary claim, several devices, apparatuses or means can be listed, comprising means for carrying out a certain task. The use of the term'means' in a claim is intended to refer to a combination of means for performing a task, even if such means are not explicitly recited in the claim. The word 'first','second', 'third', etc. do not imply any order. The terms 'first','second', 'third', etc. are to be interpreted according to the context in which they are used.

[0177] It has to be noted that the above-mentioned embodiments illustrate rather than limit the application, since various modifications are possible within the scope of the appended claims. As such, the particular embodiments provided are meant to be illustrative only and not meant to be limiting as to the scope of the disclosure.

Claims

1. A display substrate, characterized in that: include: substrate; A plurality of pixel units are located on the substrate, and each of the pixel units includes a pixel electrode, and the pixel electrode includes a plurality of sub-electrodes that are evenly spaced; Among them, there are at least two different layout structures for the multiple pixel electrodes, and the layout structure includes the spacing between the sub-electrodes and / or the size of the sub-electrodes in the target direction, and the target direction is the direction of one sub-electrode toward another adjacent sub-electrode; wherein, the pixel electrodes with different layout structures are arranged alternately on the substrate.

2. The display substrate according to claim 1, wherein: Pixel electrodes with different layout structures have the same sub-electrode size and different spacing between sub-electrodes; or, pixel electrodes with different layout structures have the same sub-electrode spacing and different sub-electrode sizes.

3. The display substrate according to claim 1, wherein Pixel electrodes with different layout structures have different sub-electrode sizes and different intervals between the sub-electrodes.

4. The display substrate according to any one of claims 1 to 3, wherein: The layout structure includes a first layout structure and a second layout structure, the structure parameter corresponding to the first layout structure is greater than 1, and the structure parameter corresponding to the second layout structure is less than 1; The structural parameter is: the ratio of the distance between two adjacent sub-electrodes to the size of the sub-electrodes.

5. The display substrate according to claim 4, wherein: The spacing between the sub-electrodes of the pixel electrode with the first layout structure is the same as the size of the sub-electrodes of the pixel electrode with the second layout structure; and the size of the sub-electrodes of the pixel electrode with the first layout structure is the same as the spacing between the sub-electrodes of the pixel electrode with the second layout structure.

6. The display substrate according to claim 4, wherein: The structural parameter corresponding to the first layout structure is greater than or equal to 1.4 and less than or equal to 2.

7. The display substrate according to claim 4, wherein: The structural parameter corresponding to the second layout structure is greater than or equal to 0.5 and less than or equal to 0.

71.

8. The display substrate according to claim 4, wherein: Different pixel electrodes having the first layout structure correspond to the same or different structural parameters.

9. The display substrate according to claim 4, wherein: Different pixel electrodes having the second layout structure correspond to the same or different structural parameters.

10. The display substrate according to claim 4, wherein: The layout structure further includes a third layout structure, and the structural parameters corresponding to the third layout structure are different from the structural parameters corresponding to the first layout structure and the second layout structure.

11. The display substrate according to claim 10, wherein: The structural parameter corresponding to the pixel electrode having the third layout structure is 1.

12. The display substrate according to claim 1, wherein Pixel units with different layout structures are arranged alternately on the substrate.

13. The display substrate according to claim 1 or 12, wherein: A plurality of pixel electrodes are arranged in an array; wherein the pixel electrodes having the same layout structure are arranged in columns or rows on the substrate.

14. The display substrate according to claim 1 or 12, wherein: A plurality of pixel electrodes are arranged in an array; wherein pixel electrodes having one layout structure and pixel electrodes having another different layout structure are alternately arranged in columns or rows on the substrate.

15. The display substrate according to claim 14, wherein: Pixel electrodes with the same layout structure are continuously arranged in multiple columns, or pixel electrodes with the same layout structure are continuously arranged in multiple rows.

16. The display substrate according to claim 1 or 12, characterized in that: A pixel electrode of one layout structure is adjacent to at least one pixel electrode of a different layout structure.

17. The display substrate according to claim 1, wherein The sub-electrodes are in a strip shape, and a plurality of the sub-electrodes of each pixel electrode are arranged in parallel.

18. A method for preparing a display substrate, characterized in that: The method comprises: providing a substrate; forming a plurality of spaced-apart thin film transistors on the substrate; forming pixel electrodes having at least two different layout structures on the plurality of thin film transistors, wherein the pixel electrodes include a plurality of strip-shaped sub-electrodes; The layout structure includes the spacing between the sub-electrodes and / or the size of the sub-electrodes in the target direction, where the target direction is the direction from one sub-electrode toward another adjacent sub-electrode; and pixel electrodes with different layout structures are arranged alternately on the substrate.

19. A display panel, characterized in that: It comprises an opposing substrate and a display substrate according to any one of claims 1 to 17, wherein a liquid crystal layer is filled between the display substrate and the opposing substrate.

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